HomeSort by: relevance | last modified time | path
    Searched defs:DefRegs (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
LiveVariables.cpp 511 SmallVector<unsigned, 4> DefRegs;
533 DefRegs.push_back(MOReg);
552 for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
553 unsigned MOReg = DefRegs[i];
MachineCopyPropagation.cpp 91 SmallVector<MCRegister, 4> DefRegs;
126 RegsToInvalidate.insert(I->second.DefRegs.begin(),
127 I->second.DefRegs.end());
142 markRegsUnavailable(I->second.DefRegs, TRI);
169 if (!is_contained(Copy.DefRegs, Def))
170 Copy.DefRegs.push_back(Def);
194 if (CI->second.DefRegs.size() != 1)
196 MCRegUnitIterator RUI(CI->second.DefRegs[0], &TRI);
MachineOutliner.cpp 789 SmallSet<Register, 2> UseRegs, DefRegs;
807 // Introduce DefRegs set to skip the redundant register.
808 DefRegs.insert(MOP.getReg());
823 for (const Register &I : DefRegs)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonExpandCondsets.cpp 470 std::set<RegisterRef> DefRegs;
480 DefRegs.insert(Op);
500 if (!Op.isReg() || !DefRegs.count(Op))
HexagonConstPropagation.cpp 2848 SmallVector<unsigned,2> DefRegs;
2857 DefRegs.push_back(R);
2870 for (unsigned i = 0, n = DefRegs.size(); i < n; ++i) {
2871 unsigned R = DefRegs[i];
2962 AllDefs = (ChangedNum == DefRegs.size());
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelLowering.cpp 2429 DenseMap<Register, bool> DefRegs;
2432 DefRegs[MOp.getReg()] = true;
2437 if (!DefRegs[Reg])
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 10550 DenseMap<unsigned, bool> DefRegs;
10555 DefRegs[OI->getReg()] = true;
10570 if (!DefRegs[Reg])

Completed in 36 milliseconds