| /src/external/apache2/llvm/dist/clang/utils/TableGen/ |
| ClangDataCollectorsEmitter.cpp | 8 const auto &Defs = RK.getClasses();
9 for (const auto &Entry : Defs) {
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CTagsEmitter.cpp | 66 const auto &Defs = Records.getDefs();
69 Tags.reserve(Classes.size() + Defs.size());
72 for (const auto &D : Defs)
|
| CodeGenTarget.cpp | 623 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic");
624 Intrinsics.reserve(Defs.size());
626 for (unsigned I = 0, e = Defs.size(); I != e; ++I)
627 Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties));
|
| InstrInfoEmitter.cpp | 728 // Emit all of the instruction's implicit uses and defs.
729 Records.startTimer("Emit uses/defs");
737 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
738 if (!Defs.empty()) {
739 unsigned &IL = EmittedLists[Defs];
740 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
1003 // Emit the implicit uses and defs lists...
1010 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
|
| GICombinerEmitter.cpp | 168 /// (defs root:$root, apint:$constant)
281 /// is primarily useful for testing for defs and similar in DagInit's since
349 DagInit *Defs = TheDef.getValueAsDag("Defs");
351 if (Defs->getOperatorAsDef(TheDef.getLoc())->getName() != "defs") {
352 PrintError(TheDef.getLoc(), "Expected defs operator");
356 for (unsigned I = 0, E = Defs->getNumArgs(); I < E; ++I) {
358 if (isSpecificDef(*Defs->getArg(I), "root")) {
359 Roots.emplace_back(Defs->getArgNameStr(I))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIPostRABundler.cpp | 49 SmallSet<Register, 16> Defs;
83 for (Register Def : Defs)
140 assert(Defs.empty());
143 Defs.insert(I->defs().begin()->getReg());
155 Defs.insert(I->defs().begin()->getReg());
208 Defs.clear();
|
| SIFormMemoryClauses.cpp | 63 bool canBundle(const MachineInstr &MI, const RegUse &Defs,
66 void collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
67 bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
120 for (const MachineOperand &ResMO : MI.defs()) {
152 bool SIFormMemoryClauses::canBundle(const MachineInstr &MI, const RegUse &Defs,
154 // Check interference with defs.
170 const RegUse &Map = MO.isDef() ? Uses : Defs;
186 // Since all defs in the clause are early clobber we can run out of registers.
191 // NB: skip advanceBeforeNext() call. Since all defs will be marked
217 // Collect register defs and uses along with their lane masks and states
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonBitSimplify.cpp | 201 static void getInstrDefs(const MachineInstr &MI, RegisterSet &Defs);
271 RegisterSet Defs;
273 getInstrDefs(I, Defs);
275 NewAVs.insert(Defs);
290 RegisterSet &Defs) {
297 Defs.insert(R);
1471 RegisterSet Defs;
1476 Defs.clear();
1477 HBS::getInstrDefs(*I, Defs);
1478 if (Defs.count() != 1
[all...] |
| HexagonBlockRanges.cpp | 313 RegisterSet Defs, Clobbers;
333 // Process defs and clobbers.
334 Defs.clear();
346 Defs.insert(S);
365 if (!Defs.count(R))
369 // Defs and clobbers can overlap, e.g.
371 for (RegisterRef R : Defs)
374 // Update maps for defs.
375 for (RegisterRef S : Defs) {
376 // Defs should already be expanded into subregs
[all...] |
| HexagonRDFOpt.cpp | 256 NodeList Defs;
261 Defs = DFG.getRelatedRefs(IA, DA);
262 if (!llvm::all_of(Defs, IsDead))
267 // Mark all nodes in Defs for removal.
268 for (auto D : Defs)
|
| HexagonGenMux.cpp | 100 BitVector Defs, Uses;
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {}
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
158 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs,
160 // First, get the implicit defs and uses for this instruction.
165 expandReg(*R++, Defs);
170 // Look over all operands, and collect explicit defs and uses.
175 BitVector &Set = MO.isDef() ? Defs : Uses;
184 BitVector Defs(NR), Uses(NR);
189 Defs.reset()
[all...] |
| HexagonOptAddrMode.cpp | 217 NodeSet Visited, Defs;
218 const auto &P = LV->getAllReachingDefsRec(UR, UN, Visited, Defs);
221 dbgs() << "*** Unable to collect all reaching defs for use ***\n"
230 dbgs() << "*** Multiple Reaching Defs found!!! ***\n";
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCBoolRetToInt.cpp | 73 SmallPtrSet<Value *, 8> Defs;
76 Defs.insert(V);
84 if (Defs.insert(Op).second)
87 return Defs;
222 auto Defs = findAllDefs(U);
225 if (llvm::none_of(Defs, [](Value *V) { return isa<Instruction>(V); }))
231 for (Value *V : Defs)
236 for (Value *V : Defs)
247 for (Value *V : Defs)
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| MCInstrDescView.h | 208 SmallVector<RegisterOperandAssignment, 1> Defs; // Unlikely size() > 1.
211 // True is Defs and Use contain an Implicit Operand.
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 163 /// Defs, Uses - Remember where defs and uses of each register are as we
167 Reg2SUnitsMap Defs;
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 121 /// bundle, and it copies externally visible defs and uses to the BUNDLE
145 SmallVector<MachineOperand*, 4> Defs;
152 Defs.push_back(&MO);
177 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
178 MachineOperand &MO = *Defs[i];
205 Defs.clear();
291 // Both defs and uses can read virtual registers.
298 // Only defs can write.
|
| LiveVariables.cpp | 227 /// implicit defs to a machine instruction if there was an earlier def of its
442 SmallVectorImpl<unsigned> &Defs) {
481 Defs.push_back(Reg); // Remember this def.
485 SmallVectorImpl<unsigned> &Defs) {
486 while (!Defs.empty()) {
487 Register Reg = Defs.back();
488 Defs.pop_back();
499 SmallVectorImpl<unsigned> &Defs) {
551 // Process all defs.
557 HandlePhysRegDef(MOReg, &MI, Defs);
[all...] |
| MachineCopyPropagation.cpp | 82 STATISTIC(NumCopyBackwardPropagated, "Number of copy defs backward propagated");
469 for (const MachineOperand &MIDef : MI.defs()) {
666 SmallVector<Register, 2> Defs;
681 Defs.push_back(Reg.asMCReg());
720 // Any previous copy definition or reading the Defs is no longer available.
721 for (MCRegister Reg : Defs)
725 // If MBB doesn't have successors, delete the copies whose defs are not used.
726 // If MBB does have successors, then conservative assume the defs are live-out
|
| RDFLiveness.cpp | 81 // The order in the returned sequence is the order of reaching defs in the
85 // covered by the defs in the list (see FullChain).
87 // (1) Returning the sequence of reaching defs for a particular reference
89 // (2) Returning a partial sequence of reaching defs, where the final goal
90 // is to traverse past phi nodes to the actual defs arising from the code
116 // Dead defs will be treated as if they were live, since they are actually
124 // The initial queue should not have reaching defs for shadows. The
126 // is not aliased to the reaching defs of the related shadows.
137 // Collect all the reaching defs, going up until a phi node is encountered,
138 // or there are no more reaching defs. From this set, the actual set o
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 68 RegisterSet &Defs, RegisterSet &Uses);
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses,
106 InsertUsesDefs(LocalDefs, Defs);
138 RegisterSet &Defs, RegisterSet &Uses) {
152 if (Uses.count(DstReg) || Defs.count(SrcReg))
196 RegisterSet Defs, Uses;
209 Defs.clear();
211 TrackDefUses(MI, Defs, Uses, TRI);
252 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
262 TrackDefUses(NMI, Defs, Uses, TRI)
[all...] |
| A15SDOptimizer.cpp | 400 SmallVector<unsigned, 8> Defs;
409 Defs.push_back(MO.getReg());
411 return Defs;
593 SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
596 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
600 // we can end up with multiple defs of this DPR.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCChecker.cpp | 44 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
45 Defs[Hexagon::LC0].insert(Unconditional);
48 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
49 Defs[Hexagon::LC1].insert(Unconditional);
127 Defs[R].insert(PredSense(PredReg, isTrue));
134 // reset R to USR, since we know how to handle multiple defs of USR,
182 Defs[*SRI].insert(PredSense(PredReg, isTrue));
394 if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) {
407 if (LatePreds.count(P) > 1 || Defs.count(P))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86LoadValueInjectionLoadHardening.cpp | 388 // (2) The use can further propagate the Def'ed value to more defs
400 // uses to all defs unless the instruction is a call, in which
413 // traversing its defs (i.e., this load will become
417 // Check whether the use propagates to more defs.
431 // `Def` inherits all of its child defs' transmitters.
474 NodeList Defs = ArgPhi.Addr->members_if(DataFlowGraph::IsDef, DFG);
475 llvm::for_each(Defs, AnalyzeDef);
486 NodeList Defs = SA.Addr->members_if(DataFlowGraph::IsDef, DFG);
487 llvm::for_each(Defs, AnalyzeDef);
|
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| SafepointIRVerifier.cpp | 449 // This set contains defs of unrelocated pointers that are proved to be legal
452 // This set contains poisoned defs. They can be safely ignored during
491 /// Remove from Contribution all defs that legally produce unrelocated
502 /// simply the defs introduced by every dominating basic block and the
556 // Simulate the flow of defs through the CFG and recalculate AvailableIn/Out
572 // Poisoned defs are skipped since they are always safe by itself by
743 const auto &Defs = BBS->Contribution;
744 Result.insert(Defs.begin(), Defs.end());
841 // and unless we want to track all defs (not only gc pointers) the onl
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 115 /// This function sets all caller-saved registers in Defs.
118 /// This function sets all unallocatable registers in Defs.
136 BitVector Defs, Uses;
192 /// Update Defs and Uses. Return true if there exist dependences that
194 /// Defs.
202 SmallPtrSet<ValueType, 4> Uses, Defs;
345 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
351 // If MI is a call, add RA to Defs to prevent users of RA from going into
354 Defs.set(Mips::RA);
360 Defs.reset(Mips::AT)
[all...] |
