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    Searched defs:Div (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
DivRemPairs.cpp 33 #define DEBUG_TYPE "div-rem-pairs"
34 STATISTIC(NumPairs, "Number of div/rem pairs");
38 DEBUG_COUNTER(DRPCounter, "div-rem-pairs-transform",
39 "Controls transformations in div-rem-pairs pass");
58 Instruction *Div;
63 m_Instruction(Div)),
68 M.Key.SignedOp = Div->getOpcode() == Instruction::SDiv;
76 /// A thin wrapper to store two values that we matched as div-rem pair.
96 /// The type for this pair, identical for both the div and rem.
119 /// Find matching pairs of integer div/rem ops (they have the same numerator
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
BranchProbabilityInfo.cpp 440 uint32_t Div = static_cast<uint32_t>(
442 BP[I] = BranchProbability::getRaw(Div);
  /src/external/apache2/llvm/dist/llvm/lib/IR/
ConstantFold.cpp 1388 assert(!CI2->isZero() && "Div by zero handled above");
1391 assert(!CI2->isZero() && "Div by zero handled above");
1396 assert(!CI2->isZero() && "Div by zero handled above");
1399 assert(!CI2->isZero() && "Div by zero handled above");
2629 Constant *Div = ConstantExpr::getSDiv(CurrIdx, Factor);
2633 Div->getType()->getScalarSizeInBits());
2638 Type *ExtendedTy = Type::getIntNTy(Div->getContext(), CommonExtendedWidth);
2649 if (!Div->getType()->isIntOrIntVectorTy(CommonExtendedWidth))
2650 Div = ConstantExpr::getSExt(Div, ExtendedTy)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineMulDivRem.cpp 270 BinaryOperator *Div = dyn_cast<BinaryOperator>(Op0);
271 if (!Div || (Div->getOpcode() != Instruction::UDiv &&
272 Div->getOpcode() != Instruction::SDiv)) {
274 Div = dyn_cast<BinaryOperator>(Op1);
277 if (Div && Div->hasOneUse() &&
278 (Div->getOperand(1) == Y || Div->getOperand(1) == Neg) &&
279 (Div->getOpcode() == Instruction::UDiv |
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCodeGenPrepare.cpp 170 /// Expands 24 bit div or rem.
179 /// Expands 32 bit div or rem.
941 Value *Div = Builder.CreateAdd(IQ, JQ);
943 Value *Res = Div;
946 Value *Rem = Builder.CreateMul(Div, Den);
1259 for (BinaryOperator *Div : Div64ToExpand) {
1260 expandDivRem64(*Div);
AMDGPUISelLowering.cpp 33 "amdgpu-bypass-slow-div",
1746 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1749 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1756 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);
1760 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);
1764 return DAG.getMergeValues({ Div, Rem }, DL);
1795 SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(0), Zero});
1798 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
ScalarEvolutionExpander.cpp 312 const SCEV *Div = SE.getConstant(CI);
313 S = Div;
1927 // We can move insertion point only if there is no div or rem operations
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 11741 Register Div = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
11742 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::DIVD : PPC::DIVW), Div)
11747 .addReg(Div)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 4019 // If div is legal, it's better to do the normal expansion
4411 // speculative DIV must not cause a DIVREM conversion. We guard against this
4412 // by skipping the simplification if isIntDivCheap(). When div is not cheap,
4419 // If the equivalent Div node also exists, update its users.
14159 SDValue Div = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, Rsqrt, Y);
14160 AddToWorklist(Div.getNode());
14161 return DAG.getNode(ISD::FMUL, DL, VT, N0, Div);
21787 // restrict ops like integer div that have immediate UB (eg, div-by-zero)
22451 // when optimising for minimum size, we don't want to expand a div to a mu
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 10226 // SVE doesn't have i8 and i16 DIV operations; widen them to 32-bit
10234 llvm_unreachable("Unexpected Custom DIV operation");
17156 // optimizing for code size, we prefer to use a div instruction, as it is
17489 // Scalable vector i32/i64 DIV is supported.
17493 // Scalable vector i8/i16 DIV is not supported. Promote it to i32.
17499 // If this is not a full vector, extend, div, and truncate it.
17505 SDValue Div = DAG.getNode(Op.getOpcode(), dl, WidenedVT, Op0, Op1);
17506 return DAG.getNode(ISD::TRUNCATE, dl, VT, Div);
17521 // Convert back to fixed vectors so the DIV can be further lowered.
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 9366 "unexpected type for custom lowering DIV");
9444 "unexpected type for custom lowering DIV");
9473 "unexpected type for custom lowering DIV");
10025 assert(Subtarget->isTargetWindows() && "can only expand DIV on Windows");
18722 "Invalid opcode for Div/Rem lowering");
18729 // div = a / b
18730 // rem = a - b * div
18731 // return {div, rem}
18740 SDValue Div = DAG.getNode(DivOpcode, dl, VT, Dividend, Divisor);
18741 SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, Div, Divisor)
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