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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIFoldOperands.cpp 267 MachineOperand &Dst0 = MI->getOperand(0);
269 assert(Dst0.isDef() && Dst1.isDef());
273 const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg());
289 Dst0.setReg(NewReg0);
AMDGPUInstructionSelector.cpp 863 Register Dst0 = MI.getOperand(0).getReg();
866 LLT Ty = MRI->getType(Dst0);
886 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0)

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