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    Searched defs:DstOp (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrFoldTables.h 70 uint16_t DstOp;
X86MCInstLower.cpp 1803 const MachineOperand &DstOp = MI->getOperand(0);
1807 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
2167 const MachineOperand &DstOp = MI->getOperand(0);
2168 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2246 const MachineOperand &DstOp = MI->getOperand(0);
2247 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2355 const MachineOperand &DstOp = MI->getOperand(0);
2356 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ExpandSpecialInstrs.cpp 88 MachineOperand &DstOp = MI.getOperand(DstIdx);
90 DstOp.getReg(), R600::OQAP);
91 DstOp.setReg(R600::OQAP);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonRDFOpt.cpp 121 const MachineOperand &DstOp = MI->getOperand(0);
124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister");
125 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi),
127 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo),
138 const MachineOperand &DstOp = MI->getOperand(0);
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()),
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h 58 class DstOp {
67 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
68 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
69 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
70 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
71 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
96 llvm_unreachable("Unrecognised DstOp::DstType enum");
425 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
437 MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
449 MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MIRYamlMapping.h 493 unsigned DstOp;
496 return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
497 std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
506 YamlIO.mapRequired("dstop", Sub.DstOp);
  /src/external/apache2/llvm/dist/llvm/lib/Linker/
IRMover.cpp 1256 MDNode *DstOp;
1258 std::tie(DstOp, DstIndex) = Flags.lookup(ID);
1272 if (!DstOp) {
1280 mdconst::extract<ConstantInt>(DstOp->getOperand(0));
1292 SrcOp->getOperand(2) != DstOp->getOperand(2))
1318 Metadata *FlagOps[] = {DstOp->getOperand(0), ID, New};
1328 SrcOp->getOperand(2) != DstOp->getOperand(2)) {
1334 << *DstOp->getOperand(2) << "' from " << DstM.getModuleIdentifier()
1342 mdconst::extract<ConstantInt>(DstOp->getOperand(2));
1349 (DstBehaviorValue != Module::Max ? SrcOp : DstOp)->getOperand(0), ID
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineScheduler.cpp 1830 const MachineOperand &DstOp = Copy->getOperand(0);
1831 Register DstReg = DstOp.getReg();
1832 if (!Register::isVirtualRegister(DstReg) || DstOp.isDead())
MachineVerifier.cpp 1460 const MachineOperand &DstOp = MI->getOperand(0);
1464 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1679 const MachineOperand &DstOp = MI->getOperand(0);
1682 const Register DstReg = DstOp.getReg();
1724 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {

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