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    Searched defs:DstSize (Results 1 - 22 of 22) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PreLegalizerCombiner.cpp 41 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
42 if (DstSize != 32 && DstSize != 64)
AArch64PostLegalizerCombiner.cpp 68 unsigned DstSize = DstTy.getSizeInBits();
69 if (DstSize != 16 && DstSize != 32 && DstSize != 64)
AArch64InstructionSelector.cpp 777 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
782 (DstSize == SrcSize ||
785 (Register::isPhysicalRegister(SrcReg) && DstSize <= SrcSize) ||
789 (((DstSize + 31) / 32 == (SrcSize + 31) / 32) && DstSize > SrcSize)) &&
793 assert((DstSize <= 64 || DstBank.getID() == AArch64::FPRRegBankID) &&
837 unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
848 if (SrcRegBank != DstRegBank && (DstSize == 1 && SrcSize == 1))
849 SrcSize = DstSize = 32;
852 getMinClassForRegBank(DstRegBank, DstSize, true)}
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Linker/
LinkModules.cpp 194 uint64_t DstSize = DstDL.getTypeAllocSize(DstGV->getValueType());
202 LinkFromSrc = SrcSize > DstSize;
204 if (SrcSize != DstSize)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CallLowering.cpp 488 const unsigned DstSize = DstTy.getSizeInBits();
504 for (unsigned Size = DstSize * DstRegs.size(); Size != LCMSize;
505 Size += DstSize) {
InlineAsmLowering.cpp 252 unsigned DstSize = TRI->getRegSizeInBits(Dst, *MRI);
254 if (DstSize < SrcSize) {
260 if (DstSize > SrcSize) {
266 Src = MIRBuilder.buildAnyExt(LLT::scalar(DstSize), Src).getReg(0);
LegalizerHelper.cpp 1349 const int DstSize = DstTy.getSizeInBits();
1352 const int NumMerge = (DstSize + WideSize - 1) / WideSize;
1358 if (WideSize >= DstSize) {
1379 if (WideSize > DstSize)
1532 unsigned DstSize = DstTy.getSizeInBits();
1536 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I);
4011 const unsigned DstSize = DstTy.getSizeInBits();
4012 const LLT DstScalarTy = LLT::scalar(DstSize);
4026 const int NumRealParts = (DstSize + NarrowSize - 1) / NarrowSize;
4829 unsigned DstSize = Ty.getSizeInBits()
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizationArtifactCombiner.h 247 const unsigned DstSize = DstTy.getSizeInBits();
252 if (DstSize < MergeSrcSize) {
263 } else if (DstSize == MergeSrcSize) {
270 } else if (DstSize % MergeSrcSize == 0) {
281 const unsigned NumSrcs = DstSize / MergeSrcSize;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 745 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
749 DstSize = (DstSize + 1) / 2;
753 DstSize += 1;
755 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
759 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
765 if (DstSize != Info->VDataDwords) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstructionSelector.cpp 235 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
245 if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID &&
271 assert((DstSize == SrcSize ||
275 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) &&
282 DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize &&
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGCall.cpp 1136 /// with an in-memory size smaller than DstSize.
1140 uint64_t DstSize, CodeGenFunction &CGF) {
1152 if (FirstEltSize < DstSize &&
1162 return EnterStructPointerForCoercedAccess(SrcPtr, SrcSTy, DstSize, CGF);
1199 uint64_t DstSize = DL.getTypeSizeInBits(DestIntTy);
1201 if (SrcSize > DstSize) {
1202 Val = CGF.Builder.CreateLShr(Val, SrcSize - DstSize, "coerce.highbits");
1206 Val = CGF.Builder.CreateShl(Val, DstSize - SrcSize, "coerce.highbits");
1236 llvm::TypeSize DstSize = CGF.CGM.getDataLayout().getTypeAllocSize(Ty);
1240 DstSize.getFixedSize(), CGF)
    [all...]
CGExprScalar.cpp 1379 unsigned DstSize = DstTy->getPrimitiveSizeInBits();
1380 if (SrcSize == DstSize)
1406 if (SrcSize > DstSize)
  /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
TargetTransformInfoImpl.h 492 unsigned DstSize = Dst->getScalarSizeInBits();
493 if (DL.isLegalInteger(DstSize) &&
494 DstSize >= DL.getPointerTypeSizeInBits(Src))
506 TypeSize DstSize = DL.getTypeSizeInBits(Dst);
507 if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedSize()))
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
BasicTTIImpl.h 868 TypeSize DstSize = DstLT.second.getSizeInBits();
884 SrcSize == DstSize)
940 if (SrcLT.first == DstLT.first && SrcSize == DstSize) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 2265 unsigned DstSize = getRegSizeInBits(*DstRC);
2272 if (SrcSize <= 32 || DstSize <= 32)
2275 return NewSize <= DstSize || NewSize <= SrcSize;
AMDGPUInstructionSelector.cpp 465 unsigned DstSize = DstTy.getSizeInBits();
469 if (Offset % 32 != 0 || DstSize > 128)
474 if (DstSize == 16)
475 DstSize = 32;
488 DstSize / 32);
515 const unsigned DstSize = DstTy.getSizeInBits();
517 TRI.getRegClassForSizeOnBank(DstSize, *DstBank, *MRI);
553 const unsigned DstSize = DstTy.getSizeInBits();
566 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8);
707 unsigned DstSize = MRI->getType(DstReg).getSizeInBits()
    [all...]
AMDGPURegisterBankInfo.cpp 2483 unsigned DstSize = DstTy.getSizeInBits();
2485 const bool UseSel64 = DstSize > 32 &&
2497 if (DstSize > 32) {
2500 } else if (DstSize < 32) {
3575 unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
3578 OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize);
3586 unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
3588 OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize);
3597 unsigned DstSize = DstTy.getSizeInBits();
3603 OpdsMapping[0] = AMDGPU::getValueMapping(DstBankID, DstSize);
    [all...]
SIInstrInfo.cpp 2546 unsigned DstSize = RI.getRegSizeInBits(*DstRC);
2548 if (DstSize == 32) {
2565 if (DstSize == 64 && Pred == SCC_TRUE) {
2592 int NElts = DstSize / 32;
3953 uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32;
3954 if (RegCount > DstSize) {
SIISelLowering.cpp 11300 uint32_t DstSize = TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32;
11301 if (DstSize < InitIdx)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineVerifier.cpp 1173 unsigned DstSize = DstElTy.getSizeInBits();
1177 if (DstSize <= SrcSize)
1182 if (DstSize >= SrcSize)
1326 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1328 if (SrcSize == DstSize)
1331 if (DstSize + OffsetOp.getImm() > SrcSize)
1348 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1351 if (DstSize <= SrcSize)
1354 if (SrcSize + OffsetOp.getImm() > DstSize)
1702 unsigned DstSize = 0
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/IR/
Instructions.cpp 2863 unsigned DstSize = DstTy->getScalarSizeInBits();
2864 if (SrcSize == DstSize)
2866 else if (SrcSize < DstSize)
2874 // inttoptr, ptrtoint -> bitcast if SrcSize<=PtrSize and SrcSize==DstSize
2879 unsigned DstSize = DstTy->getScalarSizeInBits();
2880 if (SrcSize <= PtrSize && SrcSize == DstSize)
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineCasts.cpp 1241 unsigned DstSize = CI.getType()->getScalarSizeInBits();
1243 // SrcSize < DstSize: zext(a & mask)
1244 // SrcSize == DstSize: a & mask
1245 // SrcSize > DstSize: trunc(a) & mask
1246 if (SrcSize < DstSize) {
1253 if (SrcSize == DstSize) {
1258 if (SrcSize > DstSize) {
1260 APInt AndValue(APInt::getLowBitsSet(DstSize, MidSize));

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