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    Searched defs:DstVT (Results 1 - 16 of 16) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86SelectionDAGInfo.cpp 279 EVT DstVT = Dst.getValueType();
283 DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)),
X86FastISel.cpp 95 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
705 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
707 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
710 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
1245 EVT DstVT = VA.getValVT();
1247 if (SrcVT != DstVT) {
1254 assert(DstVT == MVT::i32 && "X86 should always ext to i32");
1266 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg);
1543 EVT DstVT = TLI.getValueType(DL, I->getType());
1544 if (!TLI.isTypeLegal(DstVT))
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X86ISelDAGToDAG.cpp 1211 MVT DstVT = N->getSimpleValueType(0);
1214 if (SrcVT.isVector() || DstVT.isVector())
1222 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
1238 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT;
1249 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store,
1267 MVT DstVT = N->getSimpleValueType(0);
1270 if (SrcVT.isVector() || DstVT.isVector())
1278 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
1294 MVT MemVT = (N->getOpcode() == ISD::STRICT_FP_ROUND) ? DstVT : SrcVT;
1323 SDVTList VTs = CurDAG->getVTList(DstVT, MVT::Other)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64TargetTransformInfo.cpp 876 auto DstVT = TLI->getValueType(DL, Dst);
883 if (!VecLT.second.isVector() || !TLI->isTypeLegal(DstVT))
889 if (DstVT.getFixedSizeInBits() < SrcVT.getFixedSizeInBits())
905 if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u)
AArch64ISelDAGToDAG.cpp 1273 EVT DstVT = N->getValueType(0);
1296 DstVT = MVT::i32;
1300 if (DstVT == MVT::i64)
1306 InsertTo64 = DstVT == MVT::i64;
1309 DstVT = MVT::i32;
1313 if (DstVT == MVT::i64)
1319 InsertTo64 = DstVT == MVT::i64;
1322 DstVT = MVT::i32;
1343 SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT,
AArch64ISelLowering.cpp 3319 EVT DstVT = Op.getValueType();
3323 uint64_t DstWidth = DstVT.getScalarSizeInBits();
3343 (DstVT == MVT::i64 || DstVT == MVT::i32))
15944 EVT DstVT = N->getValueType(0);
15945 SDVTList VTs = DAG.getVTList(DstVT, MVT::Other);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
Scalarizer.cpp 695 VectorType *DstVT = dyn_cast<VectorType>(BCI.getDestTy());
697 if (!DstVT || !SrcVT)
700 unsigned DstNumElems = cast<FixedVectorType>(DstVT)->getNumElements();
709 Res[I] = Builder.CreateBitCast(Op0[I], DstVT->getElementType(),
715 auto *MidTy = FixedVectorType::get(DstVT->getElementType(), FanOut);
741 Res[ResI] = Builder.CreateBitCast(V, DstVT->getElementType(),
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp 1359 EVT DstVT = TLI.getValueType(DL, I->getType());
1361 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1362 !DstVT.isSimple())
1367 if (!TLI.isTypeLegal(DstVT))
1379 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1407 MVT DstVT = DstEVT.getSimpleVT();
1414 if (SrcVT == DstVT) {
1416 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
1427 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0);
1782 EVT DstVT = TLI.getValueType(DL, I->getType())
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LegalizeIntegerTypes.cpp 4484 EVT DstVT = N->getValueType(0);
4485 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
4491 TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N), Chain);
4604 EVT DstVT = N->getValueType(0);
4605 RTLIB::Libcall LC = RTLIB::getUINTTOFP(Op.getValueType(), DstVT);
4611 TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N), Chain);
LegalizeVectorTypes.cpp 548 EVT DstVT = N->getValueType(0).getVectorElementType();
549 return DAG.getNode(N->getOpcode(), dl, DstVT, Src, N->getOperand(1));
4741 EVT DstVT = N->getValueType(0);
4749 DstVT.getVectorElementType(), WideNumElts);
4754 ISD::EXTRACT_SUBVECTOR, dl, DstVT, Res,
TargetLowering.cpp 663 EVT DstVT = Op.getValueType();
664 if (SrcVT == DstVT)
668 unsigned NumDstEltBits = DstVT.getScalarSizeInBits();
672 return DAG.getBitcast(DstVT, V);
694 return DAG.getBitcast(DstVT, V);
713 return DAG.getBitcast(DstVT, V);
812 EVT DstVT = Op.getValueType();
813 if (DemandedElts == 1 && DstVT.getSizeInBits() == SrcVT.getSizeInBits() &&
816 return DAG.getBitcast(DstVT, Src);
6660 EVT DstVT = Node->getValueType(0)
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DAGCombiner.cpp 551 SDValue foldSubToUSubSat(EVT DstVT, SDNode *N);
3153 // Attempt to create a USUBSAT(LHS, RHS) node with DstVT, performing a
3155 static SDValue getTruncatedUSUBSAT(EVT DstVT, EVT SrcVT, SDValue LHS,
3158 assert(DstVT.getScalarSizeInBits() <= SrcVT.getScalarSizeInBits() &&
3161 if (DstVT == SrcVT)
3162 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS);
3164 // If the LHS is zero-extended then we can perform the USUBSAT as DstVT by
3167 DstVT.getScalarSizeInBits());
3173 DstVT.getScalarSizeInBits()),
3176 RHS = DAG.getNode(ISD::TRUNCATE, DL, DstVT, RHS)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 1062 MVT DstVT;
1064 if (!isTypeLegal(DstTy, DstVT))
1067 if (DstVT != MVT::f32 && DstVT != MVT::f64)
1088 if (DstVT == MVT::f32)
1111 if (DstVT == MVT::f32 && !Subtarget->hasFPCVT())
1133 if (DstVT == MVT::f32)
1187 MVT DstVT, SrcVT;
1189 if (!isTypeLegal(DstTy, DstVT))
1192 if (DstVT != MVT::i32 && DstVT != MVT::i64
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PPCISelLowering.cpp 8053 EVT DstVT = Op.getValueType();
8062 if (DstVT == MVT::i32) {
8092 SDValue SignMask = DAG.getConstant(0x80000000, dl, DstVT);
8102 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), DstVT);
8109 Sel = DAG.getBoolExtOrTrunc(Sel, dl, DstSetCCVT, DstVT);
8116 DAG.getVTList(DstVT, MVT::Other),
8120 dl, DstVT, Sel, DAG.getConstant(0, dl, DstVT), SignMask);
8121 SDValue Result = DAG.getNode(ISD::XOR, dl, DstVT, SInt, IntOfs);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CodeGenPrepare.cpp 1281 EVT DstVT = TLI.getValueType(DL, CI->getType());
1284 if (SrcVT.isInteger() != DstVT.isInteger())
1289 if (SrcVT.bitsLT(DstVT)) return false;
1297 if (TLI.getTypeAction(CI->getContext(), DstVT) ==
1299 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT);
1302 if (SrcVT != DstVT)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 5885 /// When \p DstVT, the destination type of \p BC, is on the vector
5894 EVT DstVT = BC->getValueType(0);
5902 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5912 unsigned DstNumElt = DstVT.getVectorNumElements();
5927 *DAG.getContext(), DstVT.getScalarType(),
5930 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
5948 EVT DstVT = N->getValueType(0);
5951 (DstVT == MVT::f16 || DstVT == MVT::bf16))
5952 return MoveToHPR(SDLoc(N), DAG, MVT::i32, DstVT.getSimpleVT()
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