1 /* $NetBSD: dp8390reg.h,v 1.9 2012/10/14 13:38:13 phx Exp $ */ 2 3 /* 4 * National Semiconductor DS8390 NIC register definitions. 5 * 6 * Copyright (C) 1993, David Greenman. This software may be used, modified, 7 * copied, distributed, and sold, in both source and binary form provided that 8 * the above copyright and these terms are retained. Under no circumstances is 9 * the author responsible for the proper functioning of this software, nor does 10 * the author assume any responsibility for damages incurred with its use. 11 */ 12 13 /* 14 * Page 0 register offsets 15 */ 16 #define ED_P0_CR 0x00 /* Command Register */ 17 18 #define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 19 #define ED_P0_PSTART 0x01 /* Page Start register (write) */ 20 21 #define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 22 #define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 23 24 #define ED_P0_BNRY 0x03 /* Boundary Pointer */ 25 26 #define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 27 #define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 28 29 #define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 30 #define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 31 32 #define ED_P0_FIFO 0x06 /* FIFO register (read) */ 33 #define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 34 35 #define ED_P0_ISR 0x07 /* Interrupt Status Register */ 36 37 #define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 38 #define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 39 40 #define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 41 #define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 42 43 #define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 44 45 #define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 46 47 #define ED_P0_RSR 0x0c /* Receive Status (read) */ 48 #define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 49 50 #define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 51 #define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 52 53 #define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 54 #define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 55 56 #define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 57 #define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 58 59 /* 60 * Page 1 register offsets 61 */ 62 #define ED_P1_CR 0x00 /* Command Register */ 63 #define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 64 #define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 65 #define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 66 #define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 67 #define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 68 #define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 69 #define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 70 #define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 71 #define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 72 #define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 73 #define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 74 #define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 75 #define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 76 #define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 77 #define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 78 79 /* 80 * Page 2 register offsets 81 */ 82 #define ED_P2_CR 0x00 /* Command Register */ 83 #define ED_P2_PSTART 0x01 /* Page Start (read) */ 84 #define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 85 #define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 86 #define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 87 #define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 88 #define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 89 #define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 90 #define ED_P2_ACU 0x06 /* Address Counter Upper */ 91 #define ED_P2_ACL 0x07 /* Address Counter Lower */ 92 #define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 93 #define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 94 #define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 95 #define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 96 97 /* 98 * Command Register (CR) definitions 99 */ 100 101 /* 102 * STP: SToP. Software reset command. Takes the controller offline. No 103 * packets will be received or transmitted. Any reception or transmission in 104 * progress will continue to completion before entering reset state. To exit 105 * this state, the STP bit must reset and the STA bit must be set. The 106 * software reset has executed only when indicated by the RST bit in the ISR 107 * being set. 108 */ 109 #define ED_CR_STP 0x01 110 111 /* 112 * STA: STArt. This bit is used to activate the NIC after either power-up, or 113 * when the NIC has been put in reset mode by software command or error. 114 */ 115 #define ED_CR_STA 0x02 116 117 /* 118 * TXP: Transmit Packet. This bit must be set to indicate transmission of a 119 * packet. TXP is internally reset either after the transmission is completed 120 * or aborted. This bit should be set only after the Transmit Byte Count and 121 * Transmit Page Start register have been programmed. 122 */ 123 #define ED_CR_TXP 0x04 124 125 /* 126 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 127 * of the remote DMA channel. RD2 can be set to abort any remote DMA command 128 * in progress. The Remote Byte Count registers should be cleared when a 129 * remote DMA has been aborted. The Remote Start Addresses are not restored 130 * to the starting address if the remote DMA is aborted. 131 * 132 * RD2 RD1 RD0 function 133 * 0 0 0 not allowed 134 * 0 0 1 remote read 135 * 0 1 0 remote write 136 * 0 1 1 send packet 137 * 1 X X abort 138 */ 139 #define ED_CR_RD0 0x08 140 #define ED_CR_RD1 0x10 141 #define ED_CR_RD2 0x20 142 143 /* 144 * PS0, PS1: Page Select. The two bits select which register set or 'page' to 145 * access. 146 * 147 * PS1 PS0 page 148 * 0 0 0 149 * 0 1 1 150 * 1 0 2 151 * 1 1 3 (only on chips which have extensions to the dp8390) 152 */ 153 #define ED_CR_PS0 0x40 154 #define ED_CR_PS1 0x80 155 /* bit encoded aliases */ 156 #define ED_CR_PAGE_0 0x00 /* (for consistency) */ 157 #define ED_CR_PAGE_1 (ED_CR_PS0) 158 #define ED_CR_PAGE_2 (ED_CR_PS1) 159 #define ED_CR_PAGE_3 (ED_CR_PS1|ED_CR_PS0) 160 161 /* 162 * Interrupt Status Register (ISR) definitions 163 */ 164 165 /* 166 * PRX: Packet Received. Indicates packet received with no errors. 167 */ 168 #define ED_ISR_PRX 0x01 169 170 /* 171 * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 172 */ 173 #define ED_ISR_PTX 0x02 174 175 /* 176 * RXE: Receive Error. Indicates that a packet was received with one or more 177 * the following errors: CRC error, frame alignment error, FIFO overrun, 178 * missed packet. 179 */ 180 #define ED_ISR_RXE 0x04 181 182 /* 183 * TXE: Transmission Error. Indicates that an attempt to transmit a packet 184 * resulted in one or more of the following errors: excessive collisions, FIFO 185 * underrun. 186 */ 187 #define ED_ISR_TXE 0x08 188 189 /* 190 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 191 * would exceed (has exceeded?) the boundary pointer, resulting in data that 192 * was previously received and not yet read from the buffer to be overwritten. 193 */ 194 #define ED_ISR_OVW 0x10 195 196 /* 197 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Tally 198 * Counters has been set. 199 */ 200 #define ED_ISR_CNT 0x20 201 202 /* 203 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has 204 * completed. 205 */ 206 #define ED_ISR_RDC 0x40 207 208 /* 209 * RST: Reset status. Set when the NIC enters the reset state and cleared when 210 * a Start Command is issued to the CR. This bit is also set when a receive 211 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 212 * packets have been removed from the ring. This is a read-only bit. 213 */ 214 #define ED_ISR_RST 0x80 215 216 /* 217 * Interrupt Mask Register (IMR) definitions 218 */ 219 220 /* 221 * PRXE: Packet Received interrupt Enable. If set, a received packet will 222 * cause an interrupt. 223 */ 224 #define ED_IMR_PRXE 0x01 225 226 /* 227 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated 228 * when a packet transmission completes. 229 */ 230 #define ED_IMR_PTXE 0x02 231 232 /* 233 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur 234 * whenever a packet is received with an error. 235 */ 236 #define ED_IMR_RXEE 0x04 237 238 /* 239 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur 240 * whenever a transmission results in an error. 241 */ 242 #define ED_IMR_TXEE 0x08 243 244 /* 245 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated 246 * whenever the receive ring-buffer is overrun. i.e. when the boundary pointer 247 * is exceeded. 248 */ 249 #define ED_IMR_OVWE 0x10 250 251 /* 252 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated 253 * whenever the MSB of one or more of the Network Statistics counters has been 254 * set. 255 */ 256 #define ED_IMR_CNTE 0x20 257 258 /* 259 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is 260 * generated when a remote DMA transfer has completed. 261 */ 262 #define ED_IMR_RDCE 0x40 263 264 /* 265 * Bit 7 is unused/reserved. 266 */ 267 268 /* 269 * Data Configuration Register (DCR) definitions 270 */ 271 272 /* 273 * WTS: Word Transfer Select. WTS establishes byte or word transfers for both 274 * remote and local DMA transfers 275 */ 276 #define ED_DCR_WTS 0x01 277 278 /* 279 * BOS: Byte Order Select. BOS sets the byte order for the host. Should be 0 280 * for 80x86, and 1 for 68000 series processors 281 */ 282 #define ED_DCR_BOS 0x02 283 284 /* 285 * LAS: Long Address Select. When LAS is 1, the contents of the remote DMA 286 * registers RSAR0 and RSAR1 are used to provide A16-A31. 287 */ 288 #define ED_DCR_LAS 0x04 289 290 /* 291 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 of 292 * the TCR must also be programmed for loopback operation. When 1, normal 293 * operation is selected. 294 */ 295 #define ED_DCR_LS 0x08 296 297 /* 298 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 299 * under program control. When 1, remote DMA is automatically initiated and 300 * the boundary pointer is automatically updated. 301 */ 302 #define ED_DCR_AR 0x10 303 304 /* 305 * FT0, FT1: Fifo Threshold select. 306 * 307 * FT1 FT0 Word-width Byte-width 308 * 0 0 1 word 2 bytes 309 * 0 1 2 words 4 bytes 310 * 1 0 4 words 8 bytes 311 * 1 1 8 words 12 bytes 312 * 313 * During transmission, the FIFO threshold indicates the number of bytes or 314 * words that the FIFO has filled from the local DMA before BREQ is asserted. 315 * The transmission threshold is 16 bytes minus the receiver threshold. 316 */ 317 #define ED_DCR_FT0 0x20 318 #define ED_DCR_FT1 0x40 319 320 /* 321 * bit 7 (0x80) is unused/reserved 322 */ 323 324 /* 325 * Transmit Configuration Register (TCR) definitions 326 */ 327 328 /* 329 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 330 * is not appended by the transmitter. 331 */ 332 #define ED_TCR_CRC 0x01 333 334 /* 335 * LB0, LB1: Loopback control. These two bits set the type of loopback that is 336 * to be performed. 337 * 338 * LB1 LB0 mode 339 * 0 0 0 - normal operation (DCR_LS = 0) 340 * 0 1 1 - internal loopback (DCR_LS = 0) 341 * 1 0 2 - external loopback (DCR_LS = 1) 342 * 1 1 3 - external loopback (DCR_LS = 0) 343 */ 344 #define ED_TCR_LB0 0x02 345 #define ED_TCR_LB1 0x04 346 347 /* 348 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 349 * another station to disable the NIC's transmitter by transmitting to a 350 * multicast address hashing to bit 62. Reception of a multicast address 351 * hashing to bit 63 enables the transmitter. 352 */ 353 #define ED_TCR_ATD 0x08 354 355 /* 356 * OFST: Collision Offset enable. This bit when set modifies the backoff 357 * algorithm to allow prioritization of nodes. 358 */ 359 #define ED_TCR_OFST 0x10 360 361 /* 362 * bits 5, 6, and 7 are unused/reserved 363 */ 364 365 /* 366 * Transmit Status Register (TSR) definitions 367 */ 368 369 /* 370 * PTX: Packet Transmitted. Indicates successful transmission of packet. 371 */ 372 #define ED_TSR_PTX 0x01 373 374 /* 375 * bit 1 (0x02) is unused/reserved 376 */ 377 378 /* 379 * COL: Transmit Collided. Indicates that the transmission collided at least 380 * once with another station on the network. 381 */ 382 #define ED_TSR_COL 0x04 383 384 /* 385 * ABT: Transmit aborted. Indicates that the transmission was aborted due to 386 * excessive collisions. 387 */ 388 #define ED_TSR_ABT 0x08 389 390 /* 391 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 392 * transmission of the packet. (Transmission is not aborted because of a loss 393 * of carrier). 394 */ 395 #define ED_TSR_CRS 0x10 396 397 /* 398 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 399 * transmission memory before the FIFO emptied. Transmission of the packet was 400 * aborted. 401 */ 402 #define ED_TSR_FU 0x20 403 404 /* 405 * CDH: CD Heartbeat. Indicates that the collision detection circuitry isn't 406 * working correctly during a collision heartbeat test. 407 */ 408 #define ED_TSR_CDH 0x40 409 410 /* 411 * OWC: Out of Window Collision: Indicates that a collision occurred after a 412 * slot time (51.2us). The transmission is rescheduled just as in normal 413 * collisions. 414 */ 415 #define ED_TSR_OWC 0x80 416 417 /* 418 * Receiver Configuration Register (RCR) definitions 419 */ 420 421 /* 422 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 423 * packets with CRC and frame errors are not discarded. 424 */ 425 #define ED_RCR_SEP 0x01 426 427 /* 428 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 429 * If set to 1, packets with less than 64 byte are not discarded. 430 */ 431 #define ED_RCR_AR 0x02 432 433 /* 434 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 435 * accepted. 436 */ 437 #define ED_RCR_AB 0x04 438 439 /* 440 * AM: Accept Multicast. If set, packets sent to a multicast address are 441 * checked for a match in the hashing array. If clear, multicast packets are 442 * ignored. 443 */ 444 #define ED_RCR_AM 0x08 445 446 /* 447 * PRO: Promiscuous Physical. If set, all packets with a physical addresses 448 * are accepted. If clear, a physical destination address must match this 449 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM must 450 * also be set. In addition, the multicast hashing array must be set to all 451 * 1's so that all multicast addresses are accepted. 452 */ 453 #define ED_RCR_PRO 0x10 454 455 /* 456 * MON: Monitor Mode. If set, packets will be checked for good CRC and 457 * framing, but are not stored in the ring-buffer. If clear, packets are 458 * stored (normal operation). 459 */ 460 #define ED_RCR_MON 0x20 461 462 /* 463 * INTT: Interrupt Trigger Mode. Must be set if AX88190. 464 */ 465 #define ED_RCR_INTT 0x40 466 467 /* 468 * Bit 7 is unused/reserved. 469 */ 470 471 /* 472 * Receiver Status Register (RSR) definitions 473 */ 474 475 /* 476 * PRX: Packet Received without error. 477 */ 478 #define ED_RSR_PRX 0x01 479 480 /* 481 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for 482 * frame alignment errors. 483 */ 484 #define ED_RSR_CRC 0x02 485 486 /* 487 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end 488 * on a byte boundary and the CRC did not match at the last byte boundary. 489 */ 490 #define ED_RSR_FAE 0x04 491 492 /* 493 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local 494 * DMA) causing it to overrun. Reception of the packet is aborted. 495 */ 496 #define ED_RSR_FO 0x08 497 498 /* 499 * MPA: Missed Packet. Indicates that the received packet couldn't be stored 500 * in the ring-buffer because of insufficient buffer space (exceeding the 501 * boundary pointer), or because the transfer to the ring-buffer was inhibited 502 * by RCR_MON - monitor mode. 503 */ 504 #define ED_RSR_MPA 0x10 505 506 /* 507 * PHY: Physical address. If 0, the packet received was sent to a physical 508 * address. If 1, the packet was accepted because of a multicast/broadcast 509 * address match. 510 */ 511 #define ED_RSR_PHY 0x20 512 513 /* 514 * DIS: Receiver Disabled. Set to indicate that the receiver has entered 515 * monitor mode. Cleared when the receiver exits monitor mode. 516 */ 517 #define ED_RSR_DIS 0x40 518 519 /* 520 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL 521 * inputs are active, and the transceiver has set the CD line as a result of 522 * the jabber. 523 */ 524 #define ED_RSR_DFR 0x80 525 526 /* 527 * receive ring descriptor 528 * 529 * The National Semiconductor DS8390 Network interface controller uses the 530 * following receive ring headers. The way this works is that the memory on 531 * the interface card is chopped up into 256 bytes blocks. A contiguous 532 * portion of those blocks are marked for receive packets by setting start and 533 * end block #'s in the NIC. For each packet that is put into the receive 534 * ring, one of these headers (4 bytes each) is tacked onto the front. The 535 * first byte is a copy of the receiver status register at the time the packet 536 * was received. 537 */ 538 struct dp8390_ring { 539 u_int8_t rsr; /* receiver status */ 540 u_int8_t next_packet; /* pointer to next packet */ 541 u_int16_t count; /* bytes in packet (length + 4) */ 542 }; 543 544 /* 545 * Common constants 546 */ 547 #define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 548 #define ED_PAGE_MASK 255 549 #define ED_PAGE_SHIFT 8 550 551 #define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 552
Indexes created Tue Sep 23 02:09:52 GMT 2025