1 /* $NetBSD: exynos4_reg.h,v 1.16 2022/02/16 22:00:55 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Reinoud Zandijk. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_SAMSUNG_EXYNOS4_REG_H_ 33 #define _ARM_SAMSUNG_EXYNOS4_REG_H_ 34 35 /* 36 * Physical memory layout of Exynos SoCs as per documentation 37 * 38 * Base Address Limit Address Size Description 39 * 0x00000000 0x00010000 64 KB iROM 40 * 0x02000000 0x02010000 64 KB iROM (mirror of 0x0 to 0x10000) 41 * 0x02020000 0x02060000 256 KB iRAM 42 * 0x03000000 0x03020000 128 KB Data memory or general purpose of Samsung 43 * Reconfigurable Processor SRP. 44 * 0x03020000 0x03030000 64 KB I-cache or general purpose of SRP. 45 * 0x03030000 0x03039000 36 KB Configuration memory (write only) of SRP 46 * 0x03810000 0x03830000 AudioSS's SFR region 47 * 0x04000000 0x05000000 16 MB Bank0 of Static ROM Controller (SMC) 48 * (16-bit only) 49 * 0x05000000 0x06000000 16 MB Bank1 of SMC 50 * 0x06000000 0x07000000 16 MB Bank2 of SMC 51 * 0x07000000 0x08000000 16 MB Bank3 of SMC 52 * 0x08000000 0x0C000000 64 MB Reserved 53 * 0x0C000000 0x0CD00000 Reserved 54 * 0x0CE00000 0x0D000000 SFR region of Nand Flash Contr. (NFCON) 55 * 0x10000000 0x14000000 SFR region 56 * 0x40000000 0xA0000000 1.5 GB Memory of Dynamic Memory Contr. (DMC)-0 57 * 0xA0000000 0x00000000 1.5 GB Memory of DMC-1 58 */ 59 60 /* 61 * 62 * The exynos can boot from its iROM or from an external Nand memory. Since 63 * these are normally hardly used they are excluded from the normal register 64 * space here. 65 * 66 * XXX What about the audio subsystem region. Where are the docs? 67 * 68 * EXYNOS_CORE_PBASE points to the main SFR region. 69 * 70 * Notes: 71 * 72 * SFR Special Function Register 73 * ISP In-System Programming, like a JTAG 74 * ACP Accelerator Coherency Port 75 * SSS Security Sub System 76 * GIC Generic Interurrupt Controller 77 * PMU Power Management Unit 78 * DMC 2D Graphics engine 79 * LEFTBUS Data bus / Peripheral bus 80 * RIGHTBUS ,, 81 * G3D 3D Graphics engine 82 * MFC Multi-Format Codec 83 * LCD0 LCD display 84 * MCT Multi Core Timer 85 * CMU Clock Management Unit 86 * TMU Thermal Management Unit 87 * PPMU Pin Parametric Measurement Unit (?) 88 * MMU Memory Management Unit 89 * MCTimer ? 90 * WDT Watch Dog Timer 91 * RTC Real Time Clock 92 * KEYIF Keypad interface 93 * SECKEY ? 94 * TZPC TrustZone Protection Controller 95 * UART Universal asynchronous receiver/transmitter 96 * I2C Inter IC Connect 97 * SPI Serial Peripheral Interface Bus 98 * I2S Inter-IC Sound, Integrated Interchip Sound, or IIS 99 * PCM Pulse-code modulation, audio stream at set fixed rate 100 * SPDIF Sony/Philips Digital Interface Format 101 * Slimbus Serial Low-power Inter-chip Media Bus 102 * SMMU System mmu. No idea as how its programmed (or not) 103 * PERI-L UART, I2C, SPI, I2S, PCM, SPDIF, PWM, I2CHDMI, Slimbus 104 * PERI-R CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, MCTimer, WDT, RTC, KEYIF, 105 * SECKEY, TZPC 106 */ 107 108 /* 109 * Note that this table is not 80-char friendly, this is done to allow more 110 * elaborate comments to clarify the register offsets use 111 */ 112 113 /* CORE */ 114 #define EXYNOS4_CORE_SIZE 0x04000000 115 #define EXYNOS4_SDRAM_PBASE 0x40000000 116 117 #define EXYNOS4_SYSREG_OFFSET 0x00010000 118 #define EXYNOS4_PMU_OFFSET 0x00020000 /* Power Management Unit */ 119 #define EXYNOS4_CMU_TOP_PART_OFFSET 0x00030000 /* Clock(s) management unit */ 120 #define EXYNOS4_CMU_EPLL 0x0003C010 /* Audio and ext. interf. clock */ 121 #define EXYNOS4_CMU_VPLL 0x0003C020 /* Video core (dither?) clock */ 122 #define EXYNOS4_CMU_CORE_ISP_PART_OFFSET 0x00040000 /* Clock(s) management unit */ 123 #define EXYNOS4_CMU_MPLL 0x00040008 /* MEM cntr. clock */ 124 #define EXYNOS4_CMU_APLL 0x00044000 /* ARM core clock */ 125 #define EXYNOS4_MCT_OFFSET 0x00050000 /* Multi Core Timer */ 126 #define EXYNOS4_WDT_OFFSET 0x00060000 /* Watch Dog Timer */ 127 #define EXYNOS4_RTC_OFFSET 0x00070000 /* Real Time Clock */ 128 #define EXYNOS4_KEYIF_OFFSET 0x000A0000 /* Keypad interface */ 129 #define EXYNOS4_HDMI_CEC_OFFSET 0x000B0000 /* HDMI Consumer Electronic Control */ 130 #define EXYNOS4_TMU_OFFSET 0x000C0000 /* Thermal Management */ 131 #define EXYNOS4_SECKEY_OFFSET 0x00100000 /* XXX unknown XXX */ 132 #define EXYNOS4_TZPC0_OFFSET 0x00110000 /* ARM Trusted Zone Protection Controller */ 133 #define EXYNOS4_TZPC1_OFFSET 0x00120000 134 #define EXYNOS4_TZPC2_OFFSET 0x00130000 135 #define EXYNOS4_TZPC3_OFFSET 0x00140000 136 #define EXYNOS4_TZPC4_OFFSET 0x00150000 137 #define EXYNOS4_TZPC5_OFFSET 0x00160000 138 #define EXYNOS4_INTCOMBINER_OFFSET 0x00440000 /* combines first 32 interrupt sources */ 139 #define EXYNOS4_GIC_CNTR_OFFSET 0x00480000 /* generic interrupt controller offset */ 140 #define EXYNOS4_GIC_DISTRIBUTOR_OFFSET 0x00490000 141 #define EXYNOS4_AP_C2C_OFFSET 0x00540000 /* Chip 2 Chip XXX doc? XXX */ 142 #define EXYNOS4_CP_C2C_MODEM_OFFSET 0x00580000 143 #define EXYNOS4_DMC0_OFFSET 0x00600000 /* Dynamic Memory Controller */ 144 #define EXYNOS4_DMC1_OFFSET 0x00610000 145 #define EXYNOS4_PPMU_DMC_L_OFFSET 0x006A0000 /* event counters XXX ? */ 146 #define EXYNOS4_PPMU_DMC_R_OFFSET 0x006B0000 147 #define EXYNOS4_PPMU_CPU_OFFSET 0x006C0000 148 #define EXYNOS4_GPIO_C2C_OFFSET 0x006E0000 149 #define EXYNOS4_TZASC_LR_OFFSET 0x00700000 /* trust zone access control */ 150 #define EXYNOS4_TZASC_LW_OFFSET 0x00710000 151 #define EXYNOS4_TZASC_RR_OFFSET 0x00720000 152 #define EXYNOS4_TZASC_RW_OFFSET 0x00730000 153 #define EXYNOS4_G2D_ACP_OFFSET 0x00800000 /* 2D graphics engine */ 154 #define EXYNOS4_SSS_OFFSET 0x00830000 /* Security Sub System */ 155 #define EXYNOS4_CORESIGHT_1_OFFSET 0x00880000 /* 1st region */ 156 #define EXYNOS4_CORESIGHT_2_OFFSET 0x00890000 /* 2nd region */ 157 #define EXYNOS4_CORESIGHT_3_OFFSET 0x008B0000 /* 3rd region */ 158 #define EXYNOS4_SMMUG2D_ACP_OFFSET 0x00A40000 /* system mmu for 2D graphics engine */ 159 #define EXYNOS4_SMMUSSS_OFFSET 0x00A50000 /* system mmu for SSS */ 160 #define EXYNOS4_GPIO_RIGHT_OFFSET 0x01000000 161 #define EXYNOS4_GPIO_LEFT_OFFSET 0x01400000 162 #define EXYNOS4_FIMC0_OFFSET 0x01800000 /* image for display */ 163 #define EXYNOS4_FIMC1_OFFSET 0x01810000 164 #define EXYNOS4_FIMC2_OFFSET 0x01820000 165 #define EXYNOS4_FIMC3_OFFSET 0x01830000 166 #define EXYNOS4_JPEG_OFFSET 0x01840000 /* JPEG Codec */ 167 #define EXYNOS4_MIPI_CSI0_OFFSET 0x01880000 /* MIPI-Slim bus Interface */ 168 #define EXYNOS4_MIPI_CSI1_OFFSET 0x01890000 169 #define EXYNOS4_SMMUFIMC0_OFFSET 0x01A20000 /* system mmus */ 170 #define EXYNOS4_SMMUFIMC1_OFFSET 0x01A30000 171 #define EXYNOS4_SMMUFIMC2_OFFSET 0x01A40000 172 #define EXYNOS4_SMMUFIMC3_OFFSET 0x01A50000 173 #define EXYNOS4_SMMUJPEG_OFFSET 0x01A60000 174 #define EXYNOS4_FIMD0_OFFSET 0x01C00000 /* LCD0 */ 175 #define EXYNOS4_MIPI_DSI0_OFFSET 0x01C80000 /* LCD0 */ 176 #define EXYNOS4_SMMUFIMD0_OFFSET 0x01E20000 /* system mmus */ 177 #define EXYNOS4_FIMC_ISP_OFFSET 0x02000000 /* (digital) camera video input */ 178 #define EXYNOS4_FIMC_DRC_TOP_OFFSET 0x02010000 179 #define EXYNOS4_FIMC_FD_TOP_OFFSET 0x02040000 180 #define EXYNOS4_MPWM_ISP_OFFSET 0x02110000 /* (specialised?) PWM */ 181 #define EXYNOS4_I2C0_ISP_OFFSET 0x02130000 /* I2C bus */ 182 #define EXYNOS4_I2C1_ISP_OFFSET 0x02140000 183 #define EXYNOS4_MTCADC_ISP_OFFSET 0x02150000 /* (specialised?) AD Converter */ 184 #define EXYNOS4_PWM_ISP_OFFSET 0x02160000 /* PWM */ 185 #define EXYNOS4_WDT_ISP_OFFSET 0x02170000 /* Watch Dog Timer */ 186 #define EXYNOS4_MCUCTL_ISP_OFFSET 0x02180000 /* XXX unknown XXX */ 187 #define EXYNOS4_UART_ISP_OFFSET 0x02190000 /* uart base clock */ 188 #define EXYNOS4_SPI0_ISP_OFFSET 0x021A0000 189 #define EXYNOS4_SPI1_ISP_OFFSET 0x021B0000 190 #define EXYNOS4_GIC_C_ISP_OFFSET 0x021E0000 191 #define EXYNOS4_GIC_D_ISP_OFFSET 0x021F0000 192 #define EXYNOS4_SYSMMU_FIMC_ISP_OFFSET 0x02260000 193 #define EXYNOS4_SYSMMU_FIMC_DRC_OFFSET 0x02270000 194 #define EXYNOS4_SYSMMU_FIMC_FD_OFFSET 0x022A0000 195 #define EXYNOS4_SYSMMU_ISPCPU_OFFSET 0x022B0000 196 #define EXYNOS4_FIMC_LITE0_OFFSET 0x02390000 /* external image input? */ 197 #define EXYNOS4_FIMC_LITE1_OFFSET 0x023A0000 198 #define EXYNOS4_SYSMMU_FIMC_LITE0_OFFSET 0x023B0000 199 #define EXYNOS4_SYSMMU_FIMC_LITE1_OFFSET 0x023C0000 200 #define EXYNOS4_USBDEV0_OFFSET 0x02480000 /* XXX unknown XXX */ 201 #define EXYNOS4_USBDEV0_1_OFFSET 0x02480000 202 #define EXYNOS4_USBDEV0_2_OFFSET 0x02490000 203 #define EXYNOS4_USBDEV0_3_OFFSET 0x024A0000 204 #define EXYNOS4_USBDEV0_4_OFFSET 0x024B0000 205 #define EXYNOS4_TSI_OFFSET 0x02500000 /* Transport Stream Interface */ 206 #define EXYNOS4_SDMMC0_OFFSET 0x02510000 /* SD card interface */ 207 #define EXYNOS4_SDMMC1_OFFSET 0x02520000 208 #define EXYNOS4_SDMMC2_OFFSET 0x02530000 209 #define EXYNOS4_SDMMC3_OFFSET 0x02540000 210 #define EXYNOS4_SDMMC4_OFFSET 0x02550000 211 #define EXYNOS4_MIPI_HSI_OFFSET 0x02560000 /* LCD0 */ 212 #define EXYNOS4_SROMC_OFFSET 0x02570000 213 214 #define EXYNOS4_USB2HOST_OFFSET 0x02580000 215 #define EXYNOS4_USB2_HOST_EHCI_OFFSET 0x02580000 216 #define EXYNOS4_USB2_HOST_OHCI_OFFSET 0x02590000 217 #define EXYNOS4_USB2_HOST_PHYCTRL_OFFSET 0x025B0000 218 #define EXYNOS4_USBOTG1_OFFSET 0x025B0000 /* USB On The Go interface */ 219 220 #define EXYNOS4_PDMA0_OFFSET 0x02680000 /* Peripheral DMA */ 221 #define EXYNOS4_PDMA1_OFFSET 0x02690000 222 #define EXYNOS4_GADC_OFFSET 0x026C0000 /* General AD Converter */ 223 #define EXYNOS4_ROTATOR_OFFSET 0x02810000 /* Image rotator for video output */ 224 #define EXYNOS4_SMDMA_OFFSET 0x02840000 /* (s) Memory DMA */ 225 #define EXYNOS4_NSMDMA_OFFSET 0x02850000 /* (ns) Memory DMA */ 226 #define EXYNOS4_SMMUROTATOR_OFFSET 0x02A30000 /* system mmu for rotator */ 227 #define EXYNOS4_SMMUMDMA_OFFSET 0x02A40000 228 #define EXYNOS4_VP_OFFSET 0x02C00000 /* Video Processor */ 229 #define EXYNOS4_MIXER_OFFSET 0x02C10000 /* Video mixer */ 230 #define EXYNOS4_HDMI0_OFFSET 0x02D00000 231 #define EXYNOS4_HDMI1_OFFSET 0x02D10000 232 #define EXYNOS4_HDMI2_OFFSET 0x02D20000 233 #define EXYNOS4_HDMI3_OFFSET 0x02D30000 234 #define EXYNOS4_HDMI4_OFFSET 0x02D40000 235 #define EXYNOS4_HDMI5_OFFSET 0x02D50000 236 #define EXYNOS4_HDMI6_OFFSET 0x02D60000 237 #define EXYNOS4_SMMUTV_OFFSET 0x02E20000 238 #define EXYNOS4_G3D_OFFSET 0x03000000 /* 3D Graphics Accelerator */ 239 #define EXYNOS4_PPMU_3D_OFFSET 0x03220000 240 #define EXYNOS4_MFC_OFFSET 0x03400000 /* Multi Format Codec */ 241 #define EXYNOS4_SMMUMFC_L_OFFSET 0x03620000 242 #define EXYNOS4_SMMUMFC_R_OFFSET 0x03630000 243 #define EXYNOS4_PMMU_MFC_L_OFFSET 0x03660000 /* ? */ 244 #define EXYNOS4_PMMU_MFC_R_OFFSET 0x03670000 /* ? */ 245 #define EXYNOS4_UART0_OFFSET 0x03800000 /* serial port 0 */ 246 #define EXYNOS4_UART1_OFFSET 0x03810000 /* serial port 1 */ 247 #define EXYNOS4_UART2_OFFSET 0x03820000 /* serial port 2 */ 248 #define EXYNOS4_UART3_OFFSET 0x03830000 /* serial port 3 */ 249 #define EXYNOS4_UART4_OFFSET 0x03840000 /* serial port 4 */ 250 #define EXYNOS4_I2C0_OFFSET 0x03860000 /* Inter Integrated Circuit (I2C) */ 251 #define EXYNOS4_I2C1_OFFSET 0x03870000 /* Inter Integrated Circuit (I2C) */ 252 #define EXYNOS4_I2C2_OFFSET 0x03880000 /* Inter Integrated Circuit (I2C) */ 253 #define EXYNOS4_I2C3_OFFSET 0x03890000 /* Inter Integrated Circuit (I2C) */ 254 #define EXYNOS4_I2C4_OFFSET 0x038A0000 /* Inter Integrated Circuit (I2C) */ 255 #define EXYNOS4_I2C5_OFFSET 0x038B0000 /* Inter Integrated Circuit (I2C) */ 256 #define EXYNOS4_I2C6_OFFSET 0x038C0000 /* Inter Integrated Circuit (I2C) */ 257 #define EXYNOS4_I2C7_OFFSET 0x038D0000 /* Inter Integrated Circuit (I2C) */ 258 #define EXYNOS4_I2CHDMI_OFFSET 0x038E0000 /* I2C for HDMI */ 259 #define EXYNOS4_SPI0_OFFSET 0x03920000 /* Serial Peripheral Interface0 */ 260 #define EXYNOS4_SPI1_OFFSET 0x03930000 /* Serial Peripheral Interface0 */ 261 #define EXYNOS4_SPI2_OFFSET 0x03940000 /* Serial Peripheral Interface0 */ 262 #define EXYNOS4_I2S1_OFFSET 0x03960000 /* sound */ 263 #define EXYNOS4_I2S2_OFFSET 0x03970000 /* sound */ 264 #define EXYNOS4_PCM1_OFFSET 0x03980000 /* sound */ 265 #define EXYNOS4_PCM2_OFFSET 0x03990000 /* sound */ 266 #define EXYNOS4_AC97_OFFSET 0x039A0000 /* AC97 audio codec sound */ 267 #define EXYNOS4_SPDIF_OFFSET 0x039B0000 /* SPDIF sound */ 268 #define EXYNOS4_PWMTIMER_OFFSET 0x039D0000 269 270 /* AUDIOCORE */ 271 #define EXYNOS4_AUDIOCORE_OFFSET 0x04000000 /* on 1Mb L1 chunk */ 272 #define EXYNOS4_AUDIOCORE_VBASE (EXYNOS_CORE_VBASE + EXYNOS4_AUDIOCORE_OFFSET) 273 #define EXYNOS4_AUDIOCORE_PBASE 0x03800000 /* Audio SFR */ 274 #define EXYNOS4_AUDIOCORE_SIZE 0x00100000 275 276 #define EXYNOS4_GPIO_I2S0_OFFSET (EXYNOS4_AUDIOCORE_OFFSET + 0x00060000) 277 278 /* used Exynos4 USB PHY registers */ 279 #define USB_PHYPWR 0x00 280 #define PHYPWR_FORCE_SUSPEND __BIT(1) 281 #define PHYPWR_ANALOG_POWERDOWN __BIT(3) 282 #define PHYPWR_OTG_DISABLE __BIT(4) 283 #define PHYPWR_SLEEP_PHY0 __BIT(5) 284 #define PHYPWR_NORMAL_MASK 0x19 285 #define PHYPWR_NORMAL_MASK_PHY0 (__BITS(3,3) | 1) 286 #define PHYPWR_NORMAL_MASK_PHY1 __BITS(6,3) 287 #define PHYPWR_NORMAL_MASK_HSIC0 __BITS(9,3) 288 #define PHYPWR_NORMAL_MASK_HSIC1 __BITS(12,3) 289 #define USB_PHYCLK 0x04 /* holds FSEL_CLKSEL_ */ 290 #define USB_RSTCON 0x08 291 #define RSTCON_SWRST __BIT(0) 292 #define RSTCON_HLINK_RWRST __BIT(1) 293 #define RSTCON_DEVPHYLINK_SWRST __BIT(2) 294 #define RSTCON_DEVPHY_SWRST __BITS(0,3) 295 #define RSTCON_HOSTPHY_SWRST __BITS(3,4) 296 #define RSTCON_HOSTPHYLINK_SWRST __BITS(7,4) 297 298 299 #endif /* _ARM_SAMSUNG_EXYNOS4_REG_H_ */ 300 301
Indexes created Sat Sep 20 22:09:52 GMT 2025