1 /* $NetBSD: exynos5_reg.h,v 1.22 2018/07/04 23:06:05 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_SAMSUNG_EXYNOS5_REG_H_ 33 #define _ARM_SAMSUNG_EXYNOS5_REG_H_ 34 35 /* 36 * Physical memory layout of Exynos5 SoCs as per documentation 37 * 38 * Base Address Limit Address Size Description 39 * 0x00000000 0x0000FFFF 64 KB iROM/iRAM/SROM 40 * 0x02000000 0x0200FFFF 64 KB iROM (mirror of 0x0 to 0xFFFF) 41 * 0x02020000 0x02077FFF 352 KB iRAM 42 * 0x03000000 0x03027FFF 160 KB Data memory of SRP 43 * 0x03028000 0x0303FFFF 96 KB I-cache of SRP 44 * 0x03040000 0x03048FFF 36 KB Configuration memory of SRP (write-only) 45 * 0x03800000 0x0386FFFF SFR region of AudioSS 46 * 0x04000000 0x04020000 128 KB SROMC's Bank 0 47 * 0x05000000 0x05020000 128 KB SROMC's Bank 1 48 * 0x06000000 0x06020000 128 KB SROMC's Bank 2 49 * 0x07000000 0x07020000 128 KB SROMC's Bank 3 50 * 0x10000000 0x1FFFFFFF SFR region 51 * 0x40000000 0xFFFFFFFF DRAM 52 */ 53 54 /* MJF: The GPIO offset names made no sense and the values wer wrong. */ 55 #define EXYNOS5_GPIO_MUXA_OFFSET 0x03400000 56 #define EXYNOS5_GPIO_MUXB_OFFSET 0x03410000 57 #define EXYNOS5_GPIO_MUXC_OFFSET 0x04000000 58 #define EXYNOS5_GPIO_MUXD_OFFSET 0x04010000 59 #define EXYNOS5_GPIO_MUXE_OFFSET 0x03860000 60 61 /* CORE */ 62 #define EXYNOS5_CORE_SIZE 0x0f000000 63 #define EXYNOS5_SDRAM_PBASE 0x40000000 64 65 #define EXYNOS5_CMU_CORE_PART_OFFSET 0x00010000 66 #define EXYNOS5_CMU_APLL 0x00010000 /* ARM core clock */ 67 #define EXYNOS5_CMU_MPLL 0x00014000 /* MEM cntr. clock */ 68 #define EXYNOS5_CMU_TOP_PART_OFFSET 0x00020000 69 #define EXYNOS5_CMU_CPLL 0x00020020 /* Video hardware codec clock */ 70 #define EXYNOS5_CMU_DPLL 0x00020030 /* Audio and ext. interf. clock */ 71 #define EXYNOS5_CMU_VPLL 0x00020040 /* Dither PLL (EMI reduction) clock */ 72 #define EXYNOS5_CMU_GPLL 0x00020050 /* Graphic 3D proc. clock */ 73 #define EXYNOS5_CMU_MEM_PART_OFFSET 0x00030000 74 #define EXYNOS5_CMU_BPLL 0x00030010 75 #define EXYNOS5_CMU_KPLL 0x00038000 76 #define EXYNOS5_ALIVE_OFFSET 0x00040000 77 #define EXYNOS5_PMU_OFFSET 0x00040000 /* alias */ 78 #define EXYNOS5_SYSREG_OFFSET 0x00050000 79 #define EXYNOS5_TMU_OFFSET 0x00060000 80 #define EXYNOS5_MONOTONIC_CNT_OFFSET 0x000C0000 81 82 #define EXYNOS5_HDMI_CEC_OFFSET 0x001B0000 83 #define EXYNOS5_MCT_OFFSET 0x001C0000 84 #define EXYNOS5_WDT_OFFSET 0x001D0000 85 #define EXYNOS5_RTC_OFFSET 0x001E0000 86 87 #define EXYNOS5_INT_COMB_CPU_OFFSET 0x00440000 88 #define EXYNOS5_INT_COMB_IOP_OFFSET 0x00450000 89 #define EXYNOS5_GIC_CPU_OFFSET 0x00480000 90 #define EXYNOS5_GIC_IOP_DISTRIBUTOR_OFFSET 0x00481000 91 #define EXYNOS5_GIC_IOP_CONTROLLER_OFFSET 0x00482000 92 #define EXYNOS5_MPCORE PRIVATE REGION_OFFSET 0x00500000 93 #define EXYNOS5_NS MDMA0 0x00800000 94 #define EXYNOS5_SSS_OFFSET 0x00830000 95 #define EXYNOS5_SSS_KEY_OFFSET 0x00840000 96 #define EXYNOS5_2D_OFFSET 0x00850000 97 #define EXYNOS5_CSSYS_OFFSET 0x00880000 98 #if 0 99 #define EXYNOS5_A15 (EAGLE) 0x00890000 100 #define EXYNOS5_A5 (IOP) 0x008A0000 101 #define EXYNOS5_A5 (ISP) 0x008B0000 102 #endif 103 #define EXYNOS5_SYSMMU_MDMA_OFFSET 0x00A40000 104 #define EXYNOS5_SYSMMU_SSS_OFFSET 0x00A50000 105 #define EXYNOS5_SYSMMU_2D_OFFSET 0x00A60000 106 #define EXYNOS5_DREXII_PHY0_OFFSET 0x00C00000 107 #define EXYNOS5_DREXII_PHY1_OFFSET 0x00C10000 108 #define EXYNOS5_AS_A_3D_OFFSET 0x00CC0000 109 #define EXYNOS5_AS_A_C2C_OFFSET 0x00CD0000 110 #define EXYNOS5_AS_A_LEFT_BUS_OFFSET 0x00CE0000 111 #define EXYNOS5_AS_A_RIGHT0_BUS_OFFSET 0x00CF0000 112 #define EXYNOS5_AS_A_DISP1_BUS_OFFSET 0x00D00000 113 /*#define EXYNOS5_GPIO_C2C_OFFSET 0x00D10000*/ 114 #define EXYNOS5_DREXII_OFFSET 0x00DD0000 115 #define EXYNOS5_AS_A_EFCON_OFFSET 0x00DE0000 116 #define EXYNOS5_AP_C2C_OFFSET 0x00E00000 117 #define EXYNOS5_CP_C2C_OFFSET 0x00E40000 118 #define EXYNOS5_AS_A_ACP_BLK_OFFSET 0x00E80000 119 #define EXYNOS5_AS_A_CPU_P_BLK_OFFSET 0x00E90000 120 #define EXYNOS5_AS_A_LBX_BUS_OFFSET 0x00F00000 121 #define EXYNOS5_AS_A_R1BX_BUS_OFFSET 0x00F10000 122 #define EXYNOS5_AS_A_R0BX_BUS_OFFSET 0x00F20000 123 #define EXYNOS5_AS_A_CPU_OFFSET 0x00F30000 124 #define EXYNOS5_MFC_OFFSET 0x01000000 125 #define EXYNOS5_SYSMMU_MFC0_R 0x01200000 126 #define EXYNOS5_SYSMMU_MFC1_L 0x01210000 127 /*#define EXYNOS5_GPIO_LEFT_OFFSET 0x04010000*/ 128 #define EXYNOS5_AS_A_MFC_OFFSET 0x01680000 129 #define EXYNOS5_AS_A_GENX_OFFSET 0x016A0000 130 #define EXYNOS5_3D ENGINE_OFFSET 0x01800000 131 #define EXYNOS5_ROTATOR_OFFSET 0x01C00000 132 #define EXYNOS5_NS_MDMA1 0x01C10000 133 #define EXYNOS5_SYSMMU_ROTATOR_OFFSET 0x01D40000 134 #define EXYNOS5_SYSMMU_MDMA1 0x01D50000 135 #define EXYNOS5_AS_A_FILE_OFFSET 0x01DA0000 136 #define EXYNOS5_AS_A_GPS_OFFSET 0x01DB0000 137 #define EXYNOS5_AS_A_JPEG_OFFSET 0x01DC0000 138 #define EXYNOS5_JPEG_OFFSET 0x01E00000 139 #define EXYNOS5_SYSMMU_JPEG_OFFSET 0x01F20000 140 141 #define EXYNOS5_USB3_XHCI0_OFFSET 0x02000000 142 #define EXYNOS5_USB3_PHY0_OFFSET 0x02100000 143 144 #define EXYNOS5_USB2HOST_OFFSET 0x02110000 145 #define EXYNOS5_USB2_HOST_EHCI_OFFSET 0x02110000 146 #define EXYNOS5_USB2_HOST_OHCI_OFFSET 0x02120000 147 #define EXYNOS5_USB2_HOST_PHYCTRL_OFFSET 0x02130000 148 #define EXYNOS5_USB2_DEVICE_LINK_OFFSET 0x02140000 149 150 #define EXYNOS5_MIPI_HSI_OFFSET 0x02160000 151 #define EXYNOS5_SATA PHY CONTROL_OFFSET 0x02170000 152 #define EXYNOS5_MCUCTL_IOP_OFFSET 0x02180000 /* XXX unknown XXX */ 153 #define EXYNOS5_WDT_IOP_OFFSET 0x02190000 154 #define EXYNOS5_PDMA0 0x021A0000 155 #define EXYNOS5_PDMA1 0x021B0000 156 #define EXYNOS5_RTIC_OFFSET 0x021C0000 157 #define EXYNOS5_SATA_I2C_PHY_CONTROL_OFFSET 0x021D0000 158 #define EXYNOS5_MSH0 0x02200000 159 #define EXYNOS5_MSH1 0x02210000 160 #define EXYNOS5_MSH2 0x02220000 161 #define EXYNOS5_MSH3 0x02230000 162 #define EXYNOS5_SROMC_OFFSET 0x02250000 163 #define EXYNOS5_SATA_OFFSET 0x022F0000 164 #if 0 165 #define EXYNOS5_AXI_FILE_D64 (GPV) 0x02300000 166 #define EXYNOS5_AXI_FILE_D64 (GPV) 0x02310000 167 #endif 168 #define EXYNOS5_AXI_USB_SATA_D64 0x02320000 169 #if 0 170 #define EXYNOS5_AXI_USB_SATA_D64 0x02330000 171 #endif 172 #define EXYNOS5_SYSMMU_IOPROCESSOR_OFFSET 0x02360000 173 #define EXYNOS5_SYSMMU_RTIC_OFFSET 0x02370000 174 #define EXYNOS5_AS_A_IOP_FD64X_OFFSET 0x02380000 175 #define EXYNOS5_AS_A_AUDIO_OFFSET 0x02390000 176 177 #define EXYNOS5_USB3_XHCI1_OFFSET 0x02400000 178 #define EXYNOS5_USB3_PHY1_OFFSET 0x02500000 179 180 #if 0 181 #define EXYNOS5_AXI_GPS (GPV) 0x02600000 182 #define EXYNOS5_AXI_GPS (GPV) 0x02610000 183 #endif 184 #define EXYNOS5_AS_A_GPSCPU_OFFSET 0x02620000 185 #define EXYNOS5_SYSMMU_GPS_OFFSET 0x02630000 186 #define EXYNOS5_UART0_OFFSET 0x02C00000 187 #define EXYNOS5_UART1_OFFSET 0x02C10000 188 #define EXYNOS5_UART2_OFFSET 0x02C20000 189 #define EXYNOS5_UART3_OFFSET 0x02C30000 190 #define EXYNOS5_USI0_OFFSET 0x02C50000 191 #define EXYNOS5_I2C0_OFFSET 0x02C60000 192 #define EXYNOS5_I2C1_OFFSET 0x02C70000 193 #define EXYNOS5_I2C2_OFFSET 0x02C80000 194 #define EXYNOS5_I2C3_OFFSET 0x02C90000 195 #define EXYNOS5_I2C4_OFFSET 0x02CA0000 196 #define EXYNOS5_I2C5_OFFSET 0x02CB0000 197 #define EXYNOS5_I2C6_OFFSET 0x02CC0000 198 #define EXYNOS5_I2C7_OFFSET 0x02CD0000 199 #define EXYNOS5_I2CHDMI_OFFSET 0x02CE0000 200 #define EXYNOS5_USI_OFFSET 0x02D00000 201 #define EXYNOS5_TSADC_OFFSET 0x02D10000 202 #define EXYNOS5_SPI0_OFFSET 0x02D20000 203 #define EXYNOS5_SPI1_OFFSET 0x02D30000 204 #define EXYNOS5_SPI2_OFFSET 0x02D40000 205 #define EXYNOS5_USI2_OFFSET 0x02D50000 206 #define EXYNOS5_I2S1_OFFSET 0x02D60000 207 #define EXYNOS5_I2S2_OFFSET 0x02D70000 208 #define EXYNOS5_PCM1_OFFSET 0x02D80000 209 #define EXYNOS5_PCM2_OFFSET 0x02D90000 210 #define EXYNOS5_AC97_OFFSET 0x02DA0000 211 #define EXYNOS5_SPDIF_OFFSET 0x02DB0000 212 #define EXYNOS5_PWM_OFFSET 0x02DD0000 213 #define EXYNOS5_USI3_OFFSET 0x02DE0000 214 #define EXYNOS5_FIMC_ISP_OFFSET 0x03000000 215 #define EXYNOS5_FIMC_DRC_TOP_OFFSET 0x03010000 216 #define EXYNOS5_FIMC_SCALERC_OFFSET 0x03020000 217 #define EXYNOS5_FIMC_SCALERP_OFFSET 0x03030000 218 #define EXYNOS5_FIMC_FD_TOP_OFFSET 0x03040000 219 #define EXYNOS5_FIMC_ODC_OFFSET 0x03050000 220 #define EXYNOS5_FIMC_DIS_OFFSET 0x03060000 221 #define EXYNOS5_FIMC_3DNR_OFFSET 0x03070000 222 #define EXYNOS5_ASYNC_AXI_M_OFFSET 0x030F0000 223 #define EXYNOS5_MPWM_ISP_OFFSET 0x03110000 224 #define EXYNOS5_I2C2_ISP_OFFSET 0x03120000 225 #define EXYNOS5_I2C0_ISP_OFFSET 0x03130000 226 #define EXYNOS5_I2C1_ISP_OFFSET 0x03140000 227 #define EXYNOS5_MTCADC_ISP_OFFSET 0x03150000 228 #define EXYNOS5_PWM_ISP_OFFSET 0x03160000 229 #define EXYNOS5_WDT_ISP_OFFSET 0x03170000 230 #define EXYNOS5_MCUCTL_ISP_OFFSET 0x03180000 231 #define EXYNOS5_UART_ISP_OFFSET 0x03190000 232 #define EXYNOS5_SPI0_ISP_OFFSET 0x031A0000 233 #define EXYNOS5_SPI1_ISP_OFFSET 0x031B0000 234 #define EXYNOS5_GIC_C_ISP_OFFSET 0x031E0000 235 #define EXYNOS5_GIC_D_ISP_OFFSET 0x031F0000 236 #define EXYNOS5_SYSMMU_FIMC_ISP_OFFSET 0x03260000 237 #define EXYNOS5_SYSMMU_FIMC_DRC_OFFSET 0x03270000 238 #define EXYNOS5_SYSMMU_FIMC_SCALERC_OFFSET 0x03280000 239 #define EXYNOS5_SYSMMU_FIMC_SCALERP_OFFSET 0x03290000 240 #define EXYNOS5_SYSMMU_FIMC_FD_OFFSET 0x032A0000 241 #define EXYNOS5_SYSMMU_ISPCPU_OFFSET 0x032B0000 242 #define EXYNOS5_SYSMMU_FIMC_ODC_OFFSET 0x032C0000 243 #define EXYNOS5_SYSMMU_FIMC_DIS0 0x032D0000 244 #define EXYNOS5_SYSMMU_FIMC_DIS1 0x032E0000 245 #define EXYNOS5_SYSMMU_FIMC_3DNR_OFFSET 0x032F0000 246 /*#define EXYNOS5_GPIO_RIGHT_OFFSET 0x04000000*/ 247 #define EXYNOS5_AS_A_MFC0_OFFSET 0x03620000 248 #define EXYNOS5_AS_A_ISP0_OFFSET 0x03640000 249 #define EXYNOS5_AS_A_ISP1_OFFSET 0x03650000 250 #define EXYNOS5_AS_A_RIGHT1_OFFSET 0x03670000 251 #define EXYNOS5_FIMC_LITE0_OFFSET 0x03C00000 252 #define EXYNOS5_FIMC_LITE1_OFFSET 0x03C10000 253 #define EXYNOS5_MIPI_CSI0_OFFSET 0x03C20000 254 #define EXYNOS5_MIPI_CSI1_OFFSET 0x03C30000 255 #define EXYNOS5_SYSMMU_FIMC_LITE0_OFFSET 0x03C40000 256 #define EXYNOS5_SYSMMU_FIMC_LITE1_OFFSET 0x03C50000 257 #define EXYNOS5_FIMC_LITE2_OFFSET 0x03C90000 258 #define EXYNOS5_SYSMMU_FIMC_LITE2_OFFSET 0x03CA0000 259 #define EXYNOS5_GSCALER0_OFFSET 0x03E00000 260 #define EXYNOS5_GSCALER1_OFFSET 0x03E10000 261 #define EXYNOS5_GSCALER2_OFFSET 0x03E20000 262 #define EXYNOS5_GSCALER3_OFFSET 0x03E30000 263 #define EXYNOS5_AS_A_GS0_OFFSET 0x03E40000 264 #define EXYNOS5_AS_A_GS1_OFFSET 0x03E50000 265 #define EXYNOS5_AS_A_GS2_OFFSET 0x03E60000 266 #define EXYNOS5_AS_A_GS3_OFFSET 0x03E70000 267 #define EXYNOS5_SYSMMU_GSCALER0_OFFSET 0x03E80000 268 #define EXYNOS5_SYSMMU_GSCALER1_OFFSET 0x03E90000 269 #define EXYNOS5_SYSMMU_GSCALER2_OFFSET 0x03EA0000 270 #define EXYNOS5_SYSMMU_GSCALER3_OFFSET 0x03EB0000 271 #define EXYNOS5_GPIO_USB_OFFSET 0x04000000 272 #define EXYNOS5_AS_A_GSCALER_OFFSET 0x04220000 273 #define EXYNOS5_DISP1_MIX_OFFSET 0x04400000 274 #define EXYNOS5_DISP1_ENH_OFFSET 0x04410000 275 #define EXYNOS5_DISP1_CTRL_OFFSET 0x04420000 276 #define EXYNOS5_MIE_OFFSET 0x04430000 277 #define EXYNOS5_TV_MIXER_OFFSET 0x04450000 278 #define EXYNOS5_MIPI_DSI1_OFFSET 0x04500000 279 #define EXYNOS5_DP1_OFFSET 0x04510000 280 #define EXYNOS5_HDMI_0_OFFSET 0x04530000 281 #define EXYNOS5_HDMI_1_OFFSET 0x04540000 282 #define EXYNOS5_HDMI_2_OFFSET 0x04550000 283 #define EXYNOS5_HDMI_3_OFFSET 0x04560000 284 #define EXYNOS5_HDMI_4_OFFSET 0x04570000 285 #define EXYNOS5_HDMI_5_OFFSET 0x04580000 286 #define EXYNOS5_HDMI_6_OFFSET 0x04590000 287 #define EXYNOS5_DP1_1_OFFSET 0x045B0000 288 #define EXYNOS5_SYSMMU_DISP1_OFFSET 0x04640000 289 #define EXYNOS5_SYSMMU_TV_OFFSET 0x04650000 290 #define EXYNOS5_AS_A_TV_OFFSET 0x046D0000 291 #if 0 292 #define EXYNOS5_AES0&EF0 (NEW) 0x08000000 293 #define EXYNOS5_AES0&EF0 (NEW) 0x08010000 294 #define EXYNOS5_AES0&EF0 (NEW) 0x08020000 295 #define EXYNOS5_AES0&EF0 (NEW) 0x08030000 296 #define EXYNOS5_AES0&EF0 (NEW) 0x08040000 297 #define EXYNOS5_AES0&EF0 (NEW) 0x08050000 298 #define EXYNOS5_AES0&EF0 (NEW) 0x08060000 299 #define EXYNOS5_AES0&EF0 (NEW) 0x08070000 300 #define EXYNOS5_AES0&EF0 (NER) 0x08080000 301 #define EXYNOS5_AES0&EF0 (NER) 0x08090000 302 #define EXYNOS5_AES0&EF0 (NER) 0x080A0000 303 #define EXYNOS5_AES0&EF0 (NER) 0x080B0000 304 #define EXYNOS5_AES0&EF0 (NER) 0x080C0000 305 #define EXYNOS5_AES0&EF0 (NER) 0x080D0000 306 #define EXYNOS5_AES0&EF0 (NER) 0x080E0000 307 #define EXYNOS5_AES0&EF0 (NER) 0x080F0000 308 #define EXYNOS5_AES0&EF0 (EW) 0x08100000 309 #define EXYNOS5_AES0&EF0 (EW) 0x08110000 310 #define EXYNOS5_AES0&EF0 (EW) 0x08120000 311 #define EXYNOS5_AES0&EF0 (EW) 0x08130000 312 #define EXYNOS5_AES0&EF0 (EW) 0x08140000 313 #define EXYNOS5_AES0&EF0 (EW) 0x08150000 314 #define EXYNOS5_AES0&EF0 (EW) 0x08160000 315 #define EXYNOS5_AES0&EF0 (EW) 0x08170000 316 #define EXYNOS5_AES0&EF0 (ER) 0x08180000 317 #define EXYNOS5_AES0&EF0 (ER) 0x08190000 318 #define EXYNOS5_AES0&EF0 (ER) 0x081A0000 319 #define EXYNOS5_AES0&EF0 (ER) 0x081B0000 320 #define EXYNOS5_AES0&EF0 (ER) 0x081C0000 321 #define EXYNOS5_AES0&EF0 (ER) 0x081D0000 322 #define EXYNOS5_AES0&EF0 (ER) 0x081E0000 323 #define EXYNOS5_AES0&EF0 (ER) 0x081F0000 324 #define EXYNOS5_EFCON0_OFFSET 0x08200000 325 #define EXYNOS5_AES0 SFR_OFFSET 0x08300000 326 #define EXYNOS5_AES1&EF1 (NEW) 0x08400000 327 #define EXYNOS5_AES1&EF1 (NEW) 0x08410000 328 #define EXYNOS5_AES1&EF1 (NEW) 0x08420000 329 #define EXYNOS5_AES1&EF1 (NEW) 0x08430000 330 #define EXYNOS5_AES1&EF1 (NEW) 0x08440000 331 #define EXYNOS5_AES1&EF1 (NEW) 0x08450000 332 #define EXYNOS5_AES1&EF1 (NEW) 0x08460000 333 #define EXYNOS5_AES1&EF1 (NEW) 0x08470000 334 #define EXYNOS5_AES1&EF1 (NER) 0x08480000 335 #define EXYNOS5_AES1&EF1 (NER) 0x08490000 336 #define EXYNOS5_AES1&EF1 (NER) 0x084A0000 337 #define EXYNOS5_AES1&EF1 (NER) 0x084B0000 338 #define EXYNOS5_AES1&EF1 (NER) 0x084C0000 339 #define EXYNOS5_AES1&EF1 (NER) 0x084D0000 340 #define EXYNOS5_AES1&EF1 (NER) 0x084E0000 341 #define EXYNOS5_AES1&EF1 (NER) 0x084F0000 342 #define EXYNOS5_AES1&EF1 (EW) 0x08500000 343 #define EXYNOS5_AES1&EF1 (EW) 0x08510000 344 #define EXYNOS5_AES1&EF1 (EW) 0x08520000 345 #define EXYNOS5_AES1&EF1 (EW) 0x08530000 346 #define EXYNOS5_AES1&EF1 (EW) 0x08540000 347 #define EXYNOS5_AES1&EF1 (EW) 0x08550000 348 #define EXYNOS5_AES1&EF1 (EW) 0x08560000 349 #define EXYNOS5_AES1&EF1 (EW) 0x08570000 350 #define EXYNOS5_AES1&EF1 (ER) 0x08580000 351 #define EXYNOS5_AES1&EF1 (ER) 0x08590000 352 #define EXYNOS5_AES1&EF1 (ER) 0x085A0000 353 #define EXYNOS5_AES1&EF1 (ER) 0x085B0000 354 #define EXYNOS5_AES1&EF1 (ER) 0x085C0000 355 #define EXYNOS5_AES1&EF1 (ER) 0x085D0000 356 #define EXYNOS5_AES1&EF1 (ER) 0x085E0000 357 #define EXYNOS5_AES1&EF1 (ER) 0x085F0000 358 #endif 359 #define EXYNOS5_EFCON1_OFFSET 0x08600000 360 #define EXYNOS5_NS_NDMA_OFFSET 0x08680000 361 #define EXYNOS5_S_NDMA_OFFSET 0x08690000 362 #define EXYNOS5_AES1_OFFSET 0x08700000 363 364 /* AUDIOCORE */ 365 #define EXYNOS5_AUDIOCORE_VBASE (EXYNOS_CORE_VBASE + EXYNOS5_CORE_SIZE) 366 #define EXYNOS5_AUDIOCORE_PBASE 0x03800000 /* Audio SFR */ 367 #define EXYNOS5_GPIO_I2S_OFFSET (EXYNOS5_CORE_SIZE + 0x00060000) 368 #define EXYNOS5_AUDIOCORE_SIZE 0x00100000 369 370 #define EXYNOS5_SYSRAM_VBASE (EXYNOS5_AUDIOCORE_VBASE + EXYNOS5_AUDIOCORE_SIZE) 371 #define EXYNOS5_SYSRAM_PBASE 0x02000000 372 #define EXYNOS5_SYSRAM_SIZE 0x00100000 373 374 375 /* used Exynos5 USB PHY registers */ 376 #define USB_PHY_HOST_CTRL0 0x00 377 #define HOST_CTRL0_PHY_SWRST __BIT(0) 378 #define HOST_CTRL0_LINK_SWRST __BIT(1) 379 #define HOST_CTRL0_UTMI_SWRST __BIT(2) 380 #define HOST_CTRL0_WORDINTERFACE __BIT(3) 381 #define HOST_CTRL0_FORCESUSPEND __BIT(4) 382 #define HOST_CTRL0_FORCESLEEP __BIT(5) 383 #define HOST_CTRL0_SIDDQ __BIT(6) 384 #define HOST_CTRL0_COMMONON_N __BIT(9) /* common block configuration during suspend */ 385 #define HOST_CTRL0_RETENABLE __BIT(10) 386 #define HOST_CTRL0_TESTBURNIN __BIT(11) 387 #define HOST_CTRL0_FSEL_MASK __BITS(16, 18) /* holds FSEL_CLKSEL_ */ 388 #define HOST_CTRL0_REFCLKSEL_MASK __BITS(19, 20) 389 #define HOST_CTRL0_REFCLKSEL_XTAL 0 390 #define HOST_CTRL0_REFCLKSEL_EXTL 1 391 #define HOST_CTRL0_REFCLKSEL_CLKCORE 2 392 #define HOST_CTRL0_PHY_SWRST_ALL __BIT(31) 393 394 #define USB_PHY_HSIC_CTRL1 0x10 395 #define USB_PHY_HSIC_TUNE1 0x14 396 #define USB_PHY_HSIC_CTRL2 0x20 397 #define USB_PHY_HSIC_TUNE2 0x24 398 399 #define HSIC_CTRL_PHY_SWRST __BIT(0) 400 #define HSIC_CTRL_UTMI_SWRST __BIT(2) 401 #define HSIC_CTRL_WORDINTERFACE __BIT(3) 402 #define HSIC_CTRL_FORCESUSPEND __BIT(4) 403 #define HSIC_CTRL_FORCESLEEP __BIT(5) 404 #define HSIC_CTRL_SIDDQ __BIT(6) 405 #define HSIC_CTRL_REFCLKDIV_MASK __BITS(16,22) 406 #define HSIC_CTRL_REFCLKDIV_12 0x24 407 #define HSIC_CTRL_REFCLKDIV_15 0x1c 408 #define HSIC_CTRL_REFCLKDIV_16 0x1a 409 #define HSIC_CTRL_REFCLKDIV_19_2 0x15 410 #define HSIC_CTRL_REFCLKDIV_20 0x14 411 #define HSIC_CTRL_REFCLKSEL_MASK __BITS(23, 24) 412 #define HSIC_CTRL_REFCLKSEL_DEFAULT 2 413 414 #define USB_PHY_HOST_EHCICTRL 0x30 415 #define HOST_EHCICTRL_ENA_INCR16 __BIT(26) 416 #define HOST_EHCICTRL_ENA_INCR8 __BIT(27) 417 #define HOST_EHCICTRL_ENA_INCR4 __BIT(28) 418 #define HOST_EHCICTRL_ENA_INCRXALIGN __BIT(29) 419 420 #define USB_PHY_HOST_OHCICTRL 0x34 421 #define HOST_OHCICTRL_CLKCK_RST __BIT(0) 422 #define HOST_OHCICTRL_CNTSEL __BIT(1) 423 #define HOST_OHCICTRL_APPSTARTCLK __BIT(2) 424 #define HOST_OHCICTRL_SUSPLGCY __BIT(3) 425 426 #define USB_PHY_OTG_SYS 0x38 427 #define OTG_SYS_FORCESUSPEND __BIT(0) 428 #define OTG_SYS_SIDDQ_UOTG __BIT(1) 429 #define OTG_SYS_OTGDISABLE __BIT(2) 430 #define OTG_SYS_FORCESLEEP __BIT(3) 431 #define OTG_SYS_FSEL_MASK __BITS(4, 6) /* holds FSEL_CLKSEL_ */ 432 #define OTG_SYS_COMMON_ON __BIT(7) 433 #define OTG_SYS_IDPULLUP_UOTG __BIT(8) 434 #define OTG_SYS_REFCLKSEL_MASK __BITS(9, 10) 435 #define OTG_SYS_REFCLKSEL_XTAL __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 0) 436 #define OTG_SYS_REFCLKSEL_EXTL __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 1) 437 #define OTG_SYS_REFCLKSEL_CLKCORE __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 2) 438 #define OTG_SYS_PHY0_SWRST __BIT(12) 439 #define OTG_SYS_LINK_SWRST_UOTG __BIT(13) 440 #define OTG_SYS_PHYLINK_SWRST __BIT(14) 441 442 #endif /* _ARM_SAMSUNG_EXYNOS5_REG_H_ */ 443
Indexes created Sat Sep 20 22:09:52 GMT 2025