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      1 /* $NetBSD: exynos_clock.h,v 1.1 2015/12/05 13:32:27 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _ARM_EXYNOS_CLOCK_H
     30 #define _ARM_EXYNOS_CLOCK_H
     31 
     32 #include <dev/clk/clk.h>
     33 
     34 enum exynos_clk_type {
     35 	EXYNOS_CLK_FIXED,
     36 	EXYNOS_CLK_PLL,
     37 	EXYNOS_CLK_MUX,
     38 	EXYNOS_CLK_DIV,
     39 	EXYNOS_CLK_GATE
     40 };
     41 
     42 struct exynos_fixed_clk {
     43 	u_int rate;
     44 };
     45 
     46 struct exynos_pll_clk {
     47 	u_int lock_reg;
     48 	u_int con0_reg;
     49 };
     50 
     51 struct exynos_mux_clk {
     52 	const char **parents;
     53 	u_int nparents;
     54 	u_int reg;
     55 	u_int bits;
     56 };
     57 
     58 struct exynos_div_clk {
     59 	u_int reg;
     60 	u_int bits;
     61 };
     62 
     63 struct exynos_gate_clk {
     64 	u_int reg;
     65 	u_int bits;
     66 };
     67 
     68 struct exynos_clk {
     69 	struct clk base;		/* must be first */
     70 	enum exynos_clk_type type;
     71 	const char *alias;
     72 	const char *parent;
     73 	u_int refcnt;
     74 	union {
     75 		struct exynos_fixed_clk fixed;
     76 		struct exynos_pll_clk pll;
     77 		struct exynos_mux_clk mux;
     78 		struct exynos_div_clk div;
     79 		struct exynos_gate_clk gate;
     80 	} u;
     81 };
     82 
     83 #endif /* _ARM_EXYNOS_CLOCK_H */
     84