1 /****************************************************************************** 2 * 3 * Name: actbl1.h - Additional ACPI table definitions 4 * 5 *****************************************************************************/ 6 7 /* 8 * Copyright (C) 2000 - 2026, Intel Corp. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 */ 43 44 #ifndef __ACTBL1_H__ 45 #define __ACTBL1_H__ 46 47 48 /******************************************************************************* 49 * 50 * Additional ACPI Tables 51 * 52 * These tables are not consumed directly by the ACPICA subsystem, but are 53 * included here to support device drivers and the AML disassembler. 54 * 55 ******************************************************************************/ 56 57 58 /* 59 * Values for description table header signatures for tables defined in this 60 * file. Useful because they make it more difficult to inadvertently type in 61 * the wrong signature. 62 */ 63 #define ACPI_SIG_AEST "AEST" /* Arm Error Source Table */ 64 #define ACPI_SIG_ASF "ASF!" /* Alert Standard Format table */ 65 #define ACPI_SIG_ASPT "ASPT" /* AMD Secure Processor Table */ 66 #define ACPI_SIG_BERT "BERT" /* Boot Error Record Table */ 67 #define ACPI_SIG_BGRT "BGRT" /* Boot Graphics Resource Table */ 68 #define ACPI_SIG_BOOT "BOOT" /* Simple Boot Flag Table */ 69 #define ACPI_SIG_CEDT "CEDT" /* CXL Early Discovery Table */ 70 #define ACPI_SIG_CPEP "CPEP" /* Corrected Platform Error Polling table */ 71 #define ACPI_SIG_CSRT "CSRT" /* Core System Resource Table */ 72 #define ACPI_SIG_DBG2 "DBG2" /* Debug Port table type 2 */ 73 #define ACPI_SIG_DBGP "DBGP" /* Debug Port table */ 74 #define ACPI_SIG_DMAR "DMAR" /* DMA Remapping table */ 75 #define ACPI_SIG_DRTM "DRTM" /* Dynamic Root of Trust for Measurement table */ 76 #define ACPI_SIG_DTPR "DTPR" /* DMA TXT Protection Ranges table */ 77 #define ACPI_SIG_ECDT "ECDT" /* Embedded Controller Boot Resources Table */ 78 #define ACPI_SIG_EINJ "EINJ" /* Error Injection table */ 79 #define ACPI_SIG_ERST "ERST" /* Error Record Serialization Table */ 80 #define ACPI_SIG_FPDT "FPDT" /* Firmware Performance Data Table */ 81 #define ACPI_SIG_GTDT "GTDT" /* Generic Timer Description Table */ 82 #define ACPI_SIG_HEST "HEST" /* Hardware Error Source Table */ 83 #define ACPI_SIG_HMAT "HMAT" /* Heterogeneous Memory Attributes Table */ 84 #define ACPI_SIG_HPET "HPET" /* High Precision Event Timer table */ 85 #define ACPI_SIG_IBFT "IBFT" /* iSCSI Boot Firmware Table */ 86 #define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table*/ 87 88 #define ACPI_SIG_S3PT "S3PT" /* S3 Performance (sub)Table */ 89 #define ACPI_SIG_PCCS "PCC" /* PCC Shared Memory Region */ 90 91 92 /* Reserved table signatures */ 93 94 #define ACPI_SIG_MATR "MATR" /* Memory Address Translation Table */ 95 #define ACPI_SIG_MSDM "MSDM" /* Microsoft Data Management Table */ 96 97 /* 98 * These tables have been seen in the field, but no definition has been found 99 */ 100 #ifdef ACPI_UNDEFINED_TABLES 101 #define ACPI_SIG_ATKG "ATKG" 102 #define ACPI_SIG_GSCI "GSCI" /* GMCH SCI table */ 103 #define ACPI_SIG_IEIT "IEIT" 104 #endif 105 106 /* 107 * All tables must be byte-packed to match the ACPI specification, since 108 * the tables are provided by the system BIOS. 109 */ 110 #pragma pack(1) 111 112 /* 113 * Note: C bitfields are not used for this reason: 114 * 115 * "Bitfields are great and easy to read, but unfortunately the C language 116 * does not specify the layout of bitfields in memory, which means they are 117 * essentially useless for dealing with packed data in on-disk formats or 118 * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me, 119 * this decision was a design error in C. Ritchie could have picked an order 120 * and stuck with it." Norman Ramsey. 121 * See http://stackoverflow.com/a/1053662/41661 122 */ 123 124 125 /******************************************************************************* 126 * 127 * Common subtable headers 128 * 129 ******************************************************************************/ 130 131 /* Generic subtable header (used in MADT, SRAT, etc.) */ 132 133 typedef struct acpi_subtable_header 134 { 135 UINT8 Type; 136 UINT8 Length; 137 138 } ACPI_SUBTABLE_HEADER; 139 140 141 /* Subtable header for WHEA tables (EINJ, ERST, WDAT) */ 142 143 typedef struct acpi_whea_header 144 { 145 UINT8 Action; 146 UINT8 Instruction; 147 UINT8 Flags; 148 UINT8 Reserved; 149 ACPI_GENERIC_ADDRESS RegisterRegion; 150 UINT64 Value; /* Value used with Read/Write register */ 151 UINT64 Mask; /* Bitmask required for this register instruction */ 152 153 } ACPI_WHEA_HEADER; 154 155 156 /* Larger subtable header (when Length can exceed 255) */ 157 158 typedef struct acpi_subtbl_hdr_16 159 { 160 UINT16 Type; 161 UINT16 Length; 162 163 } ACPI_SUBTBL_HDR_16; 164 165 166 /******************************************************************************* 167 * 168 * ASF - Alert Standard Format table (Signature "ASF!") 169 * Revision 0x10 170 * 171 * Conforms to the Alert Standard Format Specification V2.0, 23 April 2003 172 * 173 ******************************************************************************/ 174 175 typedef struct acpi_table_asf 176 { 177 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 178 179 } ACPI_TABLE_ASF; 180 181 182 /* ASF subtable header */ 183 184 typedef struct acpi_asf_header 185 { 186 UINT8 Type; 187 UINT8 Reserved; 188 UINT16 Length; 189 190 } ACPI_ASF_HEADER; 191 192 193 /* Values for Type field above */ 194 195 enum AcpiAsfType 196 { 197 ACPI_ASF_TYPE_INFO = 0, 198 ACPI_ASF_TYPE_ALERT = 1, 199 ACPI_ASF_TYPE_CONTROL = 2, 200 ACPI_ASF_TYPE_BOOT = 3, 201 ACPI_ASF_TYPE_ADDRESS = 4, 202 ACPI_ASF_TYPE_RESERVED = 5 203 }; 204 205 /* 206 * ASF subtables 207 */ 208 209 /* 0: ASF Information */ 210 211 typedef struct acpi_asf_info 212 { 213 ACPI_ASF_HEADER Header; 214 UINT8 MinResetValue; 215 UINT8 MinPollInterval; 216 UINT16 SystemId; 217 UINT32 MfgId; 218 UINT8 Flags; 219 UINT8 Reserved2[3]; 220 221 } ACPI_ASF_INFO; 222 223 /* Masks for Flags field above */ 224 225 #define ACPI_ASF_SMBUS_PROTOCOLS (1) 226 227 228 /* 1: ASF Alerts */ 229 230 typedef struct acpi_asf_alert 231 { 232 ACPI_ASF_HEADER Header; 233 UINT8 AssertMask; 234 UINT8 DeassertMask; 235 UINT8 Alerts; 236 UINT8 DataLength; 237 238 } ACPI_ASF_ALERT; 239 240 typedef struct acpi_asf_alert_data 241 { 242 UINT8 Address; 243 UINT8 Command; 244 UINT8 Mask; 245 UINT8 Value; 246 UINT8 SensorType; 247 UINT8 Type; 248 UINT8 Offset; 249 UINT8 SourceType; 250 UINT8 Severity; 251 UINT8 SensorNumber; 252 UINT8 Entity; 253 UINT8 Instance; 254 255 } ACPI_ASF_ALERT_DATA; 256 257 258 /* 2: ASF Remote Control */ 259 260 typedef struct acpi_asf_remote 261 { 262 ACPI_ASF_HEADER Header; 263 UINT8 Controls; 264 UINT8 DataLength; 265 UINT16 Reserved2; 266 267 } ACPI_ASF_REMOTE; 268 269 typedef struct acpi_asf_control_data 270 { 271 UINT8 Function; 272 UINT8 Address; 273 UINT8 Command; 274 UINT8 Value; 275 276 } ACPI_ASF_CONTROL_DATA; 277 278 279 /* 3: ASF RMCP Boot Options */ 280 281 typedef struct acpi_asf_rmcp 282 { 283 ACPI_ASF_HEADER Header; 284 UINT8 Capabilities[7]; 285 UINT8 CompletionCode; 286 UINT32 EnterpriseId; 287 UINT8 Command; 288 UINT16 Parameter; 289 UINT16 BootOptions; 290 UINT16 OemParameters; 291 292 } ACPI_ASF_RMCP; 293 294 295 /* 4: ASF Address */ 296 297 typedef struct acpi_asf_address 298 { 299 ACPI_ASF_HEADER Header; 300 UINT8 EpromAddress; 301 UINT8 Devices; 302 303 } ACPI_ASF_ADDRESS; 304 305 /******************************************************************************* 306 * 307 * ASPT - AMD Secure Processor Table (Signature "ASPT") 308 * Revision 0x1 309 * 310 * Conforms to AMD Socket SP5/SP6 Platform ASPT Rev1 Specification, 311 * 12 September 2022 312 * 313 ******************************************************************************/ 314 315 typedef struct acpi_table_aspt 316 { 317 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 318 UINT32 NumEntries; 319 320 } ACPI_TABLE_ASPT; 321 322 323 /* ASPT subtable header */ 324 325 typedef struct acpi_aspt_header 326 { 327 UINT16 Type; 328 UINT16 Length; 329 330 } ACPI_ASPT_HEADER; 331 332 333 /* Values for Type field above */ 334 335 enum AcpiAsptType 336 { 337 ACPI_ASPT_TYPE_GLOBAL_REGS = 0, 338 ACPI_ASPT_TYPE_SEV_MBOX_REGS = 1, 339 ACPI_ASPT_TYPE_ACPI_MBOX_REGS = 2, 340 ACPI_ASPT_TYPE_UNKNOWN = 3, 341 }; 342 343 /* 344 * ASPT subtables 345 */ 346 347 /* 0: ASPT Global Registers */ 348 349 typedef struct acpi_aspt_global_regs 350 { 351 ACPI_ASPT_HEADER Header; 352 UINT32 Reserved; 353 UINT64 FeatureRegAddr; 354 UINT64 IrqEnRegAddr; 355 UINT64 IrqStRegAddr; 356 357 } ACPI_ASPT_GLOBAL_REGS; 358 359 360 /* 1: ASPT SEV Mailbox Registers */ 361 362 typedef struct acpi_aspt_sev_mbox_regs 363 { 364 ACPI_ASPT_HEADER Header; 365 UINT8 MboxIrqId; 366 UINT8 Reserved[3]; 367 UINT64 CmdRespRegAddr; 368 UINT64 CmdBufLoRegAddr; 369 UINT64 CmdBufHiRegAddr; 370 371 } ACPI_ASPT_SEV_MBOX_REGS; 372 373 374 /* 2: ASPT ACPI Mailbox Registers */ 375 376 typedef struct acpi_aspt_acpi_mbox_regs 377 { 378 ACPI_ASPT_HEADER Header; 379 UINT32 Reserved1; 380 UINT64 CmdRespRegAddr; 381 UINT64 Reserved2[2]; 382 383 } ACPI_ASPT_ACPI_MBOX_REGS; 384 385 386 /******************************************************************************* 387 * 388 * BERT - Boot Error Record Table (ACPI 4.0) 389 * Version 1 390 * 391 ******************************************************************************/ 392 393 typedef struct acpi_table_bert 394 { 395 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 396 UINT32 RegionLength; /* Length of the boot error region */ 397 UINT64 Address; /* Physical address of the error region */ 398 399 } ACPI_TABLE_BERT; 400 401 402 /* Boot Error Region (not a subtable, pointed to by Address field above) */ 403 404 typedef struct acpi_bert_region 405 { 406 UINT32 BlockStatus; /* Type of error information */ 407 UINT32 RawDataOffset; /* Offset to raw error data */ 408 UINT32 RawDataLength; /* Length of raw error data */ 409 UINT32 DataLength; /* Length of generic error data */ 410 UINT32 ErrorSeverity; /* Severity code */ 411 412 } ACPI_BERT_REGION; 413 414 /* Values for BlockStatus flags above */ 415 416 #define ACPI_BERT_UNCORRECTABLE (1) 417 #define ACPI_BERT_CORRECTABLE (1<<1) 418 #define ACPI_BERT_MULTIPLE_UNCORRECTABLE (1<<2) 419 #define ACPI_BERT_MULTIPLE_CORRECTABLE (1<<3) 420 #define ACPI_BERT_ERROR_ENTRY_COUNT (0xFF<<4) /* 8 bits, error count */ 421 422 /* Values for ErrorSeverity above */ 423 424 enum AcpiBertErrorSeverity 425 { 426 ACPI_BERT_ERROR_CORRECTABLE = 0, 427 ACPI_BERT_ERROR_FATAL = 1, 428 ACPI_BERT_ERROR_CORRECTED = 2, 429 ACPI_BERT_ERROR_NONE = 3, 430 ACPI_BERT_ERROR_RESERVED = 4 /* 4 and greater are reserved */ 431 }; 432 433 /* 434 * Note: The generic error data that follows the ErrorSeverity field above 435 * uses the ACPI_HEST_GENERIC_DATA defined under the HEST table below 436 */ 437 438 439 /******************************************************************************* 440 * 441 * BGRT - Boot Graphics Resource Table (ACPI 5.0) 442 * Version 1 443 * 444 ******************************************************************************/ 445 446 typedef struct acpi_table_bgrt 447 { 448 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 449 UINT16 Version; 450 UINT8 Status; 451 UINT8 ImageType; 452 UINT64 ImageAddress; 453 UINT32 ImageOffsetX; 454 UINT32 ImageOffsetY; 455 456 } ACPI_TABLE_BGRT; 457 458 /* Flags for Status field above */ 459 460 #define ACPI_BGRT_DISPLAYED (1) 461 #define ACPI_BGRT_ORIENTATION_OFFSET (3 << 1) 462 463 464 /******************************************************************************* 465 * 466 * BOOT - Simple Boot Flag Table 467 * Version 1 468 * 469 * Conforms to the "Simple Boot Flag Specification", Version 2.1 470 * 471 ******************************************************************************/ 472 473 typedef struct acpi_table_boot 474 { 475 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 476 UINT8 CmosIndex; /* Index in CMOS RAM for the boot register */ 477 UINT8 Reserved[3]; 478 479 } ACPI_TABLE_BOOT; 480 481 482 /******************************************************************************* 483 * 484 * CDAT - Coherent Device Attribute Table 485 * Version 1 486 * 487 * Conforms to the "Coherent Device Attribute Table (CDAT) Specification 488 " (Revision 1.01, October 2020.) 489 * 490 ******************************************************************************/ 491 492 typedef struct acpi_table_cdat 493 { 494 UINT32 Length; /* Length of table in bytes, including this header */ 495 UINT8 Revision; /* ACPI Specification minor version number */ 496 UINT8 Checksum; /* To make sum of entire table == 0 */ 497 UINT8 Reserved[6]; 498 UINT32 Sequence; /* Used to detect runtime CDAT table changes */ 499 500 } ACPI_TABLE_CDAT; 501 502 503 /* CDAT common subtable header */ 504 505 typedef struct acpi_cdat_header 506 { 507 UINT8 Type; 508 UINT8 Reserved; 509 UINT16 Length; 510 511 } ACPI_CDAT_HEADER; 512 513 /* Values for Type field above */ 514 515 enum AcpiCdatType 516 { 517 ACPI_CDAT_TYPE_DSMAS = 0, 518 ACPI_CDAT_TYPE_DSLBIS = 1, 519 ACPI_CDAT_TYPE_DSMSCIS = 2, 520 ACPI_CDAT_TYPE_DSIS = 3, 521 ACPI_CDAT_TYPE_DSEMTS = 4, 522 ACPI_CDAT_TYPE_SSLBIS = 5, 523 ACPI_CDAT_TYPE_RESERVED = 6 /* 6 through 0xFF are reserved */ 524 }; 525 526 527 /* Subtable 0: Device Scoped Memory Affinity Structure (DSMAS) */ 528 529 typedef struct acpi_cdat_dsmas 530 { 531 UINT8 DsmadHandle; 532 UINT8 Flags; 533 UINT16 Reserved; 534 UINT64 DpaBaseAddress; 535 UINT64 DpaLength; 536 537 } ACPI_CDAT_DSMAS; 538 539 /* Flags for subtable above */ 540 541 #define ACPI_CDAT_DSMAS_NON_VOLATILE (1 << 2) 542 #define ACPI_CDAT_DSMAS_SHAREABLE (1 << 3) 543 #define ACPI_CDAT_DSMAS_READ_ONLY (1 << 6) 544 545 546 /* Subtable 1: Device scoped Latency and Bandwidth Information Structure (DSLBIS) */ 547 548 typedef struct acpi_cdat_dslbis 549 { 550 UINT8 Handle; 551 UINT8 Flags; /* If Handle matches a DSMAS handle, the definition of this field matches 552 * Flags field in HMAT System Locality Latency */ 553 UINT8 DataType; 554 UINT8 Reserved; 555 UINT64 EntryBaseUnit; 556 UINT16 Entry[3]; 557 UINT16 Reserved2; 558 559 } ACPI_CDAT_DSLBIS; 560 561 562 /* Subtable 2: Device Scoped Memory Side Cache Information Structure (DSMSCIS) */ 563 564 typedef struct acpi_cdat_dsmscis 565 { 566 UINT8 DsmasHandle; 567 UINT8 Reserved[3]; 568 UINT64 SideCacheSize; 569 UINT32 CacheAttributes; 570 571 } ACPI_CDAT_DSMSCIS; 572 573 574 /* Subtable 3: Device Scoped Initiator Structure (DSIS) */ 575 576 typedef struct acpi_cdat_dsis 577 { 578 UINT8 Flags; 579 UINT8 Handle; 580 UINT16 Reserved; 581 582 } ACPI_CDAT_DSIS; 583 584 /* Flags for above subtable */ 585 586 #define ACPI_CDAT_DSIS_MEM_ATTACHED (1 << 0) 587 588 589 /* Subtable 4: Device Scoped EFI Memory Type Structure (DSEMTS) */ 590 591 typedef struct acpi_cdat_dsemts 592 { 593 UINT8 DsmasHandle; 594 UINT8 MemoryType; 595 UINT16 Reserved; 596 UINT64 DpaOffset; 597 UINT64 RangeLength; 598 599 } ACPI_CDAT_DSEMTS; 600 601 602 /* Subtable 5: Switch Scoped Latency and Bandwidth Information Structure (SSLBIS) */ 603 604 typedef struct acpi_cdat_sslbis 605 { 606 UINT8 DataType; 607 UINT8 Reserved[3]; 608 UINT64 EntryBaseUnit; 609 610 } ACPI_CDAT_SSLBIS; 611 612 613 /* Sub-subtable for above, SslbeEntries field */ 614 615 typedef struct acpi_cdat_sslbe 616 { 617 UINT16 PortxId; 618 UINT16 PortyId; 619 UINT16 LatencyOrBandwidth; 620 UINT16 Reserved; 621 622 } ACPI_CDAT_SSLBE; 623 624 #define ACPI_CDAT_SSLBIS_US_PORT 0x0100 625 #define ACPI_CDAT_SSLBIS_ANY_PORT 0xffff 626 627 /******************************************************************************* 628 * 629 * CEDT - CXL Early Discovery Table 630 * Version 1 631 * 632 * Conforms to the "CXL Early Discovery Table" (CXL 2.0, October 2020) 633 * 634 ******************************************************************************/ 635 636 typedef struct acpi_table_cedt 637 { 638 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 639 640 } ACPI_TABLE_CEDT; 641 642 /* CEDT subtable header (Performance Record Structure) */ 643 644 typedef struct acpi_cedt_header 645 { 646 UINT8 Type; 647 UINT8 Reserved; 648 UINT16 Length; 649 650 } ACPI_CEDT_HEADER; 651 652 /* Values for Type field above */ 653 654 enum AcpiCedtType 655 { 656 ACPI_CEDT_TYPE_CHBS = 0, 657 ACPI_CEDT_TYPE_CFMWS = 1, 658 ACPI_CEDT_TYPE_CXIMS = 2, 659 ACPI_CEDT_TYPE_RDPAS = 3, 660 ACPI_CEDT_TYPE_RESERVED = 4, 661 }; 662 663 /* Values for version field above */ 664 665 #define ACPI_CEDT_CHBS_VERSION_CXL11 (0) 666 #define ACPI_CEDT_CHBS_VERSION_CXL20 (1) 667 668 /* Values for length field above */ 669 670 #define ACPI_CEDT_CHBS_LENGTH_CXL11 (0x2000) 671 #define ACPI_CEDT_CHBS_LENGTH_CXL20 (0x10000) 672 673 /* 674 * CEDT subtables 675 */ 676 677 /* 0: CXL Host Bridge Structure */ 678 679 typedef struct acpi_cedt_chbs 680 { 681 ACPI_CEDT_HEADER Header; 682 UINT32 Uid; 683 UINT32 CxlVersion; 684 UINT32 Reserved; 685 UINT64 Base; 686 UINT64 Length; 687 688 } ACPI_CEDT_CHBS; 689 690 691 /* 1: CXL Fixed Memory Window Structure */ 692 693 typedef struct acpi_cedt_cfmws 694 { 695 ACPI_CEDT_HEADER Header; 696 UINT32 Reserved1; 697 UINT64 BaseHpa; 698 UINT64 WindowSize; 699 UINT8 InterleaveWays; 700 UINT8 InterleaveArithmetic; 701 UINT16 Reserved2; 702 UINT32 Granularity; 703 UINT16 Restrictions; 704 UINT16 QtgId; 705 UINT32 InterleaveTargets[]; 706 707 } ACPI_CEDT_CFMWS; 708 709 typedef struct acpi_cedt_cfmws_target_element 710 { 711 UINT32 InterleaveTarget; 712 713 } ACPI_CEDT_CFMWS_TARGET_ELEMENT; 714 715 /* Values for Interleave Arithmetic field above */ 716 717 #define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0) 718 #define ACPI_CEDT_CFMWS_ARITHMETIC_XOR (1) 719 720 /* Values for Restrictions field above */ 721 722 #define ACPI_CEDT_CFMWS_RESTRICT_DEVMEM (1) 723 #define ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYMEM (1<<1) 724 #define ACPI_CEDT_CFMWS_RESTRICT_VOLATILE (1<<2) 725 #define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3) 726 #define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4) 727 #define ACPI_CEDT_CFMWS_RESTRICT_BI (1<<5) 728 729 /* 2: CXL XOR Interleave Math Structure */ 730 731 typedef struct acpi_cedt_cxims { 732 ACPI_CEDT_HEADER Header; 733 UINT16 Reserved1; 734 UINT8 Hbig; 735 UINT8 NrXormaps; 736 UINT64 XormapList[]; 737 } ACPI_CEDT_CXIMS; 738 739 typedef struct acpi_cedt_cxims_target_element 740 { 741 UINT64 Xormap; 742 743 } ACPI_CEDT_CXIMS_TARGET_ELEMENT; 744 745 746 /* 3: CXL RCEC Downstream Port Association Structure */ 747 748 struct acpi_cedt_rdpas { 749 ACPI_CEDT_HEADER Header; 750 UINT8 Reserved1; 751 UINT16 Length; 752 UINT16 Segment; 753 UINT16 Bdf; 754 UINT8 Protocol; 755 UINT64 Address; 756 }; 757 758 /* Masks for bdf field above */ 759 #define ACPI_CEDT_RDPAS_BUS_MASK 0xff00 760 #define ACPI_CEDT_RDPAS_DEVICE_MASK 0x00f8 761 #define ACPI_CEDT_RDPAS_FUNCTION_MASK 0x0007 762 763 #define ACPI_CEDT_RDPAS_PROTOCOL_IO (0) 764 #define ACPI_CEDT_RDPAS_PROTOCOL_CACHEMEM (1) 765 766 /******************************************************************************* 767 * 768 * CPEP - Corrected Platform Error Polling table (ACPI 4.0) 769 * Version 1 770 * 771 ******************************************************************************/ 772 773 typedef struct acpi_table_cpep 774 { 775 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 776 UINT64 Reserved; 777 778 } ACPI_TABLE_CPEP; 779 780 781 /* Subtable */ 782 783 typedef struct acpi_cpep_polling 784 { 785 ACPI_SUBTABLE_HEADER Header; 786 UINT8 Id; /* Processor ID */ 787 UINT8 Eid; /* Processor EID */ 788 UINT32 Interval; /* Polling interval (msec) */ 789 790 } ACPI_CPEP_POLLING; 791 792 793 /******************************************************************************* 794 * 795 * CSRT - Core System Resource Table 796 * Version 0 797 * 798 * Conforms to the "Core System Resource Table (CSRT)", November 14, 2011 799 * 800 ******************************************************************************/ 801 802 typedef struct acpi_table_csrt 803 { 804 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 805 806 } ACPI_TABLE_CSRT; 807 808 809 /* Resource Group subtable */ 810 811 typedef struct acpi_csrt_group 812 { 813 UINT32 Length; 814 UINT32 VendorId; 815 UINT32 SubvendorId; 816 UINT16 DeviceId; 817 UINT16 SubdeviceId; 818 UINT16 Revision; 819 UINT16 Reserved; 820 UINT32 SharedInfoLength; 821 822 /* Shared data immediately follows (Length = SharedInfoLength) */ 823 824 } ACPI_CSRT_GROUP; 825 826 /* Shared Info subtable */ 827 828 typedef struct acpi_csrt_shared_info 829 { 830 UINT16 MajorVersion; 831 UINT16 MinorVersion; 832 UINT32 MmioBaseLow; 833 UINT32 MmioBaseHigh; 834 UINT32 GsiInterrupt; 835 UINT8 InterruptPolarity; 836 UINT8 InterruptMode; 837 UINT8 NumChannels; 838 UINT8 DmaAddressWidth; 839 UINT16 BaseRequestLine; 840 UINT16 NumHandshakeSignals; 841 UINT32 MaxBlockSize; 842 843 /* Resource descriptors immediately follow (Length = Group Length - SharedInfoLength) */ 844 845 } ACPI_CSRT_SHARED_INFO; 846 847 /* Resource Descriptor subtable */ 848 849 typedef struct acpi_csrt_descriptor 850 { 851 UINT32 Length; 852 UINT16 Type; 853 UINT16 Subtype; 854 UINT32 Uid; 855 856 /* Resource-specific information immediately follows */ 857 858 } ACPI_CSRT_DESCRIPTOR; 859 860 861 /* Resource Types */ 862 863 #define ACPI_CSRT_TYPE_INTERRUPT 0x0001 864 #define ACPI_CSRT_TYPE_TIMER 0x0002 865 #define ACPI_CSRT_TYPE_DMA 0x0003 866 867 /* Resource Subtypes */ 868 869 #define ACPI_CSRT_XRUPT_LINE 0x0000 870 #define ACPI_CSRT_XRUPT_CONTROLLER 0x0001 871 #define ACPI_CSRT_TIMER 0x0000 872 #define ACPI_CSRT_DMA_CHANNEL 0x0000 873 #define ACPI_CSRT_DMA_CONTROLLER 0x0001 874 875 876 /******************************************************************************* 877 * 878 * DBG2 - Debug Port Table 2 879 * Version 0 (Both main table and subtables) 880 * 881 * Conforms to "Microsoft Debug Port Table 2 (DBG2)", September 21, 2020 882 * 883 ******************************************************************************/ 884 885 typedef struct acpi_table_dbg2 886 { 887 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 888 UINT32 InfoOffset; 889 UINT32 InfoCount; 890 891 } ACPI_TABLE_DBG2; 892 893 894 typedef struct acpi_dbg2_header 895 { 896 UINT32 InfoOffset; 897 UINT32 InfoCount; 898 899 } ACPI_DBG2_HEADER; 900 901 902 /* Debug Device Information Subtable */ 903 904 typedef struct acpi_dbg2_device 905 { 906 UINT8 Revision; 907 UINT16 Length; 908 UINT8 RegisterCount; /* Number of BaseAddress registers */ 909 UINT16 NamepathLength; 910 UINT16 NamepathOffset; 911 UINT16 OemDataLength; 912 UINT16 OemDataOffset; 913 UINT16 PortType; 914 UINT16 PortSubtype; 915 UINT16 Reserved; 916 UINT16 BaseAddressOffset; 917 UINT16 AddressSizeOffset; 918 /* 919 * Data that follows: 920 * BaseAddress (required) - Each in 12-byte Generic Address Structure format. 921 * AddressSize (required) - Array of UINT32 sizes corresponding to each BaseAddress register. 922 * Namepath (required) - Null terminated string. Single dot if not supported. 923 * OemData (optional) - Length is OemDataLength. 924 */ 925 } ACPI_DBG2_DEVICE; 926 927 /* Types for PortType field above */ 928 929 #define ACPI_DBG2_SERIAL_PORT 0x8000 930 #define ACPI_DBG2_1394_PORT 0x8001 931 #define ACPI_DBG2_USB_PORT 0x8002 932 #define ACPI_DBG2_NET_PORT 0x8003 933 934 /* Subtypes for PortSubtype field above */ 935 936 #define ACPI_DBG2_16550_COMPATIBLE 0x0000 937 #define ACPI_DBG2_16550_SUBSET 0x0001 938 #define ACPI_DBG2_MAX311XE_SPI 0x0002 939 #define ACPI_DBG2_ARM_PL011 0x0003 940 #define ACPI_DBG2_MSM8X60 0x0004 941 #define ACPI_DBG2_16550_NVIDIA 0x0005 942 #define ACPI_DBG2_TI_OMAP 0x0006 943 #define ACPI_DBG2_APM88XXXX 0x0008 944 #define ACPI_DBG2_MSM8974 0x0009 945 #define ACPI_DBG2_SAM5250 0x000A 946 #define ACPI_DBG2_INTEL_USIF 0x000B 947 #define ACPI_DBG2_IMX6 0x000C 948 #define ACPI_DBG2_ARM_SBSA_32BIT 0x000D 949 #define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E 950 #define ACPI_DBG2_ARM_DCC 0x000F 951 #define ACPI_DBG2_BCM2835 0x0010 952 #define ACPI_DBG2_SDM845_1_8432MHZ 0x0011 953 #define ACPI_DBG2_16550_WITH_GAS 0x0012 954 #define ACPI_DBG2_SDM845_7_372MHZ 0x0013 955 #define ACPI_DBG2_INTEL_LPSS 0x0014 956 957 #define ACPI_DBG2_1394_STANDARD 0x0000 958 959 #define ACPI_DBG2_USB_XHCI 0x0000 960 #define ACPI_DBG2_USB_EHCI 0x0001 961 962 963 /******************************************************************************* 964 * 965 * DBGP - Debug Port table 966 * Version 1 967 * 968 * Conforms to the "Debug Port Specification", Version 1.00, 2/9/2000 969 * 970 ******************************************************************************/ 971 972 typedef struct acpi_table_dbgp 973 { 974 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 975 UINT8 Type; /* 0=full 16550, 1=subset of 16550 */ 976 UINT8 Reserved[3]; 977 ACPI_GENERIC_ADDRESS DebugPort; 978 979 } ACPI_TABLE_DBGP; 980 981 982 /******************************************************************************* 983 * 984 * DMAR - DMA Remapping table 985 * Version 1 986 * 987 * Conforms to "Intel Virtualization Technology for Directed I/O", 988 * Version 2.3, October 2014 989 * 990 ******************************************************************************/ 991 992 typedef struct acpi_table_dmar 993 { 994 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 995 UINT8 Width; /* Host Address Width */ 996 UINT8 Flags; 997 UINT8 Reserved[10]; 998 999 } ACPI_TABLE_DMAR; 1000 1001 /* Masks for Flags field above */ 1002 1003 #define ACPI_DMAR_INTR_REMAP (1) 1004 #define ACPI_DMAR_X2APIC_OPT_OUT (1<<1) 1005 #define ACPI_DMAR_X2APIC_MODE (1<<2) 1006 1007 1008 /* DMAR subtable header */ 1009 1010 typedef struct acpi_dmar_header 1011 { 1012 UINT16 Type; 1013 UINT16 Length; 1014 1015 } ACPI_DMAR_HEADER; 1016 1017 /* Values for subtable type in ACPI_DMAR_HEADER */ 1018 1019 enum AcpiDmarType 1020 { 1021 ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, 1022 ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, 1023 ACPI_DMAR_TYPE_ROOT_ATS = 2, 1024 ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, 1025 ACPI_DMAR_TYPE_NAMESPACE = 4, 1026 ACPI_DMAR_TYPE_SATC = 5, 1027 ACPI_DMAR_TYPE_SIDP = 6, 1028 ACPI_DMAR_TYPE_RESERVED = 7 /* 7 and greater are reserved */ 1029 }; 1030 1031 1032 /* DMAR Device Scope structure */ 1033 1034 typedef struct acpi_dmar_device_scope 1035 { 1036 UINT8 EntryType; 1037 UINT8 Length; 1038 UINT8 Flags; 1039 UINT8 Reserved; 1040 UINT8 EnumerationId; 1041 UINT8 Bus; 1042 1043 } ACPI_DMAR_DEVICE_SCOPE; 1044 1045 /* Values for EntryType in ACPI_DMAR_DEVICE_SCOPE - device types */ 1046 1047 enum AcpiDmarScopeType 1048 { 1049 ACPI_DMAR_SCOPE_TYPE_NOT_USED = 0, 1050 ACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1, 1051 ACPI_DMAR_SCOPE_TYPE_BRIDGE = 2, 1052 ACPI_DMAR_SCOPE_TYPE_IOAPIC = 3, 1053 ACPI_DMAR_SCOPE_TYPE_HPET = 4, 1054 ACPI_DMAR_SCOPE_TYPE_NAMESPACE = 5, 1055 ACPI_DMAR_SCOPE_TYPE_RESERVED = 6 /* 6 and greater are reserved */ 1056 }; 1057 1058 typedef struct acpi_dmar_pci_path 1059 { 1060 UINT8 Device; 1061 UINT8 Function; 1062 1063 } ACPI_DMAR_PCI_PATH; 1064 1065 1066 /* 1067 * DMAR Subtables, correspond to Type in ACPI_DMAR_HEADER 1068 */ 1069 1070 /* 0: Hardware Unit Definition */ 1071 1072 typedef struct acpi_dmar_hardware_unit 1073 { 1074 ACPI_DMAR_HEADER Header; 1075 UINT8 Flags; 1076 UINT8 Size; 1077 UINT16 Segment; 1078 UINT64 Address; /* Register Base Address */ 1079 1080 } ACPI_DMAR_HARDWARE_UNIT; 1081 1082 /* Masks for Flags field above */ 1083 1084 #define ACPI_DMAR_INCLUDE_ALL (1) 1085 1086 1087 /* 1: Reserved Memory Definition */ 1088 1089 typedef struct acpi_dmar_reserved_memory 1090 { 1091 ACPI_DMAR_HEADER Header; 1092 UINT16 Reserved; 1093 UINT16 Segment; 1094 UINT64 BaseAddress; /* 4K aligned base address */ 1095 UINT64 EndAddress; /* 4K aligned limit address */ 1096 1097 } ACPI_DMAR_RESERVED_MEMORY; 1098 1099 /* Masks for Flags field above */ 1100 1101 #define ACPI_DMAR_ALLOW_ALL (1) 1102 1103 1104 /* 2: Root Port ATS Capability Reporting Structure */ 1105 1106 typedef struct acpi_dmar_atsr 1107 { 1108 ACPI_DMAR_HEADER Header; 1109 UINT8 Flags; 1110 UINT8 Reserved; 1111 UINT16 Segment; 1112 1113 } ACPI_DMAR_ATSR; 1114 1115 /* Masks for Flags field above */ 1116 1117 #define ACPI_DMAR_ALL_PORTS (1) 1118 1119 1120 /* 3: Remapping Hardware Static Affinity Structure */ 1121 1122 typedef struct acpi_dmar_rhsa 1123 { 1124 ACPI_DMAR_HEADER Header; 1125 UINT32 Reserved; 1126 UINT64 BaseAddress; 1127 UINT32 ProximityDomain; 1128 1129 } ACPI_DMAR_RHSA; 1130 1131 1132 /* 4: ACPI Namespace Device Declaration Structure */ 1133 1134 typedef struct acpi_dmar_andd 1135 { 1136 ACPI_DMAR_HEADER Header; 1137 UINT8 Reserved[3]; 1138 UINT8 DeviceNumber; 1139 union { 1140 char __pad; 1141 ACPI_FLEX_ARRAY(char, DeviceName); 1142 }; 1143 1144 } ACPI_DMAR_ANDD; 1145 1146 1147 /* 5: SoC Integrated Address Translation Cache (SATC) */ 1148 1149 typedef struct acpi_dmar_satc 1150 { 1151 ACPI_DMAR_HEADER Header; 1152 UINT8 Flags; 1153 UINT8 Reserved; 1154 UINT16 Segment; 1155 1156 } ACPI_DMAR_SATC; 1157 1158 1159 /* 6: SoC Integrated Device Property Reporting Structure */ 1160 1161 typedef struct acpi_dmar_sidp 1162 { 1163 ACPI_DMAR_HEADER Header; 1164 UINT16 Reserved; 1165 UINT16 Segment; 1166 1167 } ACPI_DMAR_SIDP; 1168 1169 1170 /******************************************************************************* 1171 * 1172 * DRTM - Dynamic Root of Trust for Measurement table 1173 * Conforms to "TCG D-RTM Architecture" June 17 2013, Version 1.0.0 1174 * Table version 1 1175 * 1176 ******************************************************************************/ 1177 1178 typedef struct acpi_table_drtm 1179 { 1180 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1181 UINT64 EntryBaseAddress; 1182 UINT64 EntryLength; 1183 UINT32 EntryAddress32; 1184 UINT64 EntryAddress64; 1185 UINT64 ExitAddress; 1186 UINT64 LogAreaAddress; 1187 UINT32 LogAreaLength; 1188 UINT64 ArchDependentAddress; 1189 UINT32 Flags; 1190 1191 } ACPI_TABLE_DRTM; 1192 1193 /* Flag Definitions for above */ 1194 1195 #define ACPI_DRTM_ACCESS_ALLOWED (1) 1196 #define ACPI_DRTM_ENABLE_GAP_CODE (1<<1) 1197 #define ACPI_DRTM_INCOMPLETE_MEASUREMENTS (1<<2) 1198 #define ACPI_DRTM_AUTHORITY_ORDER (1<<3) 1199 1200 1201 /* 1) Validated Tables List (64-bit addresses) */ 1202 1203 typedef struct acpi_drtm_vtable_list 1204 { 1205 UINT32 ValidatedTableCount; 1206 UINT64 ValidatedTables[]; 1207 1208 } ACPI_DRTM_VTABLE_LIST; 1209 1210 /* 2) Resources List (of Resource Descriptors) */ 1211 1212 /* Resource Descriptor */ 1213 1214 typedef struct acpi_drtm_resource 1215 { 1216 UINT8 Size[7]; 1217 UINT8 Type; 1218 UINT64 Address; 1219 1220 } ACPI_DRTM_RESOURCE; 1221 1222 typedef struct acpi_drtm_resource_list 1223 { 1224 UINT32 ResourceCount; 1225 ACPI_DRTM_RESOURCE Resources[]; 1226 1227 } ACPI_DRTM_RESOURCE_LIST; 1228 1229 /* 3) Platform-specific Identifiers List */ 1230 1231 typedef struct acpi_drtm_dps_id 1232 { 1233 UINT32 DpsIdLength; 1234 UINT8 DpsId[16]; 1235 1236 } ACPI_DRTM_DPS_ID; 1237 1238 1239 /******************************************************************************* 1240 * 1241 * DTPR - DMA TXT Protection Ranges Table 1242 * Version 1 1243 * 1244 * Conforms to "Intel Trusted Execution Technology (Intel TXT) DMA Protection 1245 * Ranges", 1246 * Revision 0.73, August 2021 1247 * 1248 ******************************************************************************/ 1249 1250 typedef struct acpi_table_dtpr { 1251 ACPI_TABLE_HEADER header; 1252 UINT32 Flags; /* 36 */ 1253 UINT32 InsCnt; 1254 1255 } ACPI_TABLE_DTPR; 1256 1257 typedef struct acpi_tpr_array { 1258 UINT64 Base; 1259 1260 } ACPI_TPR_ARRAY; 1261 1262 typedef struct acpi_tpr_instance { 1263 UINT32 Flags; 1264 UINT32 TprCnt; 1265 1266 } ACPI_TPR_INSTANCE; 1267 1268 typedef struct acpi_tpr_aux_sr { 1269 UINT32 SrlCnt; 1270 1271 } ACPI_TPR_AUX_SR; 1272 1273 1274 /* 1275 * TPRn_BASE (ACPI_TPRN_BASE_REG) 1276 * 1277 * Specifies the start address of TPRn region. TPR region address and size must 1278 * be with 1MB resolution. These bits are compared with the result of the 1279 * TPRn_LIMIT[63:20], which is applied to the incoming address, to 1280 * determine if an access fall within the TPRn defined region. 1281 * 1282 * Minimal TPRn_Base resolution is 1MB. Applied to the incoming address, to 1283 * determine if an access fall within the TPRn defined region. Width is 1284 * determined by a bus width which can be obtained via CPUID 1285 * function 0x80000008. 1286 */ 1287 1288 typedef UINT64 ACPI_TPRN_BASE_REG; 1289 1290 1291 /* TPRn_BASE Register Bit Masks */ 1292 1293 /* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */ 1294 #define ACPI_TPRN_BASE_RW_SHIFT 3 1295 1296 1297 #define ACPI_TPRN_BASE_RW_MASK ((UINT64) 1 << ACPI_TPRN_BASE_RW_SHIFT) 1298 1299 1300 /* 1301 * Bit 4 - Enable: 0 TPRn address range enabled; 1302 * 1 TPRn address range disabled. 1303 */ 1304 #define ACPI_TPRN_BASE_ENABLE_SHIFT 4 1305 1306 1307 #define ACPI_TPRN_BASE_ENABLE_MASK ((UINT64) 1 << ACPI_TPRN_BASE_ENABLE_SHIFT) 1308 1309 1310 /* Bits 63:20 - TprBaseRw */ 1311 #define ACPI_TPRN_BASE_ADDR_SHIFT 20 1312 1313 1314 #define ACPI_TPRN_BASE_ADDR_MASK ((UINT64) 0xFFFFFFFFFFF << \ 1315 ACPI_TPRN_BASE_ADDR_SHIFT) 1316 1317 1318 /* TPRn_BASE Register Bit Handlers*/ 1319 1320 /* 1321 * GET_TPRN_BASE_RW: 1322 * 1323 * Read RW bit from TPRn Base Register - bit 3. 1324 * 1325 * Input: 1326 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1327 * 1328 * Output: 1329 * 1330 * Returns RW bit value (UINT64). 1331 */ 1332 #define GET_TPRN_BASE_RW(reg) (((UINT64) reg & ACPI_TPRN_BASE_RW_MASK) >> \ 1333 ACPI_TPRN_BASE_RW_SHIFT) 1334 1335 1336 /* 1337 * GET_TPRN_BASE_ENABLE: 1338 * 1339 * Read Enable bit from TPRn Base Register - bit 4. 1340 * 1341 * Input: 1342 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1343 * 1344 * Output: 1345 * 1346 * Returns Enable bit value (UINT64). 1347 */ 1348 #define GET_TPRN_BASE_ENABLE(reg) (((UINT64) reg & ACPI_TPRN_BASE_ENABLE_MASK) \ 1349 >> ACPI_TPRN_BASE_ENABLE_SHIFT) 1350 1351 1352 /* 1353 * GET_TPRN_BASE_ADDR: 1354 * 1355 * Read TPRn Base Register address from bits 63:20. 1356 * 1357 * Input: 1358 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1359 * 1360 * Output: 1361 * 1362 * Returns TPRn Base Register address (UINT64). 1363 */ 1364 #define GET_TPRN_BASE_ADDR(reg) (((UINT64) reg & ACPI_TPRN_BASE_ADDR_MASK) \ 1365 >> ACPI_TPRN_BASE_ADDR_SHIFT) 1366 1367 1368 /* 1369 * SET_TPRN_BASE_RW: 1370 * 1371 * Set RW bit in TPRn Base Register - bit 3. 1372 * 1373 * Input: 1374 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1375 * - val (represents RW value to be set (UINT64)) 1376 */ 1377 #define SET_TPRN_BASE_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1378 ACPI_TPRN_BASE_RW_SHIFT, \ 1379 ACPI_TPRN_BASE_RW_MASK, val); 1380 1381 1382 /* 1383 * SET_TPRN_BASE_ENABLE: 1384 * 1385 * Set Enable bit in TPRn Base Register - bit 4. 1386 * 1387 * Input: 1388 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1389 * - val (represents Enable value to be set (UINT64)) 1390 */ 1391 #define SET_TPRN_BASE_ENABLE(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1392 ACPI_TPRN_BASE_ENABLE_SHIFT, \ 1393 ACPI_TPRN_BASE_ENABLE_MASK, val); 1394 1395 1396 /* 1397 * SET_TPRN_BASE_ADDR: 1398 * 1399 * Set TPRn Base Register address - bits 63:20 1400 * 1401 * Input 1402 * - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG)) 1403 * - val (represents address value to be set (UINT64)) 1404 */ 1405 #define SET_TPRN_BASE_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1406 ACPI_TPRN_BASE_ADDR_SHIFT, \ 1407 ACPI_TPRN_BASE_ADDR_MASK, val); 1408 1409 1410 /* 1411 * TPRn_LIMIT 1412 * 1413 * This register defines an isolated region of memory that can be enabled 1414 * to prohibit certain system agents from accessing memory. When an agent 1415 * sends a request upstream, whether snooped or not, a TPR prevents that 1416 * transaction from changing the state of memory. 1417 * 1418 * Minimal TPRn_Limit resolution is 1MB. Width is determined by a bus width. 1419 */ 1420 1421 typedef UINT64 ACPI_TPRN_LIMIT_REG; 1422 1423 1424 /* TPRn_LIMIT Register Bit Masks */ 1425 1426 1427 /* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */ 1428 #define ACPI_TPRN_LIMIT_RW_SHIFT 3 1429 1430 1431 #define ACPI_TPRN_LIMIT_RW_MASK ((UINT64) 1 << ACPI_TPRN_LIMIT_RW_SHIFT) 1432 1433 1434 /* Bits 63:20 - TprLimitRw */ 1435 #define ACPI_TPRN_LIMIT_ADDR_SHIFT 20 1436 1437 1438 #define ACPI_TPRN_LIMIT_ADDR_MASK ((UINT64) 0xFFFFFFFFFFF << \ 1439 ACPI_TPRN_LIMIT_ADDR_SHIFT) 1440 1441 1442 /* TPRn_LIMIT Register Bit Handlers*/ 1443 1444 /* 1445 * GET_TPRN_LIMIT_RW: 1446 * 1447 * Read RW bit from TPRn Limit Register - bit 3. 1448 * 1449 * Input: 1450 * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) 1451 * 1452 * Output: 1453 * 1454 * Returns RW bit value (UINT64). 1455 */ 1456 #define GET_TPRN_LIMIT_RW(reg) (((UINT64) reg & ACPI_TPRN_LIMIT_RW_MASK) \ 1457 >> ACPI_TPRN_LIMIT_RW_SHIFT) 1458 1459 1460 /* 1461 * GET_TPRN_LIMIT_ADDR: 1462 * 1463 * Read TPRn Limit Register address from bits 63:20. 1464 * 1465 * Input: 1466 * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) 1467 * 1468 * Output: 1469 * 1470 * Returns TPRn Limit Register address (UINT64). 1471 */ 1472 #define GET_TPRN_LIMIT_ADDR(reg) (((UINT64) reg & ACPI_TPRN_LIMIT_ADDR_MASK) \ 1473 >> ACPI_TPRN_LIMIT_ADDR_SHIFT) 1474 1475 1476 /* 1477 * SET_TPRN_LIMIT_RW: 1478 * 1479 * Set RW bit in TPRn Limit Register - bit 3. 1480 * 1481 * Input: 1482 * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) 1483 * - val (represents RW value to be set (UINT64)) 1484 */ 1485 #define SET_TPRN_LIMIT_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1486 ACPI_TPRN_LIMIT_RW_SHIFT, \ 1487 ACPI_TPRN_LIMIT_RW_MASK, val); 1488 1489 1490 /* 1491 * SET_TPRN_LIMIT_ADDR: 1492 * 1493 * Set TPRn Limit Register address - bits 63:20. 1494 * 1495 * Input: 1496 * - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG)) 1497 * - val (represents address value to be set (UINT64)) 1498 */ 1499 #define SET_TPRN_LIMIT_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \ 1500 ACPI_TPRN_LIMIT_ADDR_SHIFT, \ 1501 ACPI_TPRN_LIMIT_ADDR_MASK, val); 1502 1503 1504 /* 1505 * SERIALIZE_REQUEST 1506 * 1507 * This register is used to request serialization of non-coherent DMA 1508 * transactions. OS shall issue it before changing of TPR settings 1509 * (base / size). 1510 */ 1511 1512 typedef struct acpi_tpr_serialize_request { 1513 UINT64 SrRegister; 1514 /* 1515 * BIT 1 - Status of serialization request (RO) 1516 * 0 == register idle, 1 == serialization in progress 1517 * BIT 2 - Control field to initiate serialization (RW) 1518 * 0 == normal, 1 == initialize serialization 1519 * (self-clear to allow multiple serialization requests) 1520 */ 1521 } ACPI_TPR_SERIALIZE_REQUEST; 1522 1523 1524 /******************************************************************************* 1525 * 1526 * ECDT - Embedded Controller Boot Resources Table 1527 * Version 1 1528 * 1529 ******************************************************************************/ 1530 1531 typedef struct acpi_table_ecdt 1532 { 1533 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1534 ACPI_GENERIC_ADDRESS Control; /* Address of EC command/status register */ 1535 ACPI_GENERIC_ADDRESS Data; /* Address of EC data register */ 1536 UINT32 Uid; /* Unique ID - must be same as the EC _UID method */ 1537 UINT8 Gpe; /* The GPE for the EC */ 1538 UINT8 Id[]; /* Full namepath of the EC in the ACPI namespace */ 1539 1540 } ACPI_TABLE_ECDT; 1541 1542 1543 /******************************************************************************* 1544 * 1545 * EINJ - Error Injection Table (ACPI 4.0) 1546 * Version 1 1547 * 1548 ******************************************************************************/ 1549 1550 typedef struct acpi_table_einj 1551 { 1552 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1553 UINT32 HeaderLength; 1554 UINT8 Flags; 1555 UINT8 Reserved[3]; 1556 UINT32 Entries; 1557 1558 } ACPI_TABLE_EINJ; 1559 1560 1561 /* EINJ Injection Instruction Entries (actions) */ 1562 1563 typedef struct acpi_einj_entry 1564 { 1565 ACPI_WHEA_HEADER WheaHeader; /* Common header for WHEA tables */ 1566 1567 } ACPI_EINJ_ENTRY; 1568 1569 /* Masks for Flags field above */ 1570 1571 #define ACPI_EINJ_PRESERVE (1) 1572 1573 /* Values for Action field above */ 1574 1575 enum AcpiEinjActions 1576 { 1577 ACPI_EINJ_BEGIN_OPERATION = 0x0, 1578 ACPI_EINJ_GET_TRIGGER_TABLE = 0x1, 1579 ACPI_EINJ_SET_ERROR_TYPE = 0x2, 1580 ACPI_EINJ_GET_ERROR_TYPE = 0x3, 1581 ACPI_EINJ_END_OPERATION = 0x4, 1582 ACPI_EINJ_EXECUTE_OPERATION = 0x5, 1583 ACPI_EINJ_CHECK_BUSY_STATUS = 0x6, 1584 ACPI_EINJ_GET_COMMAND_STATUS = 0x7, 1585 ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS = 0x8, 1586 ACPI_EINJ_GET_EXECUTE_TIMINGS = 0x9, 1587 ACPI_EINJV2_GET_ERROR_TYPE = 0x11, 1588 ACPI_EINJ_ACTION_RESERVED = 0x12, /* 0x12 and greater are reserved */ 1589 ACPI_EINJ_TRIGGER_ERROR = 0xFF /* Except for this value */ 1590 }; 1591 1592 /* Values for Instruction field above */ 1593 1594 enum AcpiEinjInstructions 1595 { 1596 ACPI_EINJ_READ_REGISTER = 0, 1597 ACPI_EINJ_READ_REGISTER_VALUE = 1, 1598 ACPI_EINJ_WRITE_REGISTER = 2, 1599 ACPI_EINJ_WRITE_REGISTER_VALUE = 3, 1600 ACPI_EINJ_NOOP = 4, 1601 ACPI_EINJ_FLUSH_CACHELINE = 5, 1602 ACPI_EINJ_INSTRUCTION_RESERVED = 6 /* 6 and greater are reserved */ 1603 }; 1604 1605 typedef struct acpi_einj_error_type_with_addr 1606 { 1607 UINT32 ErrorType; 1608 UINT32 VendorStructOffset; 1609 UINT32 Flags; 1610 UINT32 ApicId; 1611 UINT64 Address; 1612 UINT64 Range; 1613 UINT32 PcieId; 1614 1615 } ACPI_EINJ_ERROR_TYPE_WITH_ADDR; 1616 1617 typedef struct acpi_einj_vendor 1618 { 1619 UINT32 Length; 1620 UINT32 PcieId; 1621 UINT16 VendorId; 1622 UINT16 DeviceId; 1623 UINT8 RevisionId; 1624 UINT8 Reserved[3]; 1625 1626 } ACPI_EINJ_VENDOR; 1627 1628 1629 /* EINJ Trigger Error Action Table */ 1630 1631 typedef struct acpi_einj_trigger 1632 { 1633 UINT32 HeaderSize; 1634 UINT32 Revision; 1635 UINT32 TableSize; 1636 UINT32 EntryCount; 1637 1638 } ACPI_EINJ_TRIGGER; 1639 1640 /* Command status return values */ 1641 1642 enum AcpiEinjCommandStatus 1643 { 1644 ACPI_EINJ_SUCCESS = 0, 1645 ACPI_EINJ_FAILURE = 1, 1646 ACPI_EINJ_INVALID_ACCESS = 2, 1647 ACPI_EINJ_STATUS_RESERVED = 3 /* 3 and greater are reserved */ 1648 }; 1649 1650 1651 /* Error types returned from ACPI_EINJ_GET_ERROR_TYPE (bitfield) */ 1652 1653 #define ACPI_EINJ_PROCESSOR_CORRECTABLE (1) 1654 #define ACPI_EINJ_PROCESSOR_UNCORRECTABLE (1<<1) 1655 #define ACPI_EINJ_PROCESSOR_FATAL (1<<2) 1656 #define ACPI_EINJ_MEMORY_CORRECTABLE (1<<3) 1657 #define ACPI_EINJ_MEMORY_UNCORRECTABLE (1<<4) 1658 #define ACPI_EINJ_MEMORY_FATAL (1<<5) 1659 #define ACPI_EINJ_PCIX_CORRECTABLE (1<<6) 1660 #define ACPI_EINJ_PCIX_UNCORRECTABLE (1<<7) 1661 #define ACPI_EINJ_PCIX_FATAL (1<<8) 1662 #define ACPI_EINJ_PLATFORM_CORRECTABLE (1<<9) 1663 #define ACPI_EINJ_PLATFORM_UNCORRECTABLE (1<<10) 1664 #define ACPI_EINJ_PLATFORM_FATAL (1<<11) 1665 #define ACPI_EINJ_CXL_CACHE_CORRECTABLE (1<<12) 1666 #define ACPI_EINJ_CXL_CACHE_UNCORRECTABLE (1<<13) 1667 #define ACPI_EINJ_CXL_CACHE_FATAL (1<<14) 1668 #define ACPI_EINJ_CXL_MEM_CORRECTABLE (1<<15) 1669 #define ACPI_EINJ_CXL_MEM_UNCORRECTABLE (1<<16) 1670 #define ACPI_EINJ_CXL_MEM_FATAL (1<<17) 1671 #define ACPI_EINJ_VENDOR_DEFINED (1<<31) 1672 1673 1674 /******************************************************************************* 1675 * 1676 * ERST - Error Record Serialization Table (ACPI 4.0) 1677 * Version 1 1678 * 1679 ******************************************************************************/ 1680 1681 typedef struct acpi_table_erst 1682 { 1683 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1684 UINT32 HeaderLength; 1685 UINT32 Reserved; 1686 UINT32 Entries; 1687 1688 } ACPI_TABLE_ERST; 1689 1690 1691 /* ERST Serialization Entries (actions) */ 1692 1693 typedef struct acpi_erst_entry 1694 { 1695 ACPI_WHEA_HEADER WheaHeader; /* Common header for WHEA tables */ 1696 1697 } ACPI_ERST_ENTRY; 1698 1699 /* Masks for Flags field above */ 1700 1701 #define ACPI_ERST_PRESERVE (1) 1702 1703 /* Values for Action field above */ 1704 1705 enum AcpiErstActions 1706 { 1707 ACPI_ERST_BEGIN_WRITE = 0, 1708 ACPI_ERST_BEGIN_READ = 1, 1709 ACPI_ERST_BEGIN_CLEAR = 2, 1710 ACPI_ERST_END = 3, 1711 ACPI_ERST_SET_RECORD_OFFSET = 4, 1712 ACPI_ERST_EXECUTE_OPERATION = 5, 1713 ACPI_ERST_CHECK_BUSY_STATUS = 6, 1714 ACPI_ERST_GET_COMMAND_STATUS = 7, 1715 ACPI_ERST_GET_RECORD_ID = 8, 1716 ACPI_ERST_SET_RECORD_ID = 9, 1717 ACPI_ERST_GET_RECORD_COUNT = 10, 1718 ACPI_ERST_BEGIN_DUMMY_WRIITE = 11, 1719 ACPI_ERST_NOT_USED = 12, 1720 ACPI_ERST_GET_ERROR_RANGE = 13, 1721 ACPI_ERST_GET_ERROR_LENGTH = 14, 1722 ACPI_ERST_GET_ERROR_ATTRIBUTES = 15, 1723 ACPI_ERST_EXECUTE_TIMINGS = 16, 1724 ACPI_ERST_ACTION_RESERVED = 17 /* 17 and greater are reserved */ 1725 }; 1726 1727 /* Values for Instruction field above */ 1728 1729 enum AcpiErstInstructions 1730 { 1731 ACPI_ERST_READ_REGISTER = 0, 1732 ACPI_ERST_READ_REGISTER_VALUE = 1, 1733 ACPI_ERST_WRITE_REGISTER = 2, 1734 ACPI_ERST_WRITE_REGISTER_VALUE = 3, 1735 ACPI_ERST_NOOP = 4, 1736 ACPI_ERST_LOAD_VAR1 = 5, 1737 ACPI_ERST_LOAD_VAR2 = 6, 1738 ACPI_ERST_STORE_VAR1 = 7, 1739 ACPI_ERST_ADD = 8, 1740 ACPI_ERST_SUBTRACT = 9, 1741 ACPI_ERST_ADD_VALUE = 10, 1742 ACPI_ERST_SUBTRACT_VALUE = 11, 1743 ACPI_ERST_STALL = 12, 1744 ACPI_ERST_STALL_WHILE_TRUE = 13, 1745 ACPI_ERST_SKIP_NEXT_IF_TRUE = 14, 1746 ACPI_ERST_GOTO = 15, 1747 ACPI_ERST_SET_SRC_ADDRESS_BASE = 16, 1748 ACPI_ERST_SET_DST_ADDRESS_BASE = 17, 1749 ACPI_ERST_MOVE_DATA = 18, 1750 ACPI_ERST_INSTRUCTION_RESERVED = 19 /* 19 and greater are reserved */ 1751 }; 1752 1753 /* Command status return values */ 1754 1755 enum AcpiErstCommandStatus 1756 { 1757 ACPI_ERST_SUCCESS = 0, 1758 ACPI_ERST_NO_SPACE = 1, 1759 ACPI_ERST_NOT_AVAILABLE = 2, 1760 ACPI_ERST_FAILURE = 3, 1761 ACPI_ERST_RECORD_EMPTY = 4, 1762 ACPI_ERST_NOT_FOUND = 5, 1763 ACPI_ERST_STATUS_RESERVED = 6 /* 6 and greater are reserved */ 1764 }; 1765 1766 1767 /* Error Record Serialization Information */ 1768 1769 typedef struct acpi_erst_info 1770 { 1771 UINT16 Signature; /* Should be "ER" */ 1772 UINT8 Data[48]; 1773 1774 } ACPI_ERST_INFO; 1775 1776 1777 /******************************************************************************* 1778 * 1779 * FPDT - Firmware Performance Data Table (ACPI 5.0) 1780 * Version 1 1781 * 1782 ******************************************************************************/ 1783 1784 typedef struct acpi_table_fpdt 1785 { 1786 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1787 1788 } ACPI_TABLE_FPDT; 1789 1790 1791 /* FPDT subtable header (Performance Record Structure) */ 1792 1793 typedef struct acpi_fpdt_header 1794 { 1795 UINT16 Type; 1796 UINT8 Length; 1797 UINT8 Revision; 1798 1799 } ACPI_FPDT_HEADER; 1800 1801 /* Values for Type field above */ 1802 1803 enum AcpiFpdtType 1804 { 1805 ACPI_FPDT_TYPE_BOOT = 0, 1806 ACPI_FPDT_TYPE_S3PERF = 1 1807 }; 1808 1809 1810 /* 1811 * FPDT subtables 1812 */ 1813 1814 /* 0: Firmware Basic Boot Performance Record */ 1815 1816 typedef struct acpi_fpdt_boot_pointer 1817 { 1818 ACPI_FPDT_HEADER Header; 1819 UINT8 Reserved[4]; 1820 UINT64 Address; 1821 1822 } ACPI_FPDT_BOOT_POINTER; 1823 1824 1825 /* 1: S3 Performance Table Pointer Record */ 1826 1827 typedef struct acpi_fpdt_s3pt_pointer 1828 { 1829 ACPI_FPDT_HEADER Header; 1830 UINT8 Reserved[4]; 1831 UINT64 Address; 1832 1833 } ACPI_FPDT_S3PT_POINTER; 1834 1835 1836 /* 1837 * S3PT - S3 Performance Table. This table is pointed to by the 1838 * S3 Pointer Record above. 1839 */ 1840 typedef struct acpi_table_s3pt 1841 { 1842 UINT8 Signature[4]; /* "S3PT" */ 1843 UINT32 Length; 1844 1845 } ACPI_TABLE_S3PT; 1846 1847 1848 /* 1849 * S3PT Subtables (Not part of the actual FPDT) 1850 */ 1851 1852 /* Values for Type field in S3PT header */ 1853 1854 enum AcpiS3ptType 1855 { 1856 ACPI_S3PT_TYPE_RESUME = 0, 1857 ACPI_S3PT_TYPE_SUSPEND = 1, 1858 ACPI_FPDT_BOOT_PERFORMANCE = 2 1859 }; 1860 1861 typedef struct acpi_s3pt_resume 1862 { 1863 ACPI_FPDT_HEADER Header; 1864 UINT32 ResumeCount; 1865 UINT64 FullResume; 1866 UINT64 AverageResume; 1867 1868 } ACPI_S3PT_RESUME; 1869 1870 typedef struct acpi_s3pt_suspend 1871 { 1872 ACPI_FPDT_HEADER Header; 1873 UINT64 SuspendStart; 1874 UINT64 SuspendEnd; 1875 1876 } ACPI_S3PT_SUSPEND; 1877 1878 1879 /* 1880 * FPDT Boot Performance Record (Not part of the actual FPDT) 1881 */ 1882 typedef struct acpi_fpdt_boot 1883 { 1884 ACPI_FPDT_HEADER Header; 1885 UINT8 Reserved[4]; 1886 UINT64 ResetEnd; 1887 UINT64 LoadStart; 1888 UINT64 StartupStart; 1889 UINT64 ExitServicesEntry; 1890 UINT64 ExitServicesExit; 1891 1892 } ACPI_FPDT_BOOT; 1893 1894 1895 /******************************************************************************* 1896 * 1897 * GTDT - Generic Timer Description Table (ACPI 5.1) 1898 * Version 2 1899 * 1900 ******************************************************************************/ 1901 1902 typedef struct acpi_table_gtdt 1903 { 1904 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 1905 UINT64 CounterBlockAddresss; 1906 UINT32 Reserved; 1907 UINT32 SecureEl1Interrupt; 1908 UINT32 SecureEl1Flags; 1909 UINT32 NonSecureEl1Interrupt; 1910 UINT32 NonSecureEl1Flags; 1911 UINT32 VirtualTimerInterrupt; 1912 UINT32 VirtualTimerFlags; 1913 UINT32 NonSecureEl2Interrupt; 1914 UINT32 NonSecureEl2Flags; 1915 UINT64 CounterReadBlockAddress; 1916 UINT32 PlatformTimerCount; 1917 UINT32 PlatformTimerOffset; 1918 1919 } ACPI_TABLE_GTDT; 1920 1921 /* Flag Definitions: Timer Block Physical Timers and Virtual timers */ 1922 1923 #define ACPI_GTDT_INTERRUPT_MODE (1) 1924 #define ACPI_GTDT_INTERRUPT_POLARITY (1<<1) 1925 #define ACPI_GTDT_ALWAYS_ON (1<<2) 1926 1927 typedef struct acpi_gtdt_el2 1928 { 1929 UINT32 VirtualEL2TimerGsiv; 1930 UINT32 VirtualEL2TimerFlags; 1931 } ACPI_GTDT_EL2; 1932 1933 1934 /* Common GTDT subtable header */ 1935 1936 typedef struct acpi_gtdt_header 1937 { 1938 UINT8 Type; 1939 UINT16 Length; 1940 1941 } ACPI_GTDT_HEADER; 1942 1943 /* Values for GTDT subtable type above */ 1944 1945 enum AcpiGtdtType 1946 { 1947 ACPI_GTDT_TYPE_TIMER_BLOCK = 0, 1948 ACPI_GTDT_TYPE_WATCHDOG = 1, 1949 ACPI_GTDT_TYPE_RESERVED = 2 /* 2 and greater are reserved */ 1950 }; 1951 1952 1953 /* GTDT Subtables, correspond to Type in acpi_gtdt_header */ 1954 1955 /* 0: Generic Timer Block */ 1956 1957 typedef struct acpi_gtdt_timer_block 1958 { 1959 ACPI_GTDT_HEADER Header; 1960 UINT8 Reserved; 1961 UINT64 BlockAddress; 1962 UINT32 TimerCount; 1963 UINT32 TimerOffset; 1964 1965 } ACPI_GTDT_TIMER_BLOCK; 1966 1967 /* Timer Sub-Structure, one per timer */ 1968 1969 typedef struct acpi_gtdt_timer_entry 1970 { 1971 UINT8 FrameNumber; 1972 UINT8 Reserved[3]; 1973 UINT64 BaseAddress; 1974 UINT64 El0BaseAddress; 1975 UINT32 TimerInterrupt; 1976 UINT32 TimerFlags; 1977 UINT32 VirtualTimerInterrupt; 1978 UINT32 VirtualTimerFlags; 1979 UINT32 CommonFlags; 1980 1981 } ACPI_GTDT_TIMER_ENTRY; 1982 1983 /* Flag Definitions: TimerFlags and VirtualTimerFlags above */ 1984 1985 #define ACPI_GTDT_GT_IRQ_MODE (1) 1986 #define ACPI_GTDT_GT_IRQ_POLARITY (1<<1) 1987 1988 /* Flag Definitions: CommonFlags above */ 1989 1990 #define ACPI_GTDT_GT_IS_SECURE_TIMER (1) 1991 #define ACPI_GTDT_GT_ALWAYS_ON (1<<1) 1992 1993 1994 /* 1: SBSA Generic Watchdog Structure */ 1995 1996 typedef struct acpi_gtdt_watchdog 1997 { 1998 ACPI_GTDT_HEADER Header; 1999 UINT8 Reserved; 2000 UINT64 RefreshFrameAddress; 2001 UINT64 ControlFrameAddress; 2002 UINT32 TimerInterrupt; 2003 UINT32 TimerFlags; 2004 2005 } ACPI_GTDT_WATCHDOG; 2006 2007 /* Flag Definitions: TimerFlags above */ 2008 2009 #define ACPI_GTDT_WATCHDOG_IRQ_MODE (1) 2010 #define ACPI_GTDT_WATCHDOG_IRQ_POLARITY (1<<1) 2011 #define ACPI_GTDT_WATCHDOG_SECURE (1<<2) 2012 2013 2014 /******************************************************************************* 2015 * 2016 * HEST - Hardware Error Source Table (ACPI 4.0) 2017 * Version 1 2018 * 2019 ******************************************************************************/ 2020 2021 typedef struct acpi_table_hest 2022 { 2023 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 2024 UINT32 ErrorSourceCount; 2025 2026 } ACPI_TABLE_HEST; 2027 2028 2029 /* HEST subtable header */ 2030 2031 typedef struct acpi_hest_header 2032 { 2033 UINT16 Type; 2034 UINT16 SourceId; 2035 2036 } ACPI_HEST_HEADER; 2037 2038 2039 /* Values for Type field above for subtables */ 2040 2041 enum AcpiHestTypes 2042 { 2043 ACPI_HEST_TYPE_IA32_CHECK = 0, 2044 ACPI_HEST_TYPE_IA32_CORRECTED_CHECK = 1, 2045 ACPI_HEST_TYPE_IA32_NMI = 2, 2046 ACPI_HEST_TYPE_NOT_USED3 = 3, 2047 ACPI_HEST_TYPE_NOT_USED4 = 4, 2048 ACPI_HEST_TYPE_NOT_USED5 = 5, 2049 ACPI_HEST_TYPE_AER_ROOT_PORT = 6, 2050 ACPI_HEST_TYPE_AER_ENDPOINT = 7, 2051 ACPI_HEST_TYPE_AER_BRIDGE = 8, 2052 ACPI_HEST_TYPE_GENERIC_ERROR = 9, 2053 ACPI_HEST_TYPE_GENERIC_ERROR_V2 = 10, 2054 ACPI_HEST_TYPE_IA32_DEFERRED_CHECK = 11, 2055 ACPI_HEST_TYPE_RESERVED = 12 /* 12 and greater are reserved */ 2056 }; 2057 2058 2059 /* 2060 * HEST substructures contained in subtables 2061 */ 2062 2063 /* 2064 * IA32 Error Bank(s) - Follows the ACPI_HEST_IA_MACHINE_CHECK and 2065 * ACPI_HEST_IA_CORRECTED structures. 2066 */ 2067 typedef struct acpi_hest_ia_error_bank 2068 { 2069 UINT8 BankNumber; 2070 UINT8 ClearStatusOnInit; 2071 UINT8 StatusFormat; 2072 UINT8 Reserved; 2073 UINT32 ControlRegister; 2074 UINT64 ControlData; 2075 UINT32 StatusRegister; 2076 UINT32 AddressRegister; 2077 UINT32 MiscRegister; 2078 2079 } ACPI_HEST_IA_ERROR_BANK; 2080 2081 2082 /* Common HEST sub-structure for PCI/AER structures below (6,7,8) */ 2083 2084 typedef struct acpi_hest_aer_common 2085 { 2086 UINT16 Reserved1; 2087 UINT8 Flags; 2088 UINT8 Enabled; 2089 UINT32 RecordsToPreallocate; 2090 UINT32 MaxSectionsPerRecord; 2091 UINT32 Bus; /* Bus and Segment numbers */ 2092 UINT16 Device; 2093 UINT16 Function; 2094 UINT16 DeviceControl; 2095 UINT16 Reserved2; 2096 UINT32 UncorrectableMask; 2097 UINT32 UncorrectableSeverity; 2098 UINT32 CorrectableMask; 2099 UINT32 AdvancedCapabilities; 2100 2101 } ACPI_HEST_AER_COMMON; 2102 2103 /* Masks for HEST Flags fields */ 2104 2105 #define ACPI_HEST_FIRMWARE_FIRST (1) 2106 #define ACPI_HEST_GLOBAL (1<<1) 2107 #define ACPI_HEST_GHES_ASSIST (1<<2) 2108 2109 /* 2110 * Macros to access the bus/segment numbers in Bus field above: 2111 * Bus number is encoded in bits 7:0 2112 * Segment number is encoded in bits 23:8 2113 */ 2114 #define ACPI_HEST_BUS(Bus) ((Bus) & 0xFF) 2115 #define ACPI_HEST_SEGMENT(Bus) (((Bus) >> 8) & 0xFFFF) 2116 2117 2118 /* Hardware Error Notification */ 2119 2120 typedef struct acpi_hest_notify 2121 { 2122 UINT8 Type; 2123 UINT8 Length; 2124 UINT16 ConfigWriteEnable; 2125 UINT32 PollInterval; 2126 UINT32 Vector; 2127 UINT32 PollingThresholdValue; 2128 UINT32 PollingThresholdWindow; 2129 UINT32 ErrorThresholdValue; 2130 UINT32 ErrorThresholdWindow; 2131 2132 } ACPI_HEST_NOTIFY; 2133 2134 /* Values for Notify Type field above */ 2135 2136 enum AcpiHestNotifyTypes 2137 { 2138 ACPI_HEST_NOTIFY_POLLED = 0, 2139 ACPI_HEST_NOTIFY_EXTERNAL = 1, 2140 ACPI_HEST_NOTIFY_LOCAL = 2, 2141 ACPI_HEST_NOTIFY_SCI = 3, 2142 ACPI_HEST_NOTIFY_NMI = 4, 2143 ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */ 2144 ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */ 2145 ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */ 2146 ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */ 2147 ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */ 2148 ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */ 2149 ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED = 11, /* ACPI 6.2 */ 2150 ACPI_HEST_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */ 2151 }; 2152 2153 /* Values for ConfigWriteEnable bitfield above */ 2154 2155 #define ACPI_HEST_TYPE (1) 2156 #define ACPI_HEST_POLL_INTERVAL (1<<1) 2157 #define ACPI_HEST_POLL_THRESHOLD_VALUE (1<<2) 2158 #define ACPI_HEST_POLL_THRESHOLD_WINDOW (1<<3) 2159 #define ACPI_HEST_ERR_THRESHOLD_VALUE (1<<4) 2160 #define ACPI_HEST_ERR_THRESHOLD_WINDOW (1<<5) 2161 2162 2163 /* 2164 * HEST subtables 2165 */ 2166 2167 /* 0: IA32 Machine Check Exception */ 2168 2169 typedef struct acpi_hest_ia_machine_check 2170 { 2171 ACPI_HEST_HEADER Header; 2172 UINT16 Reserved1; 2173 UINT8 Flags; /* See flags ACPI_HEST_GLOBAL, etc. above */ 2174 UINT8 Enabled; 2175 UINT32 RecordsToPreallocate; 2176 UINT32 MaxSectionsPerRecord; 2177 UINT64 GlobalCapabilityData; 2178 UINT64 GlobalControlData; 2179 UINT8 NumHardwareBanks; 2180 UINT8 Reserved3[7]; 2181 2182 } ACPI_HEST_IA_MACHINE_CHECK; 2183 2184 2185 /* 1: IA32 Corrected Machine Check */ 2186 2187 typedef struct acpi_hest_ia_corrected 2188 { 2189 ACPI_HEST_HEADER Header; 2190 UINT16 Reserved1; 2191 UINT8 Flags; /* See flags ACPI_HEST_GLOBAL, etc. above */ 2192 UINT8 Enabled; 2193 UINT32 RecordsToPreallocate; 2194 UINT32 MaxSectionsPerRecord; 2195 ACPI_HEST_NOTIFY Notify; 2196 UINT8 NumHardwareBanks; 2197 UINT8 Reserved2[3]; 2198 2199 } ACPI_HEST_IA_CORRECTED; 2200 2201 2202 /* 2: IA32 Non-Maskable Interrupt */ 2203 2204 typedef struct acpi_hest_ia_nmi 2205 { 2206 ACPI_HEST_HEADER Header; 2207 UINT32 Reserved; 2208 UINT32 RecordsToPreallocate; 2209 UINT32 MaxSectionsPerRecord; 2210 UINT32 MaxRawDataLength; 2211 2212 } ACPI_HEST_IA_NMI; 2213 2214 2215 /* 3,4,5: Not used */ 2216 2217 /* 6: PCI Express Root Port AER */ 2218 2219 typedef struct acpi_hest_aer_root 2220 { 2221 ACPI_HEST_HEADER Header; 2222 ACPI_HEST_AER_COMMON Aer; 2223 UINT32 RootErrorCommand; 2224 2225 } ACPI_HEST_AER_ROOT; 2226 2227 2228 /* 7: PCI Express AER (AER Endpoint) */ 2229 2230 typedef struct acpi_hest_aer 2231 { 2232 ACPI_HEST_HEADER Header; 2233 ACPI_HEST_AER_COMMON Aer; 2234 2235 } ACPI_HEST_AER; 2236 2237 2238 /* 8: PCI Express/PCI-X Bridge AER */ 2239 2240 typedef struct acpi_hest_aer_bridge 2241 { 2242 ACPI_HEST_HEADER Header; 2243 ACPI_HEST_AER_COMMON Aer; 2244 UINT32 UncorrectableMask2; 2245 UINT32 UncorrectableSeverity2; 2246 UINT32 AdvancedCapabilities2; 2247 2248 } ACPI_HEST_AER_BRIDGE; 2249 2250 2251 /* 9: Generic Hardware Error Source */ 2252 2253 typedef struct acpi_hest_generic 2254 { 2255 ACPI_HEST_HEADER Header; 2256 UINT16 RelatedSourceId; 2257 UINT8 Reserved; 2258 UINT8 Enabled; 2259 UINT32 RecordsToPreallocate; 2260 UINT32 MaxSectionsPerRecord; 2261 UINT32 MaxRawDataLength; 2262 ACPI_GENERIC_ADDRESS ErrorStatusAddress; 2263 ACPI_HEST_NOTIFY Notify; 2264 UINT32 ErrorBlockLength; 2265 2266 } ACPI_HEST_GENERIC; 2267 2268 2269 /* 10: Generic Hardware Error Source, version 2 */ 2270 2271 typedef struct acpi_hest_generic_v2 2272 { 2273 ACPI_HEST_HEADER Header; 2274 UINT16 RelatedSourceId; 2275 UINT8 Reserved; 2276 UINT8 Enabled; 2277 UINT32 RecordsToPreallocate; 2278 UINT32 MaxSectionsPerRecord; 2279 UINT32 MaxRawDataLength; 2280 ACPI_GENERIC_ADDRESS ErrorStatusAddress; 2281 ACPI_HEST_NOTIFY Notify; 2282 UINT32 ErrorBlockLength; 2283 ACPI_GENERIC_ADDRESS ReadAckRegister; 2284 UINT64 ReadAckPreserve; 2285 UINT64 ReadAckWrite; 2286 2287 } ACPI_HEST_GENERIC_V2; 2288 2289 2290 /* Generic Error Status block */ 2291 2292 typedef struct acpi_hest_generic_status 2293 { 2294 UINT32 BlockStatus; 2295 UINT32 RawDataOffset; 2296 UINT32 RawDataLength; 2297 UINT32 DataLength; 2298 UINT32 ErrorSeverity; 2299 2300 } ACPI_HEST_GENERIC_STATUS; 2301 2302 /* Values for BlockStatus flags above */ 2303 2304 #define ACPI_HEST_UNCORRECTABLE (1) 2305 #define ACPI_HEST_CORRECTABLE (1<<1) 2306 #define ACPI_HEST_MULTIPLE_UNCORRECTABLE (1<<2) 2307 #define ACPI_HEST_MULTIPLE_CORRECTABLE (1<<3) 2308 #define ACPI_HEST_ERROR_ENTRY_COUNT (0xFF<<4) /* 8 bits, error count */ 2309 2310 2311 /* Generic Error Data entry */ 2312 2313 typedef struct acpi_hest_generic_data 2314 { 2315 UINT8 SectionType[16]; 2316 UINT32 ErrorSeverity; 2317 UINT16 Revision; 2318 UINT8 ValidationBits; 2319 UINT8 Flags; 2320 UINT32 ErrorDataLength; 2321 UINT8 FruId[16]; 2322 UINT8 FruText[20]; 2323 2324 } ACPI_HEST_GENERIC_DATA; 2325 2326 /* Extension for revision 0x0300 */ 2327 2328 typedef struct acpi_hest_generic_data_v300 2329 { 2330 UINT8 SectionType[16]; 2331 UINT32 ErrorSeverity; 2332 UINT16 Revision; 2333 UINT8 ValidationBits; 2334 UINT8 Flags; 2335 UINT32 ErrorDataLength; 2336 UINT8 FruId[16]; 2337 UINT8 FruText[20]; 2338 UINT64 TimeStamp; 2339 2340 } ACPI_HEST_GENERIC_DATA_V300; 2341 2342 /* Values for ErrorSeverity above */ 2343 2344 #define ACPI_HEST_GEN_ERROR_RECOVERABLE 0 2345 #define ACPI_HEST_GEN_ERROR_FATAL 1 2346 #define ACPI_HEST_GEN_ERROR_CORRECTED 2 2347 #define ACPI_HEST_GEN_ERROR_NONE 3 2348 2349 /* Flags for ValidationBits above */ 2350 2351 #define ACPI_HEST_GEN_VALID_FRU_ID (1) 2352 #define ACPI_HEST_GEN_VALID_FRU_STRING (1<<1) 2353 #define ACPI_HEST_GEN_VALID_TIMESTAMP (1<<2) 2354 2355 2356 /* 11: IA32 Deferred Machine Check Exception (ACPI 6.2) */ 2357 2358 typedef struct acpi_hest_ia_deferred_check 2359 { 2360 ACPI_HEST_HEADER Header; 2361 UINT16 Reserved1; 2362 UINT8 Flags; /* See flags ACPI_HEST_GLOBAL, etc. above */ 2363 UINT8 Enabled; 2364 UINT32 RecordsToPreallocate; 2365 UINT32 MaxSectionsPerRecord; 2366 ACPI_HEST_NOTIFY Notify; 2367 UINT8 NumHardwareBanks; 2368 UINT8 Reserved2[3]; 2369 2370 } ACPI_HEST_IA_DEFERRED_CHECK; 2371 2372 2373 /******************************************************************************* 2374 * 2375 * HMAT - Heterogeneous Memory Attributes Table (ACPI 6.3) 2376 * 2377 ******************************************************************************/ 2378 2379 typedef struct acpi_table_hmat 2380 { 2381 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 2382 UINT32 Reserved; 2383 2384 } ACPI_TABLE_HMAT; 2385 2386 2387 /* Values for HMAT structure types */ 2388 2389 enum AcpiHmatType 2390 { 2391 ACPI_HMAT_TYPE_ADDRESS_RANGE = 0, /* Memory subsystem address range */ 2392 ACPI_HMAT_TYPE_LOCALITY = 1, /* System locality latency and bandwidth information */ 2393 ACPI_HMAT_TYPE_CACHE = 2, /* Memory side cache information */ 2394 ACPI_HMAT_TYPE_RESERVED = 3 /* 3 and greater are reserved */ 2395 }; 2396 2397 typedef struct acpi_hmat_structure 2398 { 2399 UINT16 Type; 2400 UINT16 Reserved; 2401 UINT32 Length; 2402 2403 } ACPI_HMAT_STRUCTURE; 2404 2405 2406 /* 2407 * HMAT Structures, correspond to Type in ACPI_HMAT_STRUCTURE 2408 */ 2409 2410 /* 0: Memory proximity domain attributes */ 2411 2412 typedef struct acpi_hmat_proximity_domain 2413 { 2414 ACPI_HMAT_STRUCTURE Header; 2415 UINT16 Flags; 2416 UINT16 Reserved1; 2417 UINT32 InitiatorPD; /* Attached Initiator proximity domain */ 2418 UINT32 MemoryPD; /* Memory proximity domain */ 2419 UINT32 Reserved2; 2420 UINT64 Reserved3; 2421 UINT64 Reserved4; 2422 2423 } ACPI_HMAT_PROXIMITY_DOMAIN; 2424 2425 /* Masks for Flags field above */ 2426 2427 #define ACPI_HMAT_INITIATOR_PD_VALID (1) /* 1: InitiatorPD field is valid */ 2428 2429 2430 /* 1: System locality latency and bandwidth information */ 2431 2432 typedef struct acpi_hmat_locality 2433 { 2434 ACPI_HMAT_STRUCTURE Header; 2435 UINT8 Flags; 2436 UINT8 DataType; 2437 UINT8 MinTransferSize; 2438 UINT8 Reserved1; 2439 UINT32 NumberOfInitiatorPDs; 2440 UINT32 NumberOfTargetPDs; 2441 UINT32 Reserved2; 2442 UINT64 EntryBaseUnit; 2443 2444 } ACPI_HMAT_LOCALITY; 2445 2446 /* Masks for Flags field above */ 2447 2448 #define ACPI_HMAT_MEMORY_HIERARCHY (0x0F) /* Bits 0-3 */ 2449 2450 /* Values for Memory Hierarchy flags */ 2451 2452 #define ACPI_HMAT_MEMORY 0 2453 #define ACPI_HMAT_1ST_LEVEL_CACHE 1 2454 #define ACPI_HMAT_2ND_LEVEL_CACHE 2 2455 #define ACPI_HMAT_3RD_LEVEL_CACHE 3 2456 #define ACPI_HMAT_MINIMUM_XFER_SIZE 0x10 /* Bit 4: ACPI 6.4 */ 2457 #define ACPI_HMAT_NON_SEQUENTIAL_XFERS 0x20 /* Bit 5: ACPI 6.4 */ 2458 2459 2460 /* Values for DataType field above */ 2461 2462 #define ACPI_HMAT_ACCESS_LATENCY 0 2463 #define ACPI_HMAT_READ_LATENCY 1 2464 #define ACPI_HMAT_WRITE_LATENCY 2 2465 #define ACPI_HMAT_ACCESS_BANDWIDTH 3 2466 #define ACPI_HMAT_READ_BANDWIDTH 4 2467 #define ACPI_HMAT_WRITE_BANDWIDTH 5 2468 2469 2470 /* 2: Memory side cache information */ 2471 2472 typedef struct acpi_hmat_cache 2473 { 2474 ACPI_HMAT_STRUCTURE Header; 2475 UINT32 MemoryPD; 2476 UINT32 Reserved1; 2477 UINT64 CacheSize; 2478 UINT32 CacheAttributes; 2479 UINT16 AddressMode; 2480 UINT16 NumberOfSMBIOSHandles; 2481 2482 } ACPI_HMAT_CACHE; 2483 2484 /* Masks for CacheAttributes field above */ 2485 2486 #define ACPI_HMAT_TOTAL_CACHE_LEVEL (0x0000000F) 2487 #define ACPI_HMAT_CACHE_LEVEL (0x000000F0) 2488 #define ACPI_HMAT_CACHE_ASSOCIATIVITY (0x00000F00) 2489 #define ACPI_HMAT_WRITE_POLICY (0x0000F000) 2490 #define ACPI_HMAT_CACHE_LINE_SIZE (0xFFFF0000) 2491 2492 #define ACPI_HMAT_CACHE_MODE_UNKNOWN (0) 2493 #define ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR (1) 2494 2495 /* Values for cache associativity flag */ 2496 2497 #define ACPI_HMAT_CA_NONE (0) 2498 #define ACPI_HMAT_CA_DIRECT_MAPPED (1) 2499 #define ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING (2) 2500 2501 /* Values for write policy flag */ 2502 2503 #define ACPI_HMAT_CP_NONE (0) 2504 #define ACPI_HMAT_CP_WB (1) 2505 #define ACPI_HMAT_CP_WT (2) 2506 2507 2508 /******************************************************************************* 2509 * 2510 * HPET - High Precision Event Timer table 2511 * Version 1 2512 * 2513 * Conforms to "IA-PC HPET (High Precision Event Timers) Specification", 2514 * Version 1.0a, October 2004 2515 * 2516 ******************************************************************************/ 2517 2518 typedef struct acpi_table_hpet 2519 { 2520 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 2521 UINT32 Id; /* Hardware ID of event timer block */ 2522 ACPI_GENERIC_ADDRESS Address; /* Address of event timer block */ 2523 UINT8 Sequence; /* HPET sequence number */ 2524 UINT16 MinimumTick; /* Main counter min tick, periodic mode */ 2525 UINT8 Flags; 2526 2527 } ACPI_TABLE_HPET; 2528 2529 /* Masks for Flags field above */ 2530 2531 #define ACPI_HPET_PAGE_PROTECT_MASK (3) 2532 2533 /* Values for Page Protect flags */ 2534 2535 enum AcpiHpetPageProtect 2536 { 2537 ACPI_HPET_NO_PAGE_PROTECT = 0, 2538 ACPI_HPET_PAGE_PROTECT4 = 1, 2539 ACPI_HPET_PAGE_PROTECT64 = 2 2540 }; 2541 2542 2543 /******************************************************************************* 2544 * 2545 * IBFT - Boot Firmware Table 2546 * Version 1 2547 * 2548 * Conforms to "iSCSI Boot Firmware Table (iBFT) as Defined in ACPI 3.0b 2549 * Specification", Version 1.01, March 1, 2007 2550 * 2551 * Note: It appears that this table is not intended to appear in the RSDT/XSDT. 2552 * Therefore, it is not currently supported by the disassembler. 2553 * 2554 ******************************************************************************/ 2555 2556 typedef struct acpi_table_ibft 2557 { 2558 ACPI_TABLE_HEADER Header; /* Common ACPI table header */ 2559 UINT8 Reserved[12]; 2560 2561 } ACPI_TABLE_IBFT; 2562 2563 2564 /* IBFT common subtable header */ 2565 2566 typedef struct acpi_ibft_header 2567 { 2568 UINT8 Type; 2569 UINT8 Version; 2570 UINT16 Length; 2571 UINT8 Index; 2572 UINT8 Flags; 2573 2574 } ACPI_IBFT_HEADER; 2575 2576 /* Values for Type field above */ 2577 2578 enum AcpiIbftType 2579 { 2580 ACPI_IBFT_TYPE_NOT_USED = 0, 2581 ACPI_IBFT_TYPE_CONTROL = 1, 2582 ACPI_IBFT_TYPE_INITIATOR = 2, 2583 ACPI_IBFT_TYPE_NIC = 3, 2584 ACPI_IBFT_TYPE_TARGET = 4, 2585 ACPI_IBFT_TYPE_EXTENSIONS = 5, 2586 ACPI_IBFT_TYPE_RESERVED = 6 /* 6 and greater are reserved */ 2587 }; 2588 2589 2590 /* IBFT subtables */ 2591 2592 typedef struct acpi_ibft_control 2593 { 2594 ACPI_IBFT_HEADER Header; 2595 UINT16 Extensions; 2596 UINT16 InitiatorOffset; 2597 UINT16 Nic0Offset; 2598 UINT16 Target0Offset; 2599 UINT16 Nic1Offset; 2600 UINT16 Target1Offset; 2601 2602 } ACPI_IBFT_CONTROL; 2603 2604 typedef struct acpi_ibft_initiator 2605 { 2606 ACPI_IBFT_HEADER Header; 2607 UINT8 SnsServer[16]; 2608 UINT8 SlpServer[16]; 2609 UINT8 PrimaryServer[16]; 2610 UINT8 SecondaryServer[16]; 2611 UINT16 NameLength; 2612 UINT16 NameOffset; 2613 2614 } ACPI_IBFT_INITIATOR; 2615 2616 typedef struct acpi_ibft_nic 2617 { 2618 ACPI_IBFT_HEADER Header; 2619 UINT8 IpAddress[16]; 2620 UINT8 SubnetMaskPrefix; 2621 UINT8 Origin; 2622 UINT8 Gateway[16]; 2623 UINT8 PrimaryDns[16]; 2624 UINT8 SecondaryDns[16]; 2625 UINT8 Dhcp[16]; 2626 UINT16 Vlan; 2627 UINT8 MacAddress[6]; 2628 UINT16 PciAddress; 2629 UINT16 NameLength; 2630 UINT16 NameOffset; 2631 2632 } ACPI_IBFT_NIC; 2633 2634 typedef struct acpi_ibft_target 2635 { 2636 ACPI_IBFT_HEADER Header; 2637 UINT8 TargetIpAddress[16]; 2638 UINT16 TargetIpSocket; 2639 UINT8 TargetBootLun[8]; 2640 UINT8 ChapType; 2641 UINT8 NicAssociation; 2642 UINT16 TargetNameLength; 2643 UINT16 TargetNameOffset; 2644 UINT16 ChapNameLength; 2645 UINT16 ChapNameOffset; 2646 UINT16 ChapSecretLength; 2647 UINT16 ChapSecretOffset; 2648 UINT16 ReverseChapNameLength; 2649 UINT16 ReverseChapNameOffset; 2650 UINT16 ReverseChapSecretLength; 2651 UINT16 ReverseChapSecretOffset; 2652 2653 } ACPI_IBFT_TARGET; 2654 2655 /* Reset to default packing */ 2656 2657 #pragma pack() 2658 2659 #endif /* __ACTBL1_H__ */ 2660
Indexes created Sat Jun 13 00:24:39 UTC 2026