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    Searched defs:ExtType (Results 1 - 17 of 17) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBitTracker.h 61 struct ExtType {
64 ExtType() = default;
65 ExtType(char t, uint16_t w) : Type(t), Width(w) {}
71 using RegExtMap = DenseMap<unsigned, ExtType>;
HexagonISelDAGToDAG.cpp 76 ISD::LoadExtType ExtType = LD->getExtensionType();
77 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
131 auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl)
133 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) {
138 if (ExtType == ISD::SEXTLOAD)
149 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 259 ISD::LoadExtType ExtType = LD->getExtensionType();
260 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
LegalizeIntegerTypes.cpp 685 ISD::LoadExtType ExtType =
688 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
718 ISD::LoadExtType ExtType = N->getExtensionType();
719 if (ExtType == ISD::NON_EXTLOAD)
720 ExtType = ISD::EXTLOAD;
728 ExtType);
3183 ISD::LoadExtType ExtType = N->getExtensionType();
3193 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), MemVT,
3199 if (ExtType == ISD::SEXTLOAD) {
3206 } else if (ExtType == ISD::ZEXTLOAD)
    [all...]
LegalizeVectorTypes.cpp 1689 ISD::LoadExtType ExtType = LD->getExtensionType();
1708 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1715 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, MPI,
1742 ISD::LoadExtType ExtType = MLD->getExtensionType();
1773 MMO, MLD->getAddressingMode(), ExtType,
1798 HiMemVT, MMO, MLD->getAddressingMode(), ExtType,
1827 ISD::LoadExtType ExtType = MGT->getExtensionType();
1863 MMO, MGT->getIndexType(), ExtType);
1867 MMO, MGT->getIndexType(), ExtType);
2519 ISD::LoadExtType ExtType = MGT->getExtensionType()
    [all...]
DAGCombiner.cpp 680 bool isLegalNarrowLdSt(LSBaseSDNode *LDSTN, ISD::LoadExtType ExtType,
795 ISD::NodeType ExtType);
1213 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1216 return DAG.getExtLoad(ExtType, DL, PVT,
1450 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1452 SDValue NewLD = DAG.getExtLoad(ExtType, DL, PVT,
5229 ISD::LoadExtType ExtType, EVT &MemVT,
5282 !TLI.isLoadExtLegal(ExtType, Load->getValueType(0), MemVT))
5300 if (!TLI.shouldReduceLoadWidth(Load, ExtType, MemVT))
10397 ISD::NodeType ExtType) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64InstPrinter.cpp 1008 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val);
1014 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
1018 ExtType == AArch64_AM::UXTX) ||
1020 ExtType == AArch64_AM::UXTW) ) {
1026 O << ", " << AArch64_AM::getShiftExtendName(ExtType);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 1299 ISD::LoadExtType ExtType = Load->getExtensionType();
1336 if (ExtType == ISD::SEXTLOAD) { // ... ones.
1355 ISD::LoadExtType ExtType = LoadNode->getExtensionType();
1358 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) {
SIISelLowering.cpp 1735 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1745 ExtType = ISD::SEXTLOAD;
1748 ExtType = ISD::ZEXTLOAD;
1751 ExtType = ISD::EXTLOAD;
1756 ExtType, SL, VA.getLocVT(), Chain, FIN,
7933 ISD::LoadExtType ExtType, SDValue Op,
7938 switch (ExtType) {
8025 ISD::LoadExtType ExtType = Load->getExtensionType();
8028 if (ExtType == ISD::NON_EXTLOAD && MemVT.getSizeInBits() < 32) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 89 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::InvalidShiftExtend;
104 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; }
105 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; }
215 unsigned RHSReg, AArch64_AM::ShiftExtendType ExtType,
1406 AArch64_AM::ShiftExtendType ExtType,
1444 .addImm(getArithExtendImm(ExtType, ShiftImm));
AArch64ISelDAGToDAG.cpp 1282 ISD::LoadExtType ExtType = LD->getExtensionType();
1287 if (ExtType == ISD::NON_EXTLOAD)
1289 else if (ExtType == ISD::SEXTLOAD)
1299 if (ExtType == ISD::SEXTLOAD) {
1312 if (ExtType == ISD::SEXTLOAD) {
AArch64ISelLowering.cpp 4954 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4970 ExtType = ISD::SEXTLOAD;
4973 ExtType = ISD::ZEXTLOAD;
4976 ExtType = ISD::EXTLOAD;
4981 ExtType, DL, VA.getLocVT(), Chain, FIN,
13500 unsigned ExtType = LHS.getOpcode();
13509 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
13515 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
14956 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
14957 ExtType = ISD::NON_EXTLOAD
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 4488 unsigned ExtType =
4491 if (ExtType == ISD::SEXTLOAD) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 2679 ISD::LoadExtType ExtType = LD->getExtensionType();
2689 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2708 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2709 (ExtType == ISD::EXTLOAD))
2712 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CodeGenPrepare.cpp 254 enum ExtType {
264 using TypeIsSExt = PointerIntPair<Type *, 2, ExtType>;
4024 ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension;
4047 ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension;
6995 Instruction::CastOps ExtType = Instruction::ZExt;
6998 ExtType = Instruction::SExt;
7000 auto *ExtInst = CastInst::Create(ExtType, Cond, NewType);
7006 APInt WideConst = (ExtType == Instruction::ZExt) ?
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 2145 unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
2147 widenScalarSrc(MI, WideTy, 0, ExtType);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 7040 ISD::LoadExtType ExtType;
7047 ExtType = ISD::NON_EXTLOAD;
7051 ExtType, DL, LocVT, Chain, FIN,

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