| /src/external/apache2/llvm/dist/llvm/tools/llvm-extract/ |
| llvm-extract.cpp | 1 //===- llvm-extract.cpp - LLVM function extraction utility ----------------===//
37 cl::OptionCategory ExtractCat("llvm-extract Options");
62 Recursive("recursive", cl::desc("Recursively extract all called functions"),
65 // ExtractFuncs - The functions to extract from the module.
67 ExtractFuncs("func", cl::desc("Specify function to extract"),
72 // extract from the module.
75 cl::desc("Specify function(s) to extract using a "
80 // ExtractBlocks - The blocks to extract from the module.
84 "Specify <function, basic block1[;basic block2...]> pairs to extract.\n"
89 " --bb=f:bb1;bb2 will extract one function with both bb1 and bb2;\n
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| /src/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
| BinaryStreamArray.h | 14 /// an Extractor type that can extract a record from a given offset and
163 : IterRef(Array.Stream.drop_front(Offset)), Extract(E),
168 auto EC = Extract(IterRef, ThisLen, ThisValue);
177 explicit VarStreamArrayIterator(const Extractor &E) : Extract(E) {}
217 auto EC = Extract(IterRef, ThisLen, ThisValue);
247 Extractor Extract;
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| InterleavedAccessPass.cpp | 174 /// <0, 2, 4, 6> (mask of index 0 to extract even elements)
175 /// <1, 3, 5, 7> (mask of index 1 to extract odd elements)
298 // them to later check if they can be modified to extract from one of the
308 auto *Extract = dyn_cast<ExtractElementInst>(User);
309 if (Extract && isa<ConstantInt>(Extract->getIndexOperand())) {
310 Extracts.push_back(Extract);
439 for (auto *Extract : Extracts) {
441 auto *IndexOperand = cast<ConstantInt>(Extract->getIndexOperand());
448 // If the shufflevector instruction doesn't dominate the extract, w
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| SVEIntrinsicOpts.cpp | 411 auto *Extract = Builder.CreateExtractElement(OpVal, SplatValue);
413 Builder.CreateVectorSplat(VTy->getElementCount(), Extract);
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| AArch64TargetTransformInfo.cpp | 248 // This is a base cost of 1 for the vadd, plus 3 extract shifts if we
401 // The intrinsic is extracting lane 0 so use an extract instead.
403 auto *Extract = ExtractElementInst::Create(Vec, ConstantInt::get(IdxTy, 0));
404 Extract->insertBefore(&II);
405 Extract->takeName(&II);
406 return IC.replaceInstUsesWith(II, Extract);
465 // The intrinsic is extracting a fixed lane so use an extract instead.
467 auto *Extract = ExtractElementInst::Create(Vec, ConstantInt::get(IdxTy, Idx));
468 Extract->insertBefore(&II);
469 Extract->takeName(&II)
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| AArch64ISelDAGToDAG.cpp | 624 // high lane extract.
732 /// GPR64 (either via SEXT_INREG or AND). Extract the appropriate low bits if
1917 // Check whether we really have several bits extract here.
1947 // Check for AND + SRL doing several bits extract.
2025 /// extract of a subvector.
2030 SDValue Extract = N->getOperand(0);
2032 EVT NarrowVT = Extract.getValueType();
2038 Extract = peekThroughBitcasts(Extract);
2039 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR
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| AArch64ISelLowering.cpp | 3605 // so that the shift + and get folded into a bitfield extract.
4343 // It first extend the promoted v4i16 to v8i16, truncate to v8i8, and extract
8165 /// generating an "extract from vector registers" instruction.
8296 dbgs() << "Reshuffle failed: result vector too small to extract\n");
8950 // Try to eliminate a bitcasted extract subvector before a DUPLANE.
8957 // The extract index must align in the destination type. That may not
8959 SDValue Extract = BitCast.getOperand(0);
8960 unsigned ExtIdx = Extract.getConstantOperandVal(1);
8961 unsigned SrcEltBitWidth = Extract.getScalarValueSizeInBits();
8967 // Update the lane value by offsetting with the scaled extract index
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64PostLegalizerLowering.cpp | 426 /// %extract = G_EXTRACT_VECTOR_ELT %left, 0
427 /// %ins = G_INSERT_VECTOR_ELT %left, %extract, 1
466 auto Extract = Builder.buildExtractVectorElement(ScalarTy, SrcVec, SrcCst);
468 Builder.buildInsertVectorElement(Dst, DstVec, Extract, DstCst);
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| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| SeparateConstOffsetFromGEP.cpp | 85 // (1) It can always extract constants in the indices of structure type.
234 /// the constant offset), or nullptr if we cannot extract a constant offset.
239 static Value *Extract(Value *Idx, GetElementPtrInst *GEP,
244 /// failed). The meaning of the arguments are the same as Extract.
282 /// For example, to extract the 5 from sext(a + (b + 5)), we first distribute
747 // we can extract 5 as the constant offset.
768 Value *ConstantOffsetExtractor::Extract(Value *Idx, GetElementPtrInst *GEP,
821 // Tries to extract a constant offset from this GEP index.
1015 ConstantOffsetExtractor::Extract(OldIdx, GEP, UserChainTail, DT);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| MachineIRBuilder.cpp | 536 auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
537 Dst.addDefToMIB(*getMRI(), Extract);
538 Src.addSrcToMIB(Extract);
539 Extract.addImm(Index);
540 return Extract;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelDAGToDAG.cpp | 1117 // extract which doesn't naturally align to a vector register. These must
1136 SDValue Extract = CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, V);
1137 ReplaceNode(Node, Extract.getNode());
|
| RISCVISelLowering.cpp | 493 // Custom-lower insert/extract operations to simplify patterns.
560 // Custom-lower insert/extract operations to simplify patterns.
1111 // Attempt to decompose a subvector insert/extract between VecVT and
1113 // can perform the subvector insert/extract with the given element index, as
1417 // type, bitcast to the equivalent (known-legal) mask type, and extract
1966 // is the same as the result type, and extract the first element.
3195 // extract the first element: (extractelt (slidedown vec, idx), 0). For integer
3208 // FIXME: For now we just promote to an i8 vector and extract from that,
3779 // Extract a subvector equal to the nearest full vector register type. This
3830 // elements to safely divide by 8: v8i1 = extract nxv1i1 is valid
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| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| LoadStoreVectorizer.cpp | 18 // that immediately following our new vector load we'll need to extract out the
1106 Value *Extract = Builder.CreateExtractElement(Store->getValueOperand(),
1108 if (Extract->getType() != StoreTy->getScalarType())
1109 Extract = Builder.CreateBitCast(Extract, StoreTy->getScalarType());
1112 Builder.CreateInsertElement(Vec, Extract, Builder.getInt32(NewIdx));
1119 Value *Extract = Store->getValueOperand();
1120 if (Extract->getType() != StoreTy->getScalarType())
1121 Extract =
1122 Builder.CreateBitOrPointerCast(Extract, StoreTy->getScalarType())
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| VPlan.cpp | 244 auto *Extract = Builder.CreateExtractElement(VecPart, Lane);
245 // set(Def, Extract, Instance);
246 return Extract;
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-ar/ |
| llvm-ar.cpp | 104 x - extract [files] from the archive
199 Extract, ///< Extract files back to file system
224 // match for extract/delete operations when there are multiple matches. This is
242 // Extract the member filename from the command line for the [relpos] argument
251 // Extract the parameter from the command line for the [count] argument
338 Operation = Extract;
437 if (Operation != Extract && Operation != Delete)
440 if (OriginalDates && Operation != Extract)
588 case Extract
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| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 234 // Sign extends are legal only when extending a vector extract
1636 // is a vector extract of an i8 or i16 lane. SIMD does not depend on sign
1646 const SDValue &Extract = Op.getOperand(0);
1647 MVT VecT = Extract.getOperand(0).getSimpleValueType();
1658 const SDNode *Index = Extract.getOperand(1).getNode();
1668 ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(),
1669 DAG.getBitcast(ExtractedVecT, Extract.getOperand(0)), NewIndex);
2087 auto Extract = N->getOperand(0);
2088 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR)
2090 auto Source = Extract.getOperand(0)
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| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 1160 Instruction *LowBitsToSkip, *Extract;
1163 m_Instruction(Extract))),
1179 // Extraction should extract high NBits bits, with shift amount calculated as:
1180 // low bits to skip = shift bitwidth - high bits to extract
1241 Extract->getName() + ".sext");
1242 NewAShr->copyIRFlags(Extract); // Preserve `exact`-ness.
|
| InstCombineCompares.cpp | 2889 Value *Extract = Builder.CreateExtractElement(Vec, Elem);
2891 return new ICmpInst(Pred, Extract, NewC);
5540 // extract(uadd.with.overflow(A, B), 0) ult A
5541 // -> extract(uadd.with.overflow(A, B), 1)
5556 // extract(uadd.with.overflow(A, B), 0) < A
5557 // extract(uadd.with.overflow(A, 1), 0) == 0
5558 // extract(uadd.with.overflow(A, -1), 0) != -1
5562 // A > extract(uadd.with.overflow(A, B), 0)
|
| /src/external/bsd/openldap/dist/contrib/slapd-modules/comp_match/ |
| componentlib.h | 401 ExtractFcn Extract;
431 void InstallAnyByComponentInt (int anyId, ComponentInt intId, unsigned int size, EncodeFcn encode, gser_decoder_func* G_decode, ber_tag_decoder_func B_decode, ExtractFcn extract, MatchFcn match, FreeFcn free, PrintFcn print);
433 void InstallAnyByComponentOid (int anyId, AsnOid *oid, unsigned int size, EncodeFcn encode, gser_decoder_func* G_decode, ber_tag_decoder_func* B_decode, ExtractFcn extract, MatchFcn match, FreeFcn free, PrintFcn print);
|
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| AutoUpgrade.cpp | 1114 // i8 and we need to extract down to the right number of elements.
1120 Mask, Mask, makeArrayRef(Indices, NumElts), "extract");
1839 Value *Extract =
1842 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, Align(1));
2005 // First extract half of each vector. This gives better codegen than
2428 // Extract a subvector of the first NumDstElts lanes and sign/zero extend.
3583 // Extract the second result and store it.
3833 // Extract the second result and store it.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 316 // Figure out if this is really an extract of the high 16-bits of a dword.
2017 // Extract the base and offset if possible.
2410 SDValue Extract
2413 ReplaceUses(SDValue(N, 0), Extract);
|
| SIISelLowering.cpp | 1694 SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt);
1696 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract);
7450 auto Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, NewOp,
7452 NewOp = DAG.getMergeValues({ Extract, SDValue(NewOp.getNode(), 1) }, DL);
10211 // multiple small extract_vector_elements with a single 32-bit extract.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 1834 // extract and a scaled index. Returns false if the simplification is
2383 // Try to fold the mask and shift into an extract and scale.
3565 SDValue Extract = CurDAG->getNode(X86ISD::BZHI, DL, NVT, X, NBits);
3566 ReplaceNode(Node, Extract.getNode());
3567 SelectCode(Extract.getNode());
3624 SDValue Extract = CurDAG->getNode(X86ISD::BEXTR, DL, XVT, X, Control);
3628 insertDAGNode(*CurDAG, SDValue(Node, 0), Extract);
3629 Extract = CurDAG->getNode(ISD::TRUNCATE, DL, NVT, Extract);
3632 ReplaceNode(Node, Extract.getNode())
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 648 enum class StoreSource { Unknown, Constant, Extract, Load };
656 return StoreSource::Extract;
5139 // Reduce bit extract of low half of an integer to the narrower type.
5166 // AArch64 which match a few 64-bit bit insert / bit extract patterns
6544 /// Helper function for visitOR to extract the needed side of a rotate idiom
6601 // Set Opcode and IsMulOrDiv if the extract opcode matches the needed shift
6635 // Compute the shift amount we need to extract to complete the rotate.
6645 // Now try extract the needed shift from the ExtractFrom op and see if the
6648 // Op to extract from is a mul or udiv by a constant.
6660 // Op to extract from is a shift by a constant
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| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 3047 // Extract the first half and return it in two registers.
3066 // Extract the 2nd half and fall through to handle it as an f64 value.
6100 // so that the shift + and get folded into a bitfield extract.
6370 // Extract the lower 32 bits of the shift amount if it's not an i32
6840 // possible. Lower it to a splat followed by an extract.
6873 // It's a float: cast and extract a vector element.
6890 // It's a float: cast and extract a vector element.
7281 // items are valid enough and extract some info from them (they are checked
7334 // or <1,3,5,7>. Check the first two items are valid enough and extract some
8097 // extract the first 8 bytes into the top double word and the last 8 byte
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