1 /* $NetBSD: mb86960reg.h,v 1.10 2005/12/11 12:21:27 christos Exp $ */ 2 3 /* 4 * All Rights Reserved, Copyright (C) Fujitsu Limited 1995 5 * 6 * This software may be used, modified, copied, distributed, and sold, in 7 * both source and binary form provided that the above copyright, these 8 * terms and the following disclaimer are retained. The name of the author 9 * and/or the contributor may not be used to endorse or promote products 10 * derived from this software without specific prior written permission. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 */ 24 25 /* 26 * Registers of Fujitsu MB86960A/MB86965A Ethernet controller. 27 * Written and contributed by M.S. <seki (at) sysrap.cs.fujitsu.co.jp> 28 */ 29 30 /* 31 * Notes on register naming: 32 * 33 * Fujitsu documents for MB86960A/MB86965A use no mnemonic names 34 * for their registers. They defined only three names for 32 35 * registers and appended numbers to distinguish registers of 36 * same name. Surprisingly, the numbers represent I/O address 37 * offsets of the registers from the base addresses, and their 38 * names correspond to the "bank" the registers are allocated. 39 * All this means that, for example, to say "read DLCR8" has no more 40 * than to say "read a register at offset 8 on bank DLCR." 41 * 42 * The following definitions may look silly, but that's what Fujitsu 43 * did, and it is necessary to know these names to read Fujitsu 44 * documents.. 45 */ 46 47 /* Data Link Control Registers, on invaliant port addresses. */ 48 #define FE_DLCR0 0 49 #define FE_DLCR1 1 50 #define FE_DLCR2 2 51 #define FE_DLCR3 3 52 #define FE_DLCR4 4 53 #define FE_DLCR5 5 54 #define FE_DLCR6 6 55 #define FE_DLCR7 7 56 57 /* More DLCRs, on register bank #0. */ 58 #define FE_DLCR8 8 59 #define FE_DLCR9 9 60 #define FE_DLCR10 10 61 #define FE_DLCR11 11 62 #define FE_DLCR12 12 63 #define FE_DLCR13 13 64 #define FE_DLCR14 14 65 #define FE_DLCR15 15 66 67 /* Multicast Address Registers. On register bank #1. */ 68 #define FE_MAR8 8 69 #define FE_MAR9 9 70 #define FE_MAR10 10 71 #define FE_MAR11 11 72 #define FE_MAR12 12 73 #define FE_MAR13 13 74 #define FE_MAR14 14 75 #define FE_MAR15 15 76 77 /* Buffer Memory Port Registers. On register bank #2. */ 78 #define FE_BMPR8 8 79 #define FE_BMPR9 9 80 #define FE_BMPR10 10 81 #define FE_BMPR11 11 82 #define FE_BMPR12 12 83 #define FE_BMPR13 13 84 #define FE_BMPR14 14 85 #define FE_BMPR15 15 86 87 /* More BMPRs, only on MB86965A, accessible only when JLI mode. */ 88 #define FE_BMPR16 16 89 #define FE_BMPR17 17 90 #define FE_BMPR18 18 91 #define FE_BMPR19 19 92 93 #define FE_RESET 31 94 95 /* 96 * Definitions of registers. 97 * I don't have Fujitsu documents of MB86960A/MB86965A, so I don't 98 * know the official names for the flags and fields. The following 99 * names are assigned by me (the author of this file), since I cannot 100 * memorize hexadecimal constants for all of these functions. 101 * Comments? FIXME. 102 */ 103 104 /* DLCR0 -- transmitter status */ 105 #define FE_D0_BUSERR 0x01 /* Bus write error */ 106 #define FE_D0_COLL16 0x02 /* Collision limit (16) encountered */ 107 #define FE_D0_COLLID 0x04 /* Collision on last transmission */ 108 #define FE_D0_JABBER 0x08 /* Jabber */ 109 #define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */ 110 #define FE_D0_PKTRCD 0x20 /* No collision on last transmission */ 111 #define FE_D0_NETBSY 0x40 /* Network Busy (Carrier Detected) */ 112 #define FE_D0_TXDONE 0x80 /* Transmission complete */ 113 114 /* DLCR1 -- receiver status */ 115 #define FE_D1_OVRFLO 0x01 /* Receiver buffer overflow */ 116 #define FE_D1_CRCERR 0x02 /* CRC error on last packet */ 117 #define FE_D1_ALGERR 0x04 /* Alignment error on last packet */ 118 #define FE_D1_SRTPKT 0x08 /* Short (RUNT) packet is received */ 119 #define FE_D1_RMTRST 0x10 /* Remote reset packet (type = 0x0900) */ 120 #define FE_D1_DMAEOP 0x20 /* Host asserted End of DMA OPeration */ 121 #define FE_D1_BUSERR 0x40 /* Bus read error */ 122 #define FE_D1_PKTRDY 0x80 /* Packet(s) ready on receive buffer */ 123 124 #define FE_D1_ERRBITS "\20\4SRTPKT\3ALGERR\2CRCERR\1OVRFLO" 125 126 /* DLCR2 -- transmitter interrupt control; same layout as DLCR0 */ 127 #define FE_D2_BUSERR FE_D0_BUSERR 128 #define FE_D2_COLL16 FE_D0_COLL16 129 #define FE_D2_COLLID FE_D0_COLLID 130 #define FE_D2_JABBER FE_D0_JABBER 131 #define FE_D2_TXDONE FE_D0_TXDONE 132 133 #define FE_D2_RESERVED 0x70 134 135 /* DLCR3 -- receiver interrupt control; same layout as DLCR1 */ 136 #define FE_D3_OVRFLO FE_D1_OVRFLO 137 #define FE_D3_CRCERR FE_D1_CRCERR 138 #define FE_D3_ALGERR FE_D1_ALGERR 139 #define FE_D3_SRTPKT FE_D1_SRTPKT 140 #define FE_D3_RMTRST FE_D1_RMTRST 141 #define FE_D3_DMAEOP FE_D1_DMAEOP 142 #define FE_D3_BUSERR FE_D1_BUSERR 143 #define FE_D3_PKTRDY FE_D1_PKTRDY 144 145 /* DLCR4 -- transmitter operation mode */ 146 #define FE_D4_DSC 0x01 /* Disable carrier sense on trans. */ 147 #define FE_D4_LBC 0x02 /* Loop back test control */ 148 #define FE_D4_CNTRL 0x04 /* - ??? */ 149 #define FE_D4_TEST1 0x08 /* Test output #1 */ 150 #define FE_D4_COL 0xF0 /* Collision counter */ 151 152 #define FE_D4_LBC_ENABLE 0x00 /* Perform loop back test */ 153 #define FE_D4_LBC_DISABLE 0x02 /* Normal operation */ 154 155 #define FE_D4_COL_SHIFT 4 156 157 /* DLCR5 -- receiver operation mode */ 158 #define FE_D5_AFM0 0x01 /* Receive packets for other stations */ 159 #define FE_D5_AFM1 0x02 /* Receive packets for this station */ 160 #define FE_D5_RMTRST 0x04 /* Enable remote reset operation */ 161 #define FE_D5_SRTPKT 0x08 /* Accept short (RUNT) packets */ 162 #define FE_D5_SRTADR 0x10 /* Short (16 bits?) MAC address */ 163 #define FE_D5_BADPKT 0x20 /* Accept packets with error */ 164 #define FE_D5_BUFEMP 0x40 /* Receive buffer is empty */ 165 #define FE_D5_TEST2 0x80 /* Test output #2 */ 166 167 /* DLCR6 -- hardware configuration #0 */ 168 #define FE_D6_BUFSIZ 0x03 /* Size of NIC buffer SRAM */ 169 #define FE_D6_TXBSIZ 0x0C /* Size (and config)of trans. buffer */ 170 #define FE_D6_BBW 0x10 /* Buffer SRAM bus width */ 171 #define FE_D6_SBW 0x20 /* System bus width */ 172 #define FE_D6_SRAM 0x40 /* Buffer SRAM access time */ 173 #define FE_D6_DLC 0x80 /* Disable DLC (receiver/transmitter) */ 174 175 #define FE_D6_BUFSIZ_8KB 0x00 /* The board has 8KB SRAM */ 176 #define FE_D6_BUFSIZ_16KB 0x01 /* The board has 16KB SRAM */ 177 #define FE_D6_BUFSIZ_32KB 0x02 /* The board has 32KB SRAM */ 178 #define FE_D6_BUFSIZ_64KB 0x03 /* The board has 64KB SRAM */ 179 180 #define FE_D6_TXBSIZ_1x2KB 0x00 /* Single 2KB buffer for trans. */ 181 #define FE_D6_TXBSIZ_2x2KB 0x04 /* Double 2KB buffers */ 182 #define FE_D6_TXBSIZ_2x4KB 0x08 /* Double 4KB buffers */ 183 #define FE_D6_TXBSIZ_2x8KB 0x0C /* Double 8KB buffers */ 184 185 #define FE_D6_BBW_WORD 0x00 /* SRAM has 16 bit data line */ 186 #define FE_D6_BBW_BYTE 0x10 /* SRAM has 8 bit data line */ 187 188 #define FE_D6_SBW_WORD 0x00 /* Access with 16 bit (AT) bus */ 189 #define FE_D6_SBW_BYTE 0x20 /* Access with 8 bit (XT) bus */ 190 191 #define FE_D6_SRAM_150ns 0x00 /* The board has slow SRAM */ 192 #define FE_D6_SRAM_100ns 0x40 /* The board has fast SRAM */ 193 194 #define FE_D6_DLC_ENABLE 0x00 /* Normal operation */ 195 #define FE_D6_DLC_DISABLE 0x80 /* Stop sending/receiving */ 196 197 /* DLC7 -- hardware configuration #1 */ 198 #define FE_D7_BYTSWP 0x01 /* Host byte order control */ 199 #define FE_D7_EOPPOL 0x02 /* Polarity of DMA EOP signal */ 200 #define FE_D7_RBS 0x0C /* Register bank select */ 201 #define FE_D7_RDYPNS 0x10 /* Senses RDYPNSEL input signal */ 202 #define FE_D7_POWER 0x20 /* Stand-by (power down) mode control */ 203 #define FE_D7_ED 0xC0 /* Encoder/Decoder config (for MB86960) */ 204 #define FE_D7_IDENT 0xC0 /* Chip identification */ 205 206 #define FE_D7_BYTSWP_LH 0x00 /* DEC/Intel byte order */ 207 #define FE_D7_BYTSWP_HL 0x01 /* IBM/Motorolla byte order */ 208 209 #define FE_D7_RBS_DLCR 0x00 /* Select DLCR8-15 */ 210 #define FE_D7_RBS_MAR 0x04 /* Select MAR8-15 */ 211 #define FE_D7_RBS_BMPR 0x08 /* Select BMPR8-15 */ 212 213 #define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */ 214 #define FE_D7_POWER_UP 0x20 /* Normal operation */ 215 216 #define FE_D7_ED_NORMAL 0x00 /* Normal NICE */ 217 #define FE_D7_ED_MON 0x40 /* NICE + Monitor */ 218 #define FE_D7_ED_BYPASS 0x80 /* Encoder/Decorder Bypass */ 219 #define FE_D7_ED_TEST 0xC0 /* Encoder/Decorder Test */ 220 221 #define FE_D7_IDENT_86960 0x00 /* MB86960 (NICE) */ 222 #define FE_D7_IDENT_86964 0x40 /* MB86964 */ 223 #define FE_D7_IDENT_86967 0x80 /* MB86967 */ 224 #define FE_D7_IDENT_86965 0xC0 /* MB86965 (EtherCoupler) */ 225 226 /* DLCR8 thru DLCR13 are for Ethernet station address. */ 227 228 /* DLCR14 and DLCR15 are for TDR (Time Domain Reflectometry). */ 229 230 /* MAR8 thru MAR15 are for Multicast address filter. */ 231 232 /* BMPR8 and BMPR9 are for packet data. */ 233 234 /* BMPR10 -- transmitter start trigger */ 235 #define FE_B10_START 0x80 /* Start transmitter */ 236 #define FE_B10_COUNT 0x7F /* Packet count */ 237 238 /* BMPR11 -- 16 collisions control */ 239 #define FE_B11_CTRL 0x01 /* Skip or resend errored packets */ 240 #define FE_B11_MODE1 0x02 /* Restart transmitter after COLL16 */ 241 #define FE_B11_MODE2 0x04 /* Automatic restart enable */ 242 243 #define FE_B11_CTRL_RESEND 0x00 /* Re-send the collided packet */ 244 #define FE_B11_CTRL_SKIP 0x01 /* Skip the collided packet */ 245 246 /* BMPR12 -- DMA enable */ 247 #define FE_B12_TXDMA 0x01 /* Enable transmitter DMA */ 248 #define FE_B12_RXDMA 0x02 /* Enable receiver DMA */ 249 250 /* BMPR13 -- DMA control */ 251 #define FE_B13_BSTCTL 0x03 /* DMA burst mode control */ 252 #define FE_B13_TPTYPE 0x04 /* Twisted pair cable impedance */ 253 #define FE_B13_PORT 0x18 /* Port (TP/AUI) selection */ 254 #define FE_B13_LNKTST 0x20 /* Link test enable */ 255 #define FE_B13_SQTHLD 0x40 /* Lower squelch threshold */ 256 #define FE_B13_IOUNLK 0x80 /* Change I/O base address */ 257 258 #define FE_B13_BSTCTL_1 0x00 259 #define FE_B13_BSTCTL_4 0x01 260 #define FE_B13_BSTCTL_8 0x02 261 #define FE_B13_BSTCLT_12 0x03 262 263 #define FE_B13_TPTYPE_UTP 0x00 /* Unshielded (standard) cable */ 264 #define FE_B13_TPTYPE_STP 0x04 /* Shielded (IBM) cable */ 265 266 #define FE_B13_PORT_AUTO 0x00 /* Auto detected */ 267 #define FE_B13_PORT_TP 0x08 /* Force TP */ 268 #define FE_B13_PORT_AUI 0x18 /* Force AUI */ 269 270 /* BMPR14 -- More receiver control and more transmission interrupts */ 271 #define FE_B14_FILTER 0x01 /* Filter out self-originated packets */ 272 #define FE_B14_SQE 0x02 /* SQE interrupt enable */ 273 #define FE_B14_SKIP 0x04 /* Skip a received packet */ 274 #define FE_B14_RJAB 0x20 /* RJAB interrupt enable */ 275 #define FE_B14_LLD 0x40 /* Local-link-down interrupt enable */ 276 #define FE_B14_RLD 0x80 /* Remote-link-down interrupt enable */ 277 278 /* BMPR15 -- More transmitter status; basically same layout as BMPR14 */ 279 #define FE_B15_SQE FE_B14_SQE 280 #define FE_B15_RCVPOL 0x08 /* Reversed receive line polarity */ 281 #define FE_B15_RMTPRT 0x10 /* ??? */ 282 #define FE_B15_RAJB FE_B14_RJAB 283 #define FE_B15_LLD FE_B14_LLD 284 #define FE_B15_RLD FE_B14_RLD 285 286 /* BMPR16 -- EEPROM control */ 287 #define FE_B16_DOUT 0x04 /* EEPROM Data in (CPU to EEPROM) */ 288 #define FE_B16_SELECT 0x20 /* EEPROM chip select */ 289 #define FE_B16_CLOCK 0x40 /* EEPROM shift clock */ 290 #define FE_B16_DIN 0x80 /* EEPROM data out (EEPROM to CPU) */ 291 292 /* BMPR17 -- EEPROM data */ 293 #define FE_B17_DATA 0x80 /* EEPROM data bit */ 294 295 /* BMPR18 I/O Base Address (Only JLI mode) */ 296 297 /* BMPR19 -- Jumperless Setting (Only JLI mode) */ 298 #define FE_B19_IRQ 0xC0 299 #define FE_B19_IRQ_SHIFT 6 300 301 #define FE_B19_ROM 0x38 302 #define FE_B19_ROM_SHIFT 3 303 304 #define FE_B19_ADDR 0x07 305 #define FE_B19_ADDR_SHIFT 0 306 307 /* 308 * EEPROM specification (of JLI mode). 309 */ 310 311 /* Number of bytes in an EEPROM accessible through 86965. */ 312 #define FE_EEPROM_SIZE 32 313 314 /* Offset for JLI config; automatically copied into BMPR19 at startup. */ 315 #define FE_EEPROM_CONF 0x00 316 317 /* Delay for 93c06 EEPROM access */ 318 #define FE_EEPROM_DELAY() DELAY(4) 319 320 /* 321 * EEPROM allocation of AT1700/RE2000. 322 */ 323 #define FE_ATI_EEP_ADDR 0x08 /* Station address (0x08-0x0d) */ 324 #define FE_ATI_EEP_MEDIA 0x18 /* Media type */ 325 #define FE_ATI_EEP_MAGIC 0x19 /* XXX Magic */ 326 #define FE_ATI_EEP_MODEL 0x1e /* Hardware type */ 327 #define FE_ATI_MODEL_AT1700T 0x00 328 #define FE_ATI_MODEL_AT1700BT 0x01 329 #define FE_ATI_MODEL_AT1700FT 0x02 330 #define FE_ATI_MODEL_AT1700AT 0x03 331 #define FE_ATI_EEP_REVISION 0x1f /* Hardware revision */ 332 333 /* 334 * Some 86960 specific constants. 335 */ 336 337 /* Length (in bytes) of a Multicast Address Filter. */ 338 #define FE_FILTER_LEN 8 339 340 /* How many packets we can put in the transmission buffer on NIC memory. */ 341 #define FE_QUEUEING_MAX 127 342 343 /* Size (in bytes) of a "packet length" word in transmission buffer. */ 344 #define FE_TXLEN_SIZE 2 345 346 /* receive packet status in the receive packet header. */ 347 #define FE_RXSTAT_GOODPKT 0x20 348 #define FE_RXSTAT_RMT0900 0x10 349 #define FE_RXSTAT_SHORTPKT 0x08 350 #define FE_RXSTAT_ALIGNERR 0x04 351 #define FE_RXSTAT_CRCERR 0x02 352 353 /* 354 * FUJITSU MBH10302 specific Registers. 355 */ 356 357 #define FE_MBH0 0x10 /* Master interrupt register */ 358 #define FE_MBH_ENADDR 0x1A /* Mac address */ 359 #define FE_MBH0_MASK 0x0D 360 #define FE_MBH0_INTR_ENABLE 0x10 /* Enable interrupts */ 361
Indexes created Sun Sep 21 20:09:37 GMT 2025