1 /* $NetBSD: ffbreg.h,v 1.12 2022/05/20 19:34:22 andvar Exp $ */ 2 /* $OpenBSD: creatorreg.h,v 1.5 2002/07/29 06:21:45 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef FFB_REG_H 36 #define FFB_REG_H 37 38 /* Number of register sets */ 39 #define FFB_NREGS 24 40 41 /* Register set numbers */ 42 #define FFB_REG_PROM 0 43 #define FFB_REG_DAC 1 44 #define FFB_REG_FBC 2 45 #define FFB_REG_DFB8R 3 46 #define FFB_REG_DFB8G 4 47 #define FFB_REG_DFB8B 5 48 #define FFB_REG_DFB8X 6 49 #define FFB_REG_DFB24 7 50 #define FFB_REG_DFB32 8 51 #define FFB_REG_SFB8R 9 52 #define FFB_REG_SFB8G 10 53 #define FFB_REG_SFB8B 11 54 #define FFB_REG_SFB8X 12 55 #define FFB_REG_SFB32 13 56 #define FFB_REG_SFB64 14 57 #define FFB_REG_DFB422A 15 58 59 #define FFB_DAC_TYPE 0x0 60 #define FFB_DAC_VALUE 0x4 61 #define FFB_DAC_TYPE2 0x8 62 #define FFB_DAC_VALUE2 0xc 63 64 /* DAC "TYPE" commands (registers) */ 65 #define FFB_DAC_PLL_CTRL 0x0000 /* PLL control (frequency) */ 66 #define FFB_DAC_PIX_FMT 0x1000 /* Pixel format control */ 67 #define FFB_DAC_USR_CTRL 0x1001 /* user control */ 68 #define FFB_DAC_SCMAP 0x2000 /* set (load) cmap */ 69 #define FFB_DAC_DAC_CTRL 0x5001 /* DAC control */ 70 #define FFB_DAC_TGC 0x6000 /* timing generator control */ 71 #define FFB_DAC_VBE 0x6001 /* vertical blank end */ 72 #define FFB_DAC_VBS 0x6002 /* vertical blank start */ 73 #define FFB_DAC_VSE 0x6003 /* vertical sync end */ 74 #define FFB_DAC_VSS 0x6004 /* vertical sync start */ 75 #define FFB_DAC_HRE 0x6005 /* horizontal serration end */ 76 #define FFB_DAC_HBE 0x6006 /* horizontal blank end */ 77 #define FFB_DAC_HBS 0x6007 /* horizontal blank start */ 78 #define FFB_DAC_HSE 0x6008 /* horizontal sync end */ 79 #define FFB_DAC_HSS 0x6009 /* horizontal sync start */ 80 #define FFB_DAC_HCE 0x600a /* horiz. serial clock enable end */ 81 #define FFB_DAC_HCS 0x600b /* horiz. serial clock enable start */ 82 #define FFB_DAC_EPE 0x600c /* equalisation pulse end */ 83 #define FFB_DAC_EIE 0x600d /* equalisation interval end */ 84 #define FFB_DAC_EIS 0x600e /* equalisation interval start */ 85 #define FFB_DAC_TVC 0x600f /* timing generator vertical counter */ 86 #define FFB_DAC_THC 0x6010 /* timing generator horiz. counter */ 87 #define FFB_DAC_DEVID 0x8000 /* DAC device ID (version) */ 88 #define FFB_DAC_CFG_MPDATA 0x8001 /* monitor serial port data */ 89 #define FFB_DAC_CFG_MPSENSE 0x8002 /* monitor serial port sense */ 90 91 /* 0x1000 pixel format control */ 92 #define FFB_DAC_PIX_FMT_421 0x02 /* 4/2:1 */ 93 #define FFB_DAC_PIX_FMT_821 0x03 /* 8/2:1 */ 94 95 /* 0x1001 user control */ 96 #define FFB_DAC_USR_CTRL_BLANK 0x02 /* asynchronous blank */ 97 #define FFB_DAC_USR_CTRL_DOUBLE 0x04 /* double-buffer enable */ 98 #define FFB_DAC_USR_CTRL_OVERLAY 0x08 /* transparent overlay enable */ 99 #define FFB_DAC_USR_CTRL_WMODE_C 0x00 /* window mode combined */ 100 #define FFB_DAC_USR_CTRL_WMODE_S4 0x10 /* window mode separate 4 */ 101 #define FFB_DAC_USR_CTRL_WMODE_S8 0x20 /* window mode separate 8 */ 102 103 /* 0x5001 DAC control */ 104 #define FFB_DAC_DAC_CTRL_SYNC_G 0x0020 /* enable sync on green */ 105 #define FFB_DAC_DAC_CTRL_PED_ENABLE 0x0040 /* enable pedestal */ 106 #define FFB_DAC_DAC_CTRL_VSYNC_DIS 0x0080 /* disable vsync pin */ 107 #define FFB_DAC_DAC_CTRL_POS_VSYNC 0x0100 /* enable pos. vsync */ 108 109 /* 0x6000 timing generator control */ 110 #define FFB_DAC_TGC_VIDEO_ENABLE 0x01 /* enable DAC outputs */ 111 #define FFB_DAC_TGC_TIMING_ENABLE 0x02 /* enable timing generator */ 112 #define FFB_DAC_TGC_HSYNC_DISABLE 0x04 /* disable hsync on csync */ 113 #define FFB_DAC_TGC_VSYNC_DISABLE 0x08 /* disable vsync on csync */ 114 #define FFB_DAC_TGC_EQUAL_DISABLE 0x10 /* disable equalisation */ 115 #define FFB_DAC_TGC_MASTER_ENABLE 0x20 /* enable master mode */ 116 #define FFB_DAC_TGC_ILACE_ENABLE 0x40 /* enable interlaced mode */ 117 118 /* 0x8001 monitor serial port data */ 119 #define FFB_DAC_CFG_MPDATA_SCL 0x01 /* SCL Data */ 120 #define FFB_DAC_CFG_MPDATA_SDA 0x02 /* SDA Data */ 121 122 /* 0x8002 monitor serial port sense */ 123 #define FFB_DAC_CFG_MPSENSE_SCL 0x01 /* SCL Sense */ 124 #define FFB_DAC_CFG_MPSENSE_SDA 0x02 /* SDA Sense */ 125 126 /* DAC "TYPE2" commands */ 127 #define FFB_DAC_CURSENAB 0x100 /* cursor enable */ 128 #define FFB_DAC_CURSECMAP 0x102 /* set cursor colormap */ 129 #define FFB_DAC_CURSEPOS 0x104 /* set cursor position */ 130 131 #define FFB_FBC_ALPHA 0x00c 132 #define FFB_FBC_RED 0x010 133 #define FFB_FBC_GREEN 0x014 134 #define FFB_FBC_BLUE 0x018 135 #define FFB_FBC_DEPTH 0x01c 136 #define FFB_FBC_Y 0x020 137 #define FFB_FBC_X 0x024 138 #define FFB_FBC_RYF 0x030 139 #define FFB_FBC_RXF 0x034 140 #define FFB_FBC_DMYF 0x040 141 #define FFB_FBC_DMXF 0x044 142 #define FFB_FBC_EBYI 0x050 143 #define FFB_FBC_EBXI 0x054 144 #define FFB_FBC_BY 0x060 145 #define FFB_FBC_BX 0x064 146 #define FFB_FBC_DY 0x068 147 #define FFB_FBC_DX 0x06c 148 #define FFB_FBC_BH 0x070 149 #define FFB_FBC_BW 0x074 150 #define FFB_FBC_SUVTX 0x100 151 #define FFB_FBC_PPC 0x200 /* pixel processor control */ 152 #define FFB_FBC_WID 0x204 /* current WID */ 153 #define FFB_FBC_FG 0x208 154 #define FFB_FBC_BG 0x20c 155 #define FFB_FBC_CONSTY 0x210 156 #define FFB_FBC_CONSTZ 0x214 157 #define FFB_FBC_XCLIP 0x218 158 #define FFB_FBC_DCSS 0x21c 159 #define FFB_FBC_VCLIPMIN 0x220 /* Viewclip XY Min Bounds */ 160 #define FFB_FBC_VCLIPMAX 0x224 161 #define FFB_FBC_VCLIPZMIN 0x228 162 #define FFB_FBC_VCLIPZMAX 0x22c 163 #define FFB_FBC_DCSF 0x230 164 #define FFB_FBC_DCSB 0x234 165 #define FFB_FBC_DCZF 0x238 166 #define FFB_FBC_DCZB 0x23c 167 #define FFB_FBC_BLENDC 0x244 168 #define FFB_FBC_BLENDC1 0x248 169 #define FFB_FBC_BLENDC2 0x24c 170 #define FFB_FBC_FBRAMITC 0x250 171 #define FFB_FBC_FBC 0x254 /* Frame Buffer Control */ 172 #define FFB_FBC_ROP 0x258 /* Raster OPeration */ 173 #define FFB_FBC_CMP 0x25c /* Frame Buffer Compare */ 174 #define FFB_FBC_MATCHAB 0x260 /* Buffer AB Match Mask */ 175 #define FFB_FBC_MATCHC 0x264 176 #define FFB_FBC_MAGNAB 0x268 /* Buffer AB Magnitude Mask */ 177 #define FFB_FBC_MAGNC 0x26c 178 #define FFB_FBC_FBCFG0 0x270 179 #define FFB_FBC_FBCFG1 0x274 180 #define FFB_FBC_FBCFG2 0x278 181 #define FFB_FBC_FBCFG3 0x27c 182 #define FFB_FBC_PPCFG 0x280 183 #define FFB_FBC_PICK 0x284 184 #define FFB_FBC_FILLMODE 0x288 185 #define FFB_FBC_FBRAMWAC 0x28c /* FB RAM Write Address Control */ 186 #define FFB_FBC_PMASK 0x290 /* RGB Plane Mask */ 187 #define FFB_FBC_XPMASK 0x294 /* X PlaneMask */ 188 #define FFB_FBC_YPMASK 0x298 189 #define FFB_FBC_ZPMASK 0x29c 190 #define FFB_FBC_CLIP0MIN 0x2a0 /* Auxiliary Viewport Clips */ 191 #define FFB_FBC_CLIP0MAX 0x2a4 192 #define FFB_FBC_CLIP1MIN 0x2a8 193 #define FFB_FBC_CLIP1MAX 0x2ac 194 #define FFB_FBC_CLIP2MIN 0x2b0 195 #define FFB_FBC_CLIP2MAX 0x2b4 196 #define FFB_FBC_CLIP3MIN 0x2b8 197 #define FFB_FBC_CLIP3MAX 0x2bc 198 #define FFB_FBC_RAWBLEND2 0x2c0 199 #define FFB_FBC_RAWPREBLEND 0x2c4 200 #define FFB_FBC_RAWSTENCIL 0x2c8 201 #define FFB_FBC_RAWSTENCILCTL 0x2cc 202 #define FFB_FBC_THREEDRAM1 0x2d0 203 #define FFB_FBC_THREEDRAM2 0x2d4 204 #define FFB_FBC_PASSIN 0x2d8 205 #define FFB_FBC_RAWCLRDEPTH 0x2dc 206 #define FFB_FBC_RAWPMASK 0x2e0 207 #define FFB_FBC_RAWCSRC 0x2e4 208 #define FFB_FBC_RAWMATCH 0x2e8 209 #define FFB_FBC_RAWMAGN 0x2ec 210 #define FFB_FBC_RAWROPBLEND 0x2f0 211 #define FFB_FBC_RAWCMP 0x2f4 212 #define FFB_FBC_RAWWAC 0x2f8 213 #define FFB_FBC_FBRAMID 0x2fc 214 #define FFB_FBC_DRAWOP 0x300 /* Draw OPeration */ 215 #define FFB_FBC_FONTLPAT 0x30c /* Line Pattern control */ 216 #define FFB_FBC_FONTXY 0x314 /* XY Font coordinate */ 217 #define FFB_FBC_FONTW 0x318 /* Font Width */ 218 #define FFB_FBC_FONTINC 0x31c /* Font Increment */ 219 #define FFB_FBC_FONT 0x320 220 #define FFB_FBC_BLEND2 0x330 221 #define FFB_FBC_PREBLEND 0x334 222 #define FFB_FBC_STENCIL 0x338 223 #define FFB_FBC_STENCILCTL 0x33c 224 #define FFB_FBC_DCSS1 0x350 225 #define FFB_FBC_DCSS2 0x354 226 #define FFB_FBC_DCSS3 0x358 227 #define FFB_FBC_WIDPMASK 0x35c 228 #define FFB_FBC_DCS2 0x360 229 #define FFB_FBC_DCS3 0x364 230 #define FFB_FBC_DCS4 0x368 231 #define FFB_FBC_DCD2 0x370 232 #define FFB_FBC_DCD3 0x374 233 #define FFB_FBC_DCD4 0x378 234 #define FFB_FBC_PATTERN 0x380 235 #define FFB_FBC_DEVID 0x800 236 #define FFB_FBC_UCSR 0x900 /* User Control & Status */ 237 #define FFB_FBC_MER 0x980 238 #define FFB_FBC_RAMCNF0 0x10270 /* FBRAM Configuration 0 */ 239 #define FFB_FBC_RAMCNF1 0x10274 /* FBRAM Configuration 1 */ 240 #define FFB_FBC_RAMCNF2 0x10278 /* FBRAM Configuration 2 */ 241 #define FFB_FBC_RAMCNF3 0x1027c /* FBRAM Configuration 3 */ 242 #define FFB_FBC_KCSR 0x10900 /* Kernel Control & Status */ 243 244 #define FFB_FBC_WB_A 0x20000000 245 #define FFB_FBC_WB_B 0x40000000 246 #define FFB_FBC_WE_FORCEOFF 0x00100000 247 #define FFB_FBC_WE_FORCEON 0x00200000 248 #define FFB_FBC_WM_COMBINED 0x00080000 249 #define FFB_FBC_RB_A 0x00004000 250 #define FFB_FBC_SB_BOTH 0x00003000 251 #define FFB_FBC_ZE_OFF 0x00000400 252 #define FFB_FBC_YE_OFF 0x00000100 253 #define FFB_FBC_XE_ON 0x00000080 254 #define FFB_FBC_XE_OFF 0x00000040 255 #define FFB_FBC_RGBE_ON 0x0000002a 256 #define FFB_FBC_RGBE_OFF 0x00000015 257 #define FFB_FBC_RGBE_MASK 0x0000003f 258 259 #define FBC_PPC_FW_DIS 0x00800000 /* force wid disable */ 260 #define FBC_PPC_FW_ENA 0x00c00000 /* force wid enable */ 261 #define FBC_PPC_ACE_DIS 0x00040000 /* aux clip disable */ 262 #define FBC_PPC_ACE_AUXSUB 0x00080000 /* aux clip add */ 263 #define FBC_PPC_ACE_AUXADD 0x000c0000 /* aux clip subtract */ 264 #define FBC_PPC_DCE_DIS 0x00020000 /* depth cue disable */ 265 #define FBC_PPC_DCE_ENA 0x00020000 /* depth cue enable */ 266 #define FBC_PPC_ABE_DIS 0x00008000 /* alpha blend disable */ 267 #define FBC_PPC_ABE_ENA 0x0000c000 /* alpha blend enable */ 268 #define FBC_PPC_VCE_DIS 0x00001000 /* view clip disable */ 269 #define FBC_PPC_VCE_2D 0x00002000 /* view clip 2d */ 270 #define FBC_PPC_VCE_3D 0x00003000 /* view clip 3d */ 271 #define FBC_PPC_APE_DIS 0x00000800 /* area pattern disable */ 272 #define FBC_PPC_APE_ENA 0x00000c00 /* area pattern enable */ 273 #define FBC_PPC_TBE_OPAQUE 0x00000200 /* opaque background */ 274 #define FBC_PPC_TBE_TRANSPAR 0x00000300 /* transparent background */ 275 #define FBC_PPC_ZS_VAR 0x00000080 /* z source ??? */ 276 #define FBC_PPC_ZS_CONST 0x000000c0 /* z source ??? */ 277 #define FBC_PPC_YS_VAR 0x00000020 /* y source ??? */ 278 #define FBC_PPC_YS_CONST 0x00000030 /* y source ??? */ 279 #define FBC_PPC_XS_WID 0x00000004 /* x source ??? */ 280 #define FBC_PPC_XS_VAR 0x00000008 /* x source ??? */ 281 #define FBC_PPC_XS_CONST 0x0000000c /* x source ??? */ 282 #define FBC_PPC_CS_VAR 0x00000002 /* color source ??? */ 283 #define FBC_PPC_CS_CONST 0x00000003 /* color source ??? */ 284 285 #define FBC_ROP_NEW 0x83 286 #define FBC_ROP_OLD 0x85 287 #define FBC_ROP_INVERT 0x8a 288 289 #define FBC_UCSR_FIFO_MASK 0x00000fff 290 #define FBC_UCSR_FB_BUSY 0x01000000 291 #define FBC_UCSR_RP_BUSY 0x02000000 292 #define FBC_UCSR_READ_ERR 0x40000000 293 #define FBC_UCSR_FIFO_OVFL 0x80000000 294 295 #define FBC_DRAWOP_DOT 0x00 296 #define FBC_DRAWOP_AADOT 0x01 297 #define FBC_DRAWOP_BRLINECAP 0x02 298 #define FBC_DRAWOP_BRLINEOPEN 0x03 299 #define FBC_DRAWOP_DDLINE 0x04 300 #define FBC_DRAWOP_AALINE 0x05 301 #define FBC_DRAWOP_TRIANGLE 0x06 302 #define FBC_DRAWOP_POLYGON 0x07 303 #define FBC_DRAWOP_RECTANGLE 0x08 304 #define FBC_DRAWOP_FASTFILL 0x09 305 #define FBC_DRAWOP_BCOPY 0x0a /* block copy: not implemented */ 306 #define FBC_DRAWOP_VSCROLL 0x0b /* vertical scroll */ 307 308 #define FBC_CFG0_RES_MASK 0x30 /* Resolution bits */ 309 #define FBC_CFG0_STEREO 0x10 /* Stereo */ 310 #define FBC_CFG0_SINGLE_BUF 0x20 /* Single buffer */ 311 #define FBC_CFG0_DOUBLE_BUF 0x30 /* Double buffer */ 312 313 /* Alpha Blend Control */ 314 #define FFB_BLENDC_FORCE_ONE 0x00000010 /* Defines 0xff as 1.0 */ 315 #define FFB_BLENDC_DF_MASK 0x0000000c /* Destination Frac Mask */ 316 #define FFB_BLENDC_DF_ZERO 0x00000000 /* Destination Frac: 0.00 */ 317 #define FFB_BLENDC_DF_ONE 0x00000004 /* Destination Frac: 1.00 */ 318 #define FFB_BLENDC_DF_ONE_M_A 0x00000008 /* Destination Frac: 1.00 - Xsrc */ 319 #define FFB_BLENDC_DF_A 0x0000000c /* Destination Frac: Xsrc */ 320 #define FFB_BLENDC_SF_MASK 0x00000003 /* Source Frac Mask */ 321 #define FFB_BLENDC_SF_ZERO 0x00000000 /* Source Frac: 0.00 */ 322 #define FFB_BLENDC_SF_ONE 0x00000001 /* Source Frac: 1.00 */ 323 #define FFB_BLENDC_SF_ONE_M_A 0x00000002 /* Source Frac: 1.00 - Xsrc */ 324 #define FFB_BLENDC_SF_A 0x00000003 /* Source Frac: Xsrc */ 325 326 327 #endif /* FFB_REG_H */ 328
Indexes created Mon Sep 22 21:09:42 GMT 2025