1 /* $NetBSD: db_disasm.h,v 1.11 2023/09/26 12:46:30 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Christian E. Hopps. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #define ENCB(b7,b6,b5,b4,b3,b2,b1,b0) \ 34 ((b7 << 7) | (b6 << 6) | (b5 << 5) | (b4 << 4) | \ 35 (b3 << 3) | (b2 << 2) | (b1 << 1) | (b0)) 36 37 38 #define ENCW(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \ 39 ((ENCB(b15,b14,b13,b12,b11,b10,b9,b8) << 8) |\ 40 ENCB(b7,b6,b5,b4,b3,b2,b1,b0)) 41 42 /* 43 * Group Bit-manip (0000) 44 */ 45 #define ANDITOCCR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1) 46 #define ANDIROSR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1) 47 #define EORITOCCR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1) 48 #define EORITOSR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1) 49 #define ORITOCCR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1) 50 #define ORITOSR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1) 51 #define ANDITOCCR_INST ENCW(0,0,0,0, 0,0,1,0, 0,0,1,1, 1,1,0,0) 52 #define ANDIROSR_INST ENCW(0,0,0,0, 0,0,1,0, 0,1,1,1, 1,1,0,0) 53 #define EORITOCCR_INST ENCW(0,0,0,0, 1,0,1,0, 0,0,1,1, 1,1,0,0) 54 #define EORITOSR_INST ENCW(0,0,0,0, 1,0,1,0, 0,1,1,1, 1,1,0,0) 55 #define ORITOCCR_INST ENCW(0,0,0,0, 0,0,0,0, 0,0,1,1, 1,1,0,0) 56 #define ORITOSR_INST ENCW(0,0,0,0, 0,0,0,0, 0,1,1,1, 1,1,0,0) 57 58 /* 59 * RTM: this is what gas *and* my amiga assembler spit out, however 60 * my moto manual disagrees, another 030 manual I have also has 61 * something different from all of the above! 62 * 63 * BTW there may be a consipircy, as many may recognize 64 * from the acronym associated with this opcode's name. *grin* 65 */ 66 #define RTM_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 0,0,0,0) 67 #define RTM_INST ENCW(0,0,0,0, 0,1,1,0, 1,1,0,0, 0,0,0,0) 68 69 /* Note: bit eight being 1 here allows these to be check before all else */ 70 71 /* Note: for movp bits 5-3, specify a mode An, which all the other 72 * bit 8 set commands do not, so have check first. */ 73 #define MOVEP_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,1,1, 1,0,0,0) 74 #define MOVEP_INST ENCW(0,0,0,0, 0,0,0,1, 0,0,0,0, 1,0,0,0) 75 76 #define BCHGD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0) 77 #define BCLRD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0) 78 #define BSETD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0) 79 #define BTSTD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0) 80 #define BCHGD_INST ENCW(0,0,0,0, 0,0,0,1, 0,1,0,0, 0,0,0,0) 81 #define BCLRD_INST ENCW(0,0,0,0, 0,0,0,1, 1,0,0,0, 0,0,0,0) 82 #define BSETD_INST ENCW(0,0,0,0, 0,0,0,1, 1,1,0,0, 0,0,0,0) 83 #define BTSTD_INST ENCW(0,0,0,0, 0,0,0,1, 0,0,0,0, 0,0,0,0) 84 85 #define BCHGS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 86 #define BCLRS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 87 #define BSETS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 88 #define BTSTS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 89 #define BCHGS_INST ENCW(0,0,0,0, 1,0,0,0, 0,1,0,0, 0,0,0,0) 90 #define BCLRS_INST ENCW(0,0,0,0, 1,0,0,0, 1,0,0,0, 0,0,0,0) 91 #define BSETS_INST ENCW(0,0,0,0, 1,0,0,0, 1,1,0,0, 0,0,0,0) 92 #define BTSTS_INST ENCW(0,0,0,0, 1,0,0,0, 0,0,0,0, 0,0,0,0) 93 94 #define CAS2_MASK ENCW(1,1,1,1, 1,1,0,1, 1,1,1,1, 1,1,1,1) 95 #define CAS2_INST ENCW(0,0,0,0, 1,1,0,0, 1,1,1,1, 1,1,0,0) 96 97 #define CAS_MASK ENCW(1,1,1,1, 1,0,0,1, 1,1,0,0, 0,0,0,0) 98 #define CHK2_MASK ENCW(1,1,1,1, 1,0,0,1, 1,1,0,0, 0,0,0,0) 99 #define CMP2_MASK ENCW(1,1,1,1, 1,0,0,1, 1,1,0,0, 0,0,0,0) 100 #define CAS_INST ENCW(0,0,0,0, 1,0,0,0, 1,1,0,0, 0,0,0,0) 101 #define CHK2_INST ENCW(0,0,0,0, 0,0,0,0, 1,1,0,0, 0,0,0,0) 102 #define CMP2_INST ENCW(0,0,0,0, 0,0,0,0, 1,1,0,0, 0,0,0,0) 103 104 /* close ties with Bxxx but bit eight here is 0 and there 1 */ 105 /* also above (cas,chk2,cmp2) bits 7-6 here are size and never 11 */ 106 #define ADDI_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 107 #define ANDI_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 108 #define CMPI_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 109 #define EORI_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 110 #define MOVES_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 111 #define ORI_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 112 #define SUBI_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 113 #define ADDI_INST ENCW(0,0,0,0, 0,1,1,0, 0,0,0,0, 0,0,0,0) 114 #define ANDI_INST ENCW(0,0,0,0, 0,0,1,0, 0,0,0,0, 0,0,0,0) 115 #define CMPI_INST ENCW(0,0,0,0, 1,1,0,0, 0,0,0,0, 0,0,0,0) 116 #define EORI_INST ENCW(0,0,0,0, 1,0,1,0, 0,0,0,0, 0,0,0,0) 117 #define MOVES_INST ENCW(0,0,0,0, 1,1,1,0, 0,0,0,0, 0,0,0,0) 118 #define ORI_INST ENCW(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0) 119 #define SUBI_INST ENCW(0,0,0,0, 0,1,0,0, 0,0,0,0, 0,0,0,0) 120 121 /* 122 * Group misc. (0100) 123 */ 124 #define BGND_MASK 0xffff 125 #define ILLEGAL_MASK 0xffff 126 #define MOVEFRC_MASK 0xffff 127 #define MOVETOC_MASK 0xffff 128 #define NOP_MASK 0xffff 129 #define RESET_MASK 0xffff 130 #define RTD_MASk 0xffff 131 #define RTE_MASK 0xffff 132 #define RTR_MASK 0xffff 133 #define RTS_MASK 0xffff 134 #define STOP_MASK 0xffff 135 #define TRAPV_MASK 0xffff 136 #define BGND_INST ENCW(0,1,0,0, 1,0,1,0, 1,1,1,1, 1,0,1,0) 137 #define ILLEGAL_INST ENCW(0,1,0,0, 1,0,1,0, 1,1,1,1, 1,1,0,0) 138 #define MOVEFRC_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 1,0,1,0) 139 #define MOVETOC_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 1,0,1,1) 140 #define NOP_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,0,0,1) 141 #define RESET_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,0,0,0) 142 #define RTD_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,1,0,0) 143 #define RTE_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,0,1,1) 144 #define RTR_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,1,1,1) 145 #define RTS_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,1,0,1) 146 #define STOP_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,0,1,0) 147 #define TRAPV_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,1, 0,1,1,0) 148 #define SWAP_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0) 149 #define SWAP_INST ENCW(0,1,0,0, 1,0,0,0, 0,1,0,0, 0,0,0,0) 150 151 #define BKPT_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0) 152 #define EXTBW_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0) 153 #define EXTWL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0) 154 #define EXTBL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0) 155 #define LINKW_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0) 156 #define LINKL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0) 157 #define MOVEFRUSP_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0) 158 #define MOVETOUSP_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0) 159 #define UNLK_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0) 160 #undef BKPT_INST 161 #define BKPT_INST ENCW(0,1,0,0, 1,0,0,0, 0,1,0,0, 1,0,0,0) 162 #define EXTBW_INST ENCW(0,1,0,0, 1,0,0,0, 1,0,0,0, 0,0,0,0) 163 #define EXTWL_INST ENCW(0,1,0,0, 1,0,0,0, 1,1,0,0, 0,0,0,0) 164 #define EXTBL_INST ENCW(0,1,0,0, 1,0,0,1, 1,1,0,0, 0,0,0,0) 165 #define LINKW_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,0,1, 0,0,0,0) 166 #define LINKL_INST ENCW(0,1,0,0, 1,0,0,0, 0,0,0,0, 1,0,0,0) 167 #define MOVETOUSP_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,0, 0,0,0,0) 168 #define MOVEFRUSP_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,1,0, 1,0,0,0) 169 #define UNLK_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,0,1, 1,0,0,0) 170 171 #define TRAP_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,1,1, 0,0,0,0) 172 #define TRAP_INST ENCW(0,1,0,0, 1,1,1,0, 0,1,0,0, 0,0,0,0) 173 174 #define DIVSL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 175 #define DIVUL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 176 #define JMP_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 177 #define JSR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 178 #define MOVEFRCCR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 179 #define MOVETOCCR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 180 #define MOVEFRSR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 181 #define MOVETOSR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 182 #define MULSL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 183 #define MULUL_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 184 #define NBCD_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 185 #define PEA_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 186 #define TAS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 187 #define DIVSL_INST ENCW(0,1,0,0, 1,1,0,0, 0,1,0,0, 0,0,0,0) 188 #define DIVUL_INST DIVSL_INST 189 #define JMP_INST ENCW(0,1,0,0, 1,1,1,0, 1,1,0,0, 0,0,0,0) 190 #define JSR_INST ENCW(0,1,0,0, 1,1,1,0, 1,0,0,0, 0,0,0,0) 191 #define MOVEFRCCR_INST ENCW(0,1,0,0, 0,0,1,0, 1,1,0,0, 0,0,0,0) 192 #define MOVETOCCR_INST ENCW(0,1,0,0, 0,1,0,0, 1,1,0,0, 0,0,0,0) 193 #define MOVEFRSR_INST ENCW(0,1,0,0, 0,0,0,0, 1,1,0,0, 0,0,0,0) 194 #define MOVETOSR_INST ENCW(0,1,0,0, 0,1,1,0, 1,1,0,0, 0,0,0,0) 195 #define MULSL_INST ENCW(0,1,0,0, 1,1,0,0, 0,0,0,0, 0,0,0,0) 196 #define MULUL_INST MULSL_INST 197 #define NBCD_INST ENCW(0,1,0,0, 1,0,0,0, 0,0,0,0, 0,0,0,0) 198 #define PEA_INST ENCW(0,1,0,0, 1,0,0,0, 0,1,0,0, 0,0,0,0) 199 #define TAS_INST ENCW(0,1,0,0, 1,0,1,0, 1,1,0,0, 0,0,0,0) 200 201 #define MOVEM_MASK ENCW(1,1,1,1, 1,0,1,1, 1,0,0,0, 0,0,0,0) 202 #define MOVEM_INST ENCW(0,1,0,0, 1,0,0,0, 1,0,0,0, 0,0,0,0) 203 204 #define CLR_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 205 #define NEG_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 206 #define NEGX_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 207 #define NOT_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 208 #define TST_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 209 #define CLR_INST ENCW(0,1,0,0, 0,0,1,0, 0,0,0,0, 0,0,0,0) 210 #define NEG_INST ENCW(0,1,0,0, 0,1,0,0, 0,0,0,0, 0,0,0,0) 211 #define NEGX_INST ENCW(0,1,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0) 212 #define NOT_INST ENCW(0,1,0,0, 0,1,1,0, 0,0,0,0, 0,0,0,0) 213 /* Note: very similatr to MOVEM but bit 9 differentiates. */ 214 #define TST_INST ENCW(0,1,0,0, 1,0,1,0, 0,0,0,0, 0,0,0,0) 215 216 #define LEA_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0) 217 #define LEA_INST ENCW(0,1,0,0, 0,0,0,1, 1,1,0,0, 0,0,0,0) 218 219 #define CHK_MASK ENCW(1,1,1,1, 0,0,0,1, 0,1,0,0, 0,0,0,0) 220 #define CHK_INST ENCW(0,1,0,0, 0,0,0,1, 0,0,0,0, 0,0,0,0) 221 222 /* 223 * Group bitfield/Shift/Rotate. (1110) 224 */ 225 #define BFCHG_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 226 #define BFCLR_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 227 #define BFEXTS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 228 #define BFEXTU_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 229 #define BFFFO_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 230 #define BFINS_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 231 #define BFSET_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 232 #define BFTST_MASK ENCW(1,1,1,1, 1,1,1,1, 1,1,0,0, 0,0,0,0) 233 234 #define BFCHG_INST ENCW(1,1,1,0, 1,0,1,0, 1,1,0,0, 0,0,0,0) 235 #define BFCLR_INST ENCW(1,1,1,0, 1,1,0,0, 1,1,0,0, 0,0,0,0) 236 #define BFEXTS_INST ENCW(1,1,1,0, 1,0,1,1, 1,1,0,0, 0,0,0,0) 237 #define BFEXTU_INST ENCW(1,1,1,0, 1,0,0,1, 1,1,0,0, 0,0,0,0) 238 #define BFFFO_INST ENCW(1,1,1,0, 1,1,0,1, 1,1,0,0, 0,0,0,0) 239 #define BFINS_INST ENCW(1,1,1,0, 1,1,1,1, 1,1,0,0, 0,0,0,0) 240 #define BFSET_INST ENCW(1,1,1,0, 1,1,1,0, 1,1,0,0, 0,0,0,0) 241 #define BFTST_INST ENCW(1,1,1,0, 1,0,0,0, 1,1,0,0, 0,0,0,0) 242 243 #define AS_TYPE 0x0 244 #define LS_TYPE 0x1 245 #define RO_TYPE 0x3 246 #define ROX_TYPE 0x2 247 248 /* 249 * Group DBcc/TRAPcc/ADDQ/SUBQ (0101) 250 */ 251 #define DBcc_MASK ENCW(1,1,1,1, 0,0,0,0, 1,1,1,1, 1,0,0,0) 252 #define TRAPcc_MASK ENCW(1,1,1,1, 0,0,0,0, 1,1,1,1, 1,0,0,0) 253 #define Scc_MASK ENCW(1,1,1,1, 0,0,0,0, 1,1,0,0, 0,0,0,0) 254 #define ADDQ_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,0,0, 0,0,0,0) 255 #define SUBQ_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,0,0, 0,0,0,0) 256 #define DBcc_INST ENCW(0,1,0,1, 0,0,0,0, 1,1,0,0, 1,0,0,0) 257 #define TRAPcc_INST ENCW(0,1,0,1, 0,0,0,0, 1,1,1,1, 1,0,0,0) 258 #define Scc_INST ENCW(0,1,0,1, 0,0,0,0, 1,1,0,0, 0,0,0,0) 259 #define ADDQ_INST ENCW(0,1,0,1, 0,0,0,0, 0,0,0,0, 0,0,0,0) 260 #define SUBQ_INST ENCW(0,1,0,1, 0,0,0,1, 0,0,0,0, 0,0,0,0) 261 262 /* 263 * Group ADD/ADDX (1101) 264 */ 265 #define ADDX_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,1,1, 0,0,0,0) 266 #define ADDX_INST ENCW(1,1,0,1, 0,0,0,1, 0,0,0,0, 0,0,0,0) 267 #define ADD_MASK ENCW(1,1,1,1, 0,0,0,0, 0,0,0,0, 0,0,0,0) 268 #define ADD_INST ENCW(1,1,0,1, 0,0,0,0, 0,0,0,0, 0,0,0,0) 269 270 /* 271 * Group SUB/SUBX (1001) 272 */ 273 #define SUBX_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,1,1, 0,0,0,0) 274 #define SUBX_INST ENCW(1,0,0,1, 0,0,0,1, 0,0,0,0, 0,0,0,0) 275 #define SUB_MASK ENCW(1,1,1,1, 0,0,0,0, 0,0,0,0, 0,0,0,0) 276 #define SUB_INST ENCW(1,0,0,1, 0,0,0,0, 0,0,0,0, 0,0,0,0) 277 278 /* 279 * Group CMP/CMPA/EOR (1011) 280 */ 281 #define CMPA_MASK ENCW(1,1,1,1, 0,0,0,0, 1,1,0,0, 0,0,0,0) 282 #define CMPA_INST ENCW(1,0,1,1, 0,0,0,0, 1,1,0,0, 0,0,0,0) 283 284 #define CMP_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,0,0, 0,0,0,0) 285 #define CMP_INST ENCW(1,0,1,1, 0,0,0,0, 0,0,0,0, 0,0,0,0) 286 287 #define EOR_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,0,0, 0,0,0,0) 288 #define EOR_INST ENCW(1,0,1,1, 0,0,0,1, 0,0,0,0, 0,0,0,0) 289 290 /* 291 * Group branch. (0110) 292 */ 293 #define BRA_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 294 #define BSR_MASK ENCW(1,1,1,1, 1,1,1,1, 0,0,0,0, 0,0,0,0) 295 #define Bcc_MASK ENCW(1,1,1,1, 0,0,0,0, 0,0,0,0, 0,0,0,0) 296 #define BRA_INST ENCW(0,1,1,0, 0,0,0,0, 0,0,0,0, 0,0,0,0) 297 #define BSR_INST ENCW(0,1,1,0, 0,0,0,1, 0,0,0,0, 0,0,0,0) 298 #define Bcc_INST ENCW(0,1,1,0, 0,0,0,0, 0,0,0,0, 0,0,0,0) 299 300 301 /* 302 * Group SBCD/DIVx/OR (1000) 303 */ 304 305 #define UNPKA_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,1,1, 1,0,0,0) 306 #define UNPKD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,1,1, 1,0,0,0) 307 #define UNPKA_INST ENCW(1,0,0,0, 0,0,0,1, 1,0,0,0, 1,0,0,0) 308 #define UNPKD_INST ENCW(1,0,0,0, 0,0,0,1, 1,0,0,0, 0,0,0,0) 309 #define SBCDA_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,1,1, 1,0,0,0) 310 #define SBCDD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,1,1, 1,0,0,0) 311 #define SBCDA_INST ENCW(1,0,0,0, 0,0,0,1, 0,0,0,0, 1,1,1,1) 312 #define SBCDD_INST ENCW(1,0,0,0, 0,0,0,1, 0,0,0,0, 0,1,1,1) 313 314 #define DIVSW_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0) 315 #define DIVUW_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0) 316 #define DIVSW_INST ENCW(1,0,0,0, 0,0,0,1, 1,1,0,0, 0,0,0,0) 317 #define DIVUW_INST ENCW(1,0,0,0, 0,0,0,0, 1,1,0,0, 0,0,0,0) 318 319 #define OR_MASK ENCW(1,1,1,1, 0,0,0,0, 0,0,0,0, 0,0,0,0) 320 #define OR_INST ENCW(1,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0) 321 322 /* 323 * Group AND/MUL/ABCD/EXG (1100) 324 */ 325 #define ABCDA_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,1,1, 1,0,0,0) 326 #define ABCDD_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,1,1, 1,0,0,0) 327 #define ABCDA_INST ENCW(1,1,0,0, 0,0,0,1, 0,0,0,0, 1,0,0,0) 328 #define ABCDD_INST ENCW(1,1,0,0, 0,0,0,1, 0,0,0,0, 0,0,0,0) 329 330 #define MULSW_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0) 331 #define MULUW_MASK ENCW(1,1,1,1, 0,0,0,1, 1,1,0,0, 0,0,0,0) 332 #define MULSW_INST ENCW(1,1,0,0, 0,0,0,1, 1,1,0,0, 0,0,0,0) 333 #define MULUW_INST ENCW(1,1,0,0, 0,0,0,0, 1,1,0,0, 0,0,0,0) 334 335 #define EXG_MASK ENCW(1,1,1,1, 0,0,0,1, 0,0,1,1, 0,0,0,0) 336 #define EXG_INST ENCW(1,1,0,0, 0,0,0,1, 0,0,0,0, 0,0,0,0) 337 338 #define AND_MASK ENCW(1,1,1,1, 0,0,0,0, 0,0,0,0, 0,0,0,0) 339 #define AND_INST ENCW(1,1,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0) 340 341 #define ENCFT(b5,b4,b3,b2,b1,b0) ENCB(0,0,b5,b4,b3,b2,b1,b0) 342 343 #define FABS ENCFT(0,1,1,0,0,0) 344 #define FACOS ENCFT(0,1,1,1,0,0) 345 #define FADD ENCFT(1,0,0,0,1,0) 346 #define FASIN ENCFT(0,0,1,1,0,0) 347 #define FATAN ENCFT(0,0,1,0,1,0) 348 #define FATANH ENCFT(0,0,1,1,0,1) 349 #define FCMP ENCFT(1,1,1,0,0,0) 350 #define FCOS ENCFT(0,1,1,1,0,1) 351 #define FCOSH ENCFT(0,1,1,0,0,1) 352 #define FDIV ENCFT(1,0,0,0,0,0) 353 #define FETOX ENCFT(0,1,0,0,0,0) 354 #define FGETEXP ENCFT(0,1,1,1,1,0) 355 #define FGETMAN ENCFT(0,1,1,1,1,1) 356 #define FINT ENCFT(0,0,0,0,0,1) 357 #define FINTRZ ENCFT(0,0,0,0,1,1) 358 #define FLOG10 ENCFT(0,1,0,1,0,1) 359 #define FLOG2 ENCFT(0,1,0,1,1,0) 360 #define FLOGN ENCFT(0,1,0,1,0,0) 361 #define FLOGNP1 ENCFT(0,0,0,1,1,0) 362 #define FMOD ENCFT(1,0,0,0,0,1) 363 #define FMOVE ENCFT(0,0,0,0,0,0) 364 #define FMUL ENCFT(1,0,0,0,1,1) 365 #define FNEG ENCFT(0,1,1,0,1,0) 366 #define FREM ENCFT(1,0,0,1,0,1) 367 #undef FSCALE 368 #define FSCALE ENCFT(1,0,0,1,1,0) 369 #define FSGLDIV ENCFT(1,0,0,1,0,0) 370 #define FSGLMUL ENCFT(1,0,0,1,1,1) 371 #define FSIN ENCFT(0,0,1,1,1,0) 372 #define FSINH ENCFT(0,0,0,0,1,0) 373 #define FSQRT ENCFT(0,0,0,1,0,0) 374 #define FSUB ENCFT(1,0,1,0,0,0) 375 #define FTAN ENCFT(0,0,1,1,1,1) 376 #define FTANH ENCFT(0,0,1,0,0,1) 377 #define FTENTOX ENCFT(0,1,0,0,1,0) 378 #define FTST ENCFT(1,1,1,0,1,0) 379 #define FTWOTOX ENCFT(0,1,0,0,0,1) 380 381 enum getmod_flag { GETMOD_BEFORE = -1, GETMOD_AFTER = -2 }; 382 383 enum opcode_flags { 384 CPU_000 = 0x1, CPU_010 = 0x2, CPU_020 = 0x4, CPU_030 = 0x8, 385 CPU_040 = 0x10, FPU_881 = 0x40, FPU_882 = 0x80, FPU_040 = 0x100, 386 MMU_851 = 0x400, MMU_030 = 0x800, MMU_040 = 0x1000, 387 388 CPU_ANY = CPU_000 | CPU_010 | CPU_020 | CPU_030 | CPU_040, 389 FPU_ANY = FPU_881 | FPU_882 | FPU_040, 390 MMU_ANY = MMU_851 | MMU_030 | MMU_040, 391 CPU_020UP = CPU_020 | CPU_030 | CPU_040, 392 }; 393 394 enum mod_types { 395 DR_DIR = 0, 396 AR_DIR, AR_IND, AR_INC, AR_DEC, 397 AR_DIS, AR_IDX, MOD_SPECIAL 398 }; 399 400 enum sizes { SIZE_BYTE = sizeof(char), SIZE_WORD = sizeof(short), 401 SIZE_LONG = sizeof(long), SIZE_SINGLE = 5, SIZE_QUAD = 6, 402 SIZE_DOUBLE = SIZE_QUAD, SIZE_EXTENDED = 7, SIZE_PACKED = 8 }; 403 404 struct dis_buffer { 405 short *val; /* pointer to memory. */ 406 char *dasm; /* actual dasm. */ 407 char *casm; /* current position in dasm. */ 408 char *info; /* extra info. */ 409 char *cinfo; /* current position in info. */ 410 int used; /* length used. */ 411 int mit; /* use mit sytanx. */ 412 }; 413 typedef struct dis_buffer dis_buffer_t; 414 415 #define ISBITSET(val,b) ((val) & (1 << (b))) 416 #define BITFIELD_MASK(sb,eb) (((1 << ((sb) + 1))-1) & (~((1 << (eb))-1))) 417 #define BITFIELD(val,sb,eb) ((BITFIELD_MASK(sb,eb) & (val)) >> (eb)) 418 #define OPCODE_MAP(x) (BITFIELD(x,15,12)) 419 #ifdef __STDC__ 420 #define IS_INST(inst,val) ((inst ## _MASK & (val)) == inst ## _INST) 421 #else 422 #define IS_INST(inst,val) ((inst/**/_MASK & (val)) == inst/**/_INST) 423 #endif 424 #define PRINT_FPREG(dbuf, reg) addstr(dbuf, fpregs[reg]) 425 #define PRINT_DREG(dbuf, reg) addstr(dbuf, dregs[reg]) 426 #define PRINT_AREG(dbuf, reg) addstr(dbuf, aregs[reg]) 427
Indexes created Tue Sep 30 20:09:53 GMT 2025