| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| a2.s | 26 FP = P0;
28 R0 = [ FP + 0 ]; DBGA ( R0.L , 50 );
29 R0 = [ FP + 4 ]; DBGA ( R0.L , 51 );
30 R0 = [ FP + 8 ]; DBGA ( R0.L , 52 );
31 R0 = [ FP + 12 ]; DBGA ( R0.L , 53 );
32 R0 = [ FP + 16 ]; DBGA ( R0.L , 54 );
33 R0 = [ FP + 20 ]; DBGA ( R0.L , 55 );
34 R0 = [ FP + 24 ]; DBGA ( R0.L , 56 );
35 R0 = [ FP + 28 ]; DBGA ( R0.L , 57 );
36 R0 = [ FP + 32 ]; DBGA ( R0.L , 58 )
[all...] |
| a3.s | 108 FP = P1;
110 R0 = W [ FP + -2 ] (Z); DBGA ( R0.L , 49 );
111 R0 = W [ FP + -4 ] (Z); DBGA ( R0.L , 48 );
112 R0 = W [ FP + -6 ] (Z); DBGA ( R0.L , 47 );
113 R0 = W [ FP + -8 ] (Z); DBGA ( R0.L , 46 );
114 R0 = W [ FP + -10 ] (Z); DBGA ( R0.L , 45 );
115 R0 = W [ FP + -12 ] (Z); DBGA ( R0.L , 44 );
116 R0 = W [ FP + -14 ] (Z); DBGA ( R0.L , 43 );
117 R0 = W [ FP + -16 ] (Z); DBGA ( R0.L , 42 );
118 R0 = W [ FP + -18 ] (Z); DBGA ( R0.L , 41 )
[all...] |
| c_progctrl_call_pr.s | 12 FP = SP;
|
| c_regmv_dr_pr.s | 22 FP = R0;
27 CHECKREG fp, 0x20001001;
33 FP = R1;
38 CHECKREG fp, 0x20021003;
44 FP = R2;
49 CHECKREG fp, 0x20041005;
55 FP = R3;
60 CHECKREG fp, 0x20061007;
66 FP = R4;
71 CHECKREG fp, 0x20081009
[all...] |
| c_regmv_pr_pr.s | 13 imm32 fp, 0x200e100f;
19 imm32 fp, 0x200e100f;
24 FP = P1;
29 CHECKREG fp, 0x20021003;
35 imm32 fp, 0x200e100f;
40 FP = P2;
45 CHECKREG fp, 0x20041005;
51 imm32 fp, 0x200e100f;
56 FP = P4;
61 CHECKREG fp, 0x20081009
[all...] |
| c_comp3op_pr_plus_pr_sh1.s | 14 imm32 fp, 0x12341678;
21 FP = P1 + FP;
28 CHECKREG fp, 0xAF357045;
36 imm32 fp, 0x12345628;
43 FP = P2 + ( FP << 1 );
50 CHECKREG fp, 0x27D27AD4;
58 imm32 fp, 0x12345673;
65 FP = P3 + ( FP << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 14 imm32 fp, 0x12341678;
21 FP = P1 + FP;
28 CHECKREG fp, 0xC28BAC23;
36 imm32 fp, 0x12345628;
43 FP = P2 + ( FP << 2 );
50 CHECKREG fp, 0xF92C5B7C;
58 imm32 fp, 0x12345673;
65 FP = P3 + ( FP << 2 )
[all...] |
| c_ldimmhalf_lz_pr.s | 16 FP = 0x000d (Z);
23 CHECKREG fp, 0x0000000d;
31 FP = 0x00d0 (Z);
39 CHECKREG fp, 0x000000d0;
47 FP = 0x0d00 (Z);
54 CHECKREG fp, 0x00000d00;
62 FP = 0xd000 (Z);
69 CHECKREG fp, 0x0000d000;
|
| c_ldimmhalf_lzhi_pr.s | 23 FP = 0x000d (Z);
24 FP.H = 0x000c;
32 CHECKREG fp, 0x000c000d;
45 FP = 0x00d0 (Z);
46 FP.H = 0x00c0;
55 CHECKREG fp, 0x00c000d0;
68 FP = 0x0d00 (Z);
69 FP.H = 0x0c00;
77 CHECKREG fp, 0x0c000d00;
90 FP = 0xd000 (Z)
[all...] |
| c_ptr2op_pr_sft_2_1.s | 14 imm32 fp, 0x206e109f;
21 FP = P1 >> 1;
28 CHECKREG fp, 0x61242406;
36 imm32 fp, 0x200e10bf;
43 FP = P2;
50 CHECKREG fp, 0x26041005;
58 imm32 fp, 0x200e100f;
65 FP = P3 << 2;
72 CHECKREG fp, 0x20061004;
80 imm32 fp, 0x900e104f
[all...] |
| c_pushpopmultiple_preg.s | 8 FP = SP;
|
| stk5.s | 7 FP = SP;
16 R5 = [ FP + 8 ];
18 R5 = [ FP + 12 ];
|
| c_compi2opp_pr_eq_i7_n.s | 15 FP = -7;
23 CHECKREG fp, -7;
32 FP = -15;
40 CHECKREG fp, -15;
49 FP = -23;
57 CHECKREG fp, -23;
66 FP = -31;
74 CHECKREG fp, -31;
83 FP = -39;
91 CHECKREG fp, -39
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| a2.s | 26 FP = P0;
28 R0 = [ FP + 0 ]; DBGA ( R0.L , 50 );
29 R0 = [ FP + 4 ]; DBGA ( R0.L , 51 );
30 R0 = [ FP + 8 ]; DBGA ( R0.L , 52 );
31 R0 = [ FP + 12 ]; DBGA ( R0.L , 53 );
32 R0 = [ FP + 16 ]; DBGA ( R0.L , 54 );
33 R0 = [ FP + 20 ]; DBGA ( R0.L , 55 );
34 R0 = [ FP + 24 ]; DBGA ( R0.L , 56 );
35 R0 = [ FP + 28 ]; DBGA ( R0.L , 57 );
36 R0 = [ FP + 32 ]; DBGA ( R0.L , 58 )
[all...] |
| a3.s | 108 FP = P1;
110 R0 = W [ FP + -2 ] (Z); DBGA ( R0.L , 49 );
111 R0 = W [ FP + -4 ] (Z); DBGA ( R0.L , 48 );
112 R0 = W [ FP + -6 ] (Z); DBGA ( R0.L , 47 );
113 R0 = W [ FP + -8 ] (Z); DBGA ( R0.L , 46 );
114 R0 = W [ FP + -10 ] (Z); DBGA ( R0.L , 45 );
115 R0 = W [ FP + -12 ] (Z); DBGA ( R0.L , 44 );
116 R0 = W [ FP + -14 ] (Z); DBGA ( R0.L , 43 );
117 R0 = W [ FP + -16 ] (Z); DBGA ( R0.L , 42 );
118 R0 = W [ FP + -18 ] (Z); DBGA ( R0.L , 41 )
[all...] |
| c_progctrl_call_pr.s | 12 FP = SP;
|
| c_regmv_dr_pr.s | 22 FP = R0;
27 CHECKREG fp, 0x20001001;
33 FP = R1;
38 CHECKREG fp, 0x20021003;
44 FP = R2;
49 CHECKREG fp, 0x20041005;
55 FP = R3;
60 CHECKREG fp, 0x20061007;
66 FP = R4;
71 CHECKREG fp, 0x20081009
[all...] |
| c_regmv_pr_pr.s | 13 imm32 fp, 0x200e100f;
19 imm32 fp, 0x200e100f;
24 FP = P1;
29 CHECKREG fp, 0x20021003;
35 imm32 fp, 0x200e100f;
40 FP = P2;
45 CHECKREG fp, 0x20041005;
51 imm32 fp, 0x200e100f;
56 FP = P4;
61 CHECKREG fp, 0x20081009
[all...] |
| c_comp3op_pr_plus_pr_sh1.s | 14 imm32 fp, 0x12341678;
21 FP = P1 + FP;
28 CHECKREG fp, 0xAF357045;
36 imm32 fp, 0x12345628;
43 FP = P2 + ( FP << 1 );
50 CHECKREG fp, 0x27D27AD4;
58 imm32 fp, 0x12345673;
65 FP = P3 + ( FP << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 14 imm32 fp, 0x12341678;
21 FP = P1 + FP;
28 CHECKREG fp, 0xC28BAC23;
36 imm32 fp, 0x12345628;
43 FP = P2 + ( FP << 2 );
50 CHECKREG fp, 0xF92C5B7C;
58 imm32 fp, 0x12345673;
65 FP = P3 + ( FP << 2 )
[all...] |
| c_ldimmhalf_lz_pr.s | 16 FP = 0x000d (Z);
23 CHECKREG fp, 0x0000000d;
31 FP = 0x00d0 (Z);
39 CHECKREG fp, 0x000000d0;
47 FP = 0x0d00 (Z);
54 CHECKREG fp, 0x00000d00;
62 FP = 0xd000 (Z);
69 CHECKREG fp, 0x0000d000;
|
| c_ldimmhalf_lzhi_pr.s | 23 FP = 0x000d (Z);
24 FP.H = 0x000c;
32 CHECKREG fp, 0x000c000d;
45 FP = 0x00d0 (Z);
46 FP.H = 0x00c0;
55 CHECKREG fp, 0x00c000d0;
68 FP = 0x0d00 (Z);
69 FP.H = 0x0c00;
77 CHECKREG fp, 0x0c000d00;
90 FP = 0xd000 (Z)
[all...] |
| c_ptr2op_pr_sft_2_1.s | 14 imm32 fp, 0x206e109f;
21 FP = P1 >> 1;
28 CHECKREG fp, 0x61242406;
36 imm32 fp, 0x200e10bf;
43 FP = P2;
50 CHECKREG fp, 0x26041005;
58 imm32 fp, 0x200e100f;
65 FP = P3 << 2;
72 CHECKREG fp, 0x20061004;
80 imm32 fp, 0x900e104f
[all...] |
| c_pushpopmultiple_preg.s | 8 FP = SP;
|
| stk5.s | 7 FP = SP;
16 R5 = [ FP + 8 ];
18 R5 = [ FP + 12 ];
|
