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    Searched defs:FSL (Results 1 - 4 of 4) sorted by relevancy

  /src/external/gpl3/binutils/dist/opcodes/
ppc-opc.c 3860 /* Xilinx FSL related masks and macros */
3861 #define FSL FCRT + 1
3866 #define URT FSL + 1
5493 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5516 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5528 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5530 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5570 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
5593 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
5652 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
ppc-opc.c 3859 /* Xilinx FSL related masks and macros */
3860 #define FSL FCRT + 1
3865 #define URT FSL + 1
5465 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5488 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5500 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5502 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5542 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
5565 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
5624 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
    [all...]
  /src/external/gpl3/gdb/dist/opcodes/
ppc-opc.c 3781 /* Xilinx FSL related masks and macros */
3782 #define FSL FCRT + 1
3787 #define URT FSL + 1
5346 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5369 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5381 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5383 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5423 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
5446 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
5505 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
ppc-opc.c 3781 /* Xilinx FSL related masks and macros */
3782 #define FSL FCRT + 1
3787 #define URT FSL + 1
5346 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5369 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5381 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5383 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
5423 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
5446 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
5505 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
    [all...]

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