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    Searched defs:FalseReg (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CmovConversion.cpp 715 Register FalseReg =
719 auto FRIt = FalseBBRegRewriteTable.find(FalseReg);
722 FalseReg = FRIt->second;
724 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 788 auto FalseReg = MIB.getReg(3);
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
795 .addUse(FalseReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyFastISel.cpp 920 unsigned FalseReg = getRegForValue(Select->getFalseValue());
921 if (FalseReg == 0)
925 std::swap(TrueReg, FalseReg);
964 .addReg(FalseReg)
WebAssemblyISelLowering.cpp 409 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg;
414 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
447 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg);
451 .addReg(FalseReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 7133 Register FalseReg = MI->getOperand(2).getReg();
7139 std::swap(TrueReg, FalseReg);
7144 if (RegRewriteTable.find(FalseReg) != RegRewriteTable.end())
7145 FalseReg = RegRewriteTable[FalseReg].second;
7150 .addReg(FalseReg).addMBB(FalseMBB);
7153 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg);
7238 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]

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