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    Searched defs:FalseVal (Results 1 - 20 of 20) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/CodeView/
RecordSerialization.cpp 38 bool FalseVal = false;
82 Num = APSInt(APInt(32, N, FalseVal), true);
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
IVDescriptors.cpp 569 Value *FalseVal = SI->getFalseValue();
572 if ((isa<PHINode>(*TrueVal) && isa<PHINode>(*FalseVal)) ||
573 (!isa<PHINode>(*TrueVal) && !isa<PHINode>(*FalseVal)))
577 isa<PHINode>(*TrueVal) ? dyn_cast<Instruction>(FalseVal)
InlineCost.cpp 1915 Value *FalseVal = SI.getFalseValue();
1920 Constant *FalseC = dyn_cast<Constant>(FalseVal);
1922 FalseC = SimplifiedValues.lookup(FalseVal);
1939 ConstantOffsetPtrs.lookup(FalseVal);
1954 : (CondC->isNullValue()) ? FalseVal : nullptr;
  /src/external/apache2/llvm/dist/llvm/lib/TableGen/
TGLexer.h 61 TrueVal, FalseVal,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 1432 SDValue FalseVal =
1436 std::swap(TrueVal, FalseVal);
1438 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineShifts.cpp 512 Value *FalseVal = SI->getFalseValue();
514 canEvaluateShifted(FalseVal, NumBits, IsLeftShift, IC, SI);
850 Value *FalseVal;
852 m_Value(FalseVal)))) {
854 if (!isa<Constant>(FalseVal) && TBO->getOperand(0) == FalseVal &&
861 Builder.CreateBinOp(I.getOpcode(), FalseVal, Op1);
InstCombineSelect.cpp 432 Value *FalseVal) {
436 if (TVI->hasOneUse() && !isa<Constant>(FalseVal)) {
439 if ((SFO & 1) && FalseVal == TVI->getOperand(0)) {
441 } else if ((SFO & 2) && FalseVal == TVI->getOperand(1)) {
458 FalseVal, NewSel);
467 if (auto *FVI = dyn_cast<BinaryOperator>(FalseVal)) {
549 Value *FalseVal,
567 // Canonicalize so that ashr is in FalseVal.
569 std::swap(TrueVal, FalseVal);
572 match(FalseVal, m_AShr(m_Specific(X), m_Specific(Y))) &
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
GVN.cpp 2361 Value *FalseVal = ConstantInt::getFalse(FalseSucc->getContext());
2363 Changed |= propagateEquality(BranchCond, FalseVal, FalseE, true);
InductiveRangeCheckElimination.cpp 436 Metadata *FalseVal =
440 {MDString::get(Context, "llvm.loop.vectorize.enable"), FalseVal});
445 {MDString::get(Context, "llvm.loop.distribute.enable"), FalseVal});
JumpThreading.cpp 955 Constant *FalseVal = getKnownConstant(SI->getFalseValue(), Preference);
957 if ((TrueVal || FalseVal) &&
977 if (Constant *Val = KnownCond ? TrueVal : FalseVal)
2852 /// %s = select %p, trueval, falseval
2859 /// %s = select %c, trueval, falseval
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
PatternMatch.h 1789 auto *FalseVal = SI->getFalseValue();
1792 if ((TrueVal != LHS || FalseVal != RHS) &&
1793 (TrueVal != RHS || FalseVal != LHS))
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeFloatTypes.cpp 2478 SDValue FalseVal = GetPromotedFloat(N->getOperand(2));
2481 N->getOperand(0), TrueVal, FalseVal);
2488 SDValue FalseVal = GetPromotedFloat(N->getOperand(3));
2492 N->getOperand(1), TrueVal, FalseVal, N->getOperand(4));
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 1986 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1993 SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
2046 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2053 SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 2477 SDValue FalseVal = Op.getOperand(3);
2502 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
  /src/external/apache2/llvm/dist/llvm/lib/Bitcode/Reader/
BitcodeReader.cpp 4280 Value *TrueVal, *FalseVal, *Cond;
4282 popValue(Record, OpNum, NextValueNo, TrueVal->getType(), FalseVal) ||
4286 I = SelectInst::Create(Cond, TrueVal, FalseVal);
4295 Value *TrueVal, *FalseVal, *Cond;
4297 popValue(Record, OpNum, NextValueNo, TrueVal->getType(), FalseVal) ||
4313 I = SelectInst::Create(Cond, TrueVal, FalseVal);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 6504 auto *FalseVal = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(1));
6505 if (!FalseVal)
6507 if (CompareRHS->getZExtValue() == FalseVal->getZExtValue())
6631 auto *FalseVal = dyn_cast<ConstantSDNode>(Select->getOperand(1));
6632 if (!TrueVal || !FalseVal)
6634 if (TrueVal->getZExtValue() != 0 && FalseVal->getZExtValue() == 0)
6636 else if (TrueVal->getZExtValue() == 0 && FalseVal->getZExtValue() != 0)
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
SimplifyCFG.cpp 2845 Value *FalseVal = PN->getIncomingValue(PN->getIncomingBlock(0) == IfTrue);
2847 Value *Sel = Builder.CreateSelect(IfCond, TrueVal, FalseVal, "", InsertPt);
4011 ConstantInt *FalseVal = dyn_cast<ConstantInt>(Select->getFalseValue());
4012 if (!TrueVal || !FalseVal)
4018 BasicBlock *FalseBB = SI->findCaseValue(FalseVal)->getCaseSuccessor();
4030 (uint32_t)Weights[SI->findCaseValue(FalseVal)->getSuccessorIndex()];
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 2690 const APInt &FalseVal = cast<ConstantSDNode>(FalseV)->getAPIntValue();
2691 if (TrueVal - 1 == FalseVal)
2693 if (TrueVal + 1 == FalseVal)
5443 SDValue FalseVal = Slct.getOperand(4);
5447 NonConstantVal = FalseVal;
5448 } else if (isZeroOrAllOnes(FalseVal, AllOnes)) {
5456 FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
5459 std::swap(TrueVal, FalseVal);
5463 Slct.getOperand(2), TrueVal, FalseVal});
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 7038 const int64_t FalseVal = CFVal->getSExtValue();
7044 if (TrueVal == ~FalseVal) {
7046 } else if (FalseVal > std::numeric_limits<int64_t>::min() &&
7047 TrueVal == -FalseVal) {
7066 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
7069 if (TrueVal > FalseVal) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 4977 SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4981 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4982 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4988 SDValue FalseLow = FalseVal.getValue(0);
4989 SDValue FalseHigh = FalseVal.getValue(1);
4998 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
5011 // See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
5018 const SDValue TrueVal, const SDValue FalseVal,
5021 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
5023 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
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