1 /* $NetBSD: smu11_driver_if.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef SMU11_DRIVER_IF_H 27 #define SMU11_DRIVER_IF_H 28 29 // *** IMPORTANT *** 30 // SMU TEAM: Always increment the interface version if 31 // any structure is changed in this file 32 // Be aware of that the version should be updated in 33 // smu_v11_0.h, rename is also needed. 34 // #define SMU11_DRIVER_IF_VERSION 0x13 35 36 #define PPTABLE_V20_SMU_VERSION 3 37 38 #define NUM_GFXCLK_DPM_LEVELS 16 39 #define NUM_VCLK_DPM_LEVELS 8 40 #define NUM_DCLK_DPM_LEVELS 8 41 #define NUM_ECLK_DPM_LEVELS 8 42 #define NUM_MP0CLK_DPM_LEVELS 2 43 #define NUM_SOCCLK_DPM_LEVELS 8 44 #define NUM_UCLK_DPM_LEVELS 4 45 #define NUM_FCLK_DPM_LEVELS 8 46 #define NUM_DCEFCLK_DPM_LEVELS 8 47 #define NUM_DISPCLK_DPM_LEVELS 8 48 #define NUM_PIXCLK_DPM_LEVELS 8 49 #define NUM_PHYCLK_DPM_LEVELS 8 50 #define NUM_LINK_LEVELS 2 51 #define NUM_XGMI_LEVELS 2 52 53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 54 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 55 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 56 #define MAX_ECLK_DPM_LEVEL (NUM_ECLK_DPM_LEVELS - 1) 57 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 58 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 59 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 60 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1) 61 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1) 62 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1) 63 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1) 64 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1) 65 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1) 66 #define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1) 67 68 #define PPSMC_GeminiModeNone 0 69 #define PPSMC_GeminiModeMaster 1 70 #define PPSMC_GeminiModeSlave 2 71 72 73 #define FEATURE_DPM_PREFETCHER_BIT 0 74 #define FEATURE_DPM_GFXCLK_BIT 1 75 #define FEATURE_DPM_UCLK_BIT 2 76 #define FEATURE_DPM_SOCCLK_BIT 3 77 #define FEATURE_DPM_UVD_BIT 4 78 #define FEATURE_DPM_VCE_BIT 5 79 #define FEATURE_ULV_BIT 6 80 #define FEATURE_DPM_MP0CLK_BIT 7 81 #define FEATURE_DPM_LINK_BIT 8 82 #define FEATURE_DPM_DCEFCLK_BIT 9 83 #define FEATURE_DS_GFXCLK_BIT 10 84 #define FEATURE_DS_SOCCLK_BIT 11 85 #define FEATURE_DS_LCLK_BIT 12 86 #define FEATURE_PPT_BIT 13 87 #define FEATURE_TDC_BIT 14 88 #define FEATURE_THERMAL_BIT 15 89 #define FEATURE_GFX_PER_CU_CG_BIT 16 90 #define FEATURE_RM_BIT 17 91 #define FEATURE_DS_DCEFCLK_BIT 18 92 #define FEATURE_ACDC_BIT 19 93 #define FEATURE_VR0HOT_BIT 20 94 #define FEATURE_VR1HOT_BIT 21 95 #define FEATURE_FW_CTF_BIT 22 96 #define FEATURE_LED_DISPLAY_BIT 23 97 #define FEATURE_FAN_CONTROL_BIT 24 98 #define FEATURE_GFX_EDC_BIT 25 99 #define FEATURE_GFXOFF_BIT 26 100 #define FEATURE_CG_BIT 27 101 #define FEATURE_DPM_FCLK_BIT 28 102 #define FEATURE_DS_FCLK_BIT 29 103 #define FEATURE_DS_MP1CLK_BIT 30 104 #define FEATURE_DS_MP0CLK_BIT 31 105 #define FEATURE_XGMI_BIT 32 106 #define FEATURE_ECC_BIT 33 107 #define FEATURE_SPARE_34_BIT 34 108 #define FEATURE_SPARE_35_BIT 35 109 #define FEATURE_SPARE_36_BIT 36 110 #define FEATURE_SPARE_37_BIT 37 111 #define FEATURE_SPARE_38_BIT 38 112 #define FEATURE_SPARE_39_BIT 39 113 #define FEATURE_SPARE_40_BIT 40 114 #define FEATURE_SPARE_41_BIT 41 115 #define FEATURE_SPARE_42_BIT 42 116 #define FEATURE_SPARE_43_BIT 43 117 #define FEATURE_SPARE_44_BIT 44 118 #define FEATURE_SPARE_45_BIT 45 119 #define FEATURE_SPARE_46_BIT 46 120 #define FEATURE_SPARE_47_BIT 47 121 #define FEATURE_SPARE_48_BIT 48 122 #define FEATURE_SPARE_49_BIT 49 123 #define FEATURE_SPARE_50_BIT 50 124 #define FEATURE_SPARE_51_BIT 51 125 #define FEATURE_SPARE_52_BIT 52 126 #define FEATURE_SPARE_53_BIT 53 127 #define FEATURE_SPARE_54_BIT 54 128 #define FEATURE_SPARE_55_BIT 55 129 #define FEATURE_SPARE_56_BIT 56 130 #define FEATURE_SPARE_57_BIT 57 131 #define FEATURE_SPARE_58_BIT 58 132 #define FEATURE_SPARE_59_BIT 59 133 #define FEATURE_SPARE_60_BIT 60 134 #define FEATURE_SPARE_61_BIT 61 135 #define FEATURE_SPARE_62_BIT 62 136 #define FEATURE_SPARE_63_BIT 63 137 138 #define NUM_FEATURES 64 139 140 #define FEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT ) 141 #define FEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT ) 142 #define FEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT ) 143 #define FEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT ) 144 #define FEATURE_DPM_UVD_MASK (1 << FEATURE_DPM_UVD_BIT ) 145 #define FEATURE_DPM_VCE_MASK (1 << FEATURE_DPM_VCE_BIT ) 146 #define FEATURE_ULV_MASK (1 << FEATURE_ULV_BIT ) 147 #define FEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT ) 148 #define FEATURE_DPM_LINK_MASK (1 << FEATURE_DPM_LINK_BIT ) 149 #define FEATURE_DPM_DCEFCLK_MASK (1 << FEATURE_DPM_DCEFCLK_BIT ) 150 #define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT ) 151 #define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT ) 152 #define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT ) 153 #define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT ) 154 #define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT ) 155 #define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT ) 156 #define FEATURE_GFX_PER_CU_CG_MASK (1 << FEATURE_GFX_PER_CU_CG_BIT ) 157 #define FEATURE_RM_MASK (1 << FEATURE_RM_BIT ) 158 #define FEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT ) 159 #define FEATURE_ACDC_MASK (1 << FEATURE_ACDC_BIT ) 160 #define FEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT ) 161 #define FEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT ) 162 #define FEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT ) 163 #define FEATURE_LED_DISPLAY_MASK (1 << FEATURE_LED_DISPLAY_BIT ) 164 #define FEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT ) 165 #define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT ) 166 #define FEATURE_GFXOFF_MASK (1 << FEATURE_GFXOFF_BIT ) 167 #define FEATURE_CG_MASK (1 << FEATURE_CG_BIT ) 168 #define FEATURE_DPM_FCLK_MASK (1 << FEATURE_DPM_FCLK_BIT ) 169 #define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT ) 170 #define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT ) 171 #define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT ) 172 #define FEATURE_XGMI_MASK (1ULL << FEATURE_XGMI_BIT ) 173 #define FEATURE_ECC_MASK (1ULL << FEATURE_ECC_BIT ) 174 175 #define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001 176 #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 177 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK 0x00000004 178 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK 0x00000008 179 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK 0x00000010 180 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK 0x00000020 181 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK 0x00000040 182 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK 0x00000080 183 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK 0x00000100 184 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK 0x00000200 185 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK 0x00000400 186 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK 0x00000800 187 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00001000 188 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00002000 189 #define DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH 0x00004000 190 #define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH 0x00008000 191 #define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH 0x00010000 192 #define DPM_OVERRIDE_ENABLE_GFXOFF_FCLK_SWITCH 0x00020000 193 194 #define I2C_CONTROLLER_ENABLED 1 195 #define I2C_CONTROLLER_DISABLED 0 196 197 #define VR_MAPPING_VR_SELECT_MASK 0x01 198 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 199 200 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 201 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 202 203 204 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 205 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 206 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 207 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 208 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 209 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 210 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 211 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 212 213 214 #define THROTTLER_STATUS_PADDING_BIT 0 215 #define THROTTLER_STATUS_TEMP_EDGE_BIT 1 216 #define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2 217 #define THROTTLER_STATUS_TEMP_HBM_BIT 3 218 #define THROTTLER_STATUS_TEMP_VR_GFX_BIT 4 219 #define THROTTLER_STATUS_TEMP_VR_SOC_BIT 5 220 #define THROTTLER_STATUS_TEMP_VR_MEM0_BIT 6 221 #define THROTTLER_STATUS_TEMP_VR_MEM1_BIT 7 222 #define THROTTLER_STATUS_TEMP_LIQUID_BIT 8 223 #define THROTTLER_STATUS_TEMP_PLX_BIT 9 224 #define THROTTLER_STATUS_TEMP_SKIN_BIT 10 225 #define THROTTLER_STATUS_TDC_GFX_BIT 11 226 #define THROTTLER_STATUS_TDC_SOC_BIT 12 227 #define THROTTLER_STATUS_PPT_BIT 13 228 #define THROTTLER_STATUS_FIT_BIT 14 229 #define THROTTLER_STATUS_PPM_BIT 15 230 231 232 #define TABLE_TRANSFER_OK 0x0 233 #define TABLE_TRANSFER_FAILED 0xFF 234 235 236 #define WORKLOAD_DEFAULT_BIT 0 237 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 238 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 239 #define WORKLOAD_PPLIB_VIDEO_BIT 3 240 #define WORKLOAD_PPLIB_VR_BIT 4 241 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 242 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 243 #define WORKLOAD_PPLIB_COUNT 7 244 245 246 #define XGMI_STATE_D0 1 247 #define XGMI_STATE_D3 0 248 249 typedef enum { 250 I2C_CONTROLLER_PORT_0 = 0, 251 I2C_CONTROLLER_PORT_1 = 1, 252 } I2cControllerPort_e; 253 254 typedef enum { 255 I2C_CONTROLLER_NAME_VR_GFX = 0, 256 I2C_CONTROLLER_NAME_VR_SOC, 257 I2C_CONTROLLER_NAME_VR_VDDCI, 258 I2C_CONTROLLER_NAME_VR_HBM, 259 I2C_CONTROLLER_NAME_LIQUID_0, 260 I2C_CONTROLLER_NAME_LIQUID_1, 261 I2C_CONTROLLER_NAME_PLX, 262 I2C_CONTROLLER_NAME_COUNT, 263 } I2cControllerName_e; 264 265 typedef enum { 266 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 267 I2C_CONTROLLER_THROTTLER_VR_GFX, 268 I2C_CONTROLLER_THROTTLER_VR_SOC, 269 I2C_CONTROLLER_THROTTLER_VR_VDDCI, 270 I2C_CONTROLLER_THROTTLER_VR_HBM, 271 I2C_CONTROLLER_THROTTLER_LIQUID_0, 272 I2C_CONTROLLER_THROTTLER_LIQUID_1, 273 I2C_CONTROLLER_THROTTLER_PLX, 274 } I2cControllerThrottler_e; 275 276 typedef enum { 277 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 278 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 279 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 280 I2C_CONTROLLER_PROTOCOL_SPARE_0, 281 I2C_CONTROLLER_PROTOCOL_SPARE_1, 282 I2C_CONTROLLER_PROTOCOL_SPARE_2, 283 } I2cControllerProtocol_e; 284 285 typedef enum { 286 I2C_CONTROLLER_SPEED_SLOW = 0, 287 I2C_CONTROLLER_SPEED_FAST = 1, 288 } I2cControllerSpeed_e; 289 290 typedef struct { 291 uint32_t Enabled; 292 uint32_t SlaveAddress; 293 uint32_t ControllerPort; 294 uint32_t ControllerName; 295 296 uint32_t ThermalThrottler; 297 uint32_t I2cProtocol; 298 uint32_t I2cSpeed; 299 } I2cControllerConfig_t; 300 301 typedef struct { 302 uint32_t a; 303 uint32_t b; 304 uint32_t c; 305 } QuadraticInt_t; 306 307 typedef struct { 308 uint32_t m; 309 uint32_t b; 310 } LinearInt_t; 311 312 typedef struct { 313 uint32_t a; 314 uint32_t b; 315 uint32_t c; 316 } DroopInt_t; 317 318 typedef enum { 319 PPCLK_GFXCLK, 320 PPCLK_VCLK, 321 PPCLK_DCLK, 322 PPCLK_ECLK, 323 PPCLK_SOCCLK, 324 PPCLK_UCLK, 325 PPCLK_DCEFCLK, 326 PPCLK_DISPCLK, 327 PPCLK_PIXCLK, 328 PPCLK_PHYCLK, 329 PPCLK_FCLK, 330 PPCLK_COUNT, 331 } PPCLK_e; 332 333 typedef enum { 334 POWER_SOURCE_AC, 335 POWER_SOURCE_DC, 336 POWER_SOURCE_COUNT, 337 } POWER_SOURCE_e; 338 339 typedef enum { 340 VOLTAGE_MODE_AVFS = 0, 341 VOLTAGE_MODE_AVFS_SS, 342 VOLTAGE_MODE_SS, 343 VOLTAGE_MODE_COUNT, 344 } VOLTAGE_MODE_e; 345 346 347 typedef enum { 348 AVFS_VOLTAGE_GFX = 0, 349 AVFS_VOLTAGE_SOC, 350 AVFS_VOLTAGE_COUNT, 351 } AVFS_VOLTAGE_TYPE_e; 352 353 354 typedef struct { 355 uint8_t VoltageMode; 356 uint8_t SnapToDiscrete; 357 uint8_t NumDiscreteLevels; 358 uint8_t padding; 359 LinearInt_t ConversionToAvfsClk; 360 QuadraticInt_t SsCurve; 361 } DpmDescriptor_t; 362 363 typedef struct { 364 uint32_t Version; 365 366 367 uint32_t FeaturesToRun[2]; 368 369 370 uint16_t SocketPowerLimitAc0; 371 uint16_t SocketPowerLimitAc0Tau; 372 uint16_t SocketPowerLimitAc1; 373 uint16_t SocketPowerLimitAc1Tau; 374 uint16_t SocketPowerLimitAc2; 375 uint16_t SocketPowerLimitAc2Tau; 376 uint16_t SocketPowerLimitAc3; 377 uint16_t SocketPowerLimitAc3Tau; 378 uint16_t SocketPowerLimitDc; 379 uint16_t SocketPowerLimitDcTau; 380 uint16_t TdcLimitSoc; 381 uint16_t TdcLimitSocTau; 382 uint16_t TdcLimitGfx; 383 uint16_t TdcLimitGfxTau; 384 385 uint16_t TedgeLimit; 386 uint16_t ThotspotLimit; 387 uint16_t ThbmLimit; 388 uint16_t Tvr_gfxLimit; 389 uint16_t Tvr_memLimit; 390 uint16_t Tliquid1Limit; 391 uint16_t Tliquid2Limit; 392 uint16_t TplxLimit; 393 uint32_t FitLimit; 394 395 uint16_t PpmPowerLimit; 396 uint16_t PpmTemperatureThreshold; 397 398 uint8_t MemoryOnPackage; 399 uint8_t padding8_limits; 400 uint16_t Tvr_SocLimit; 401 402 uint16_t UlvVoltageOffsetSoc; 403 uint16_t UlvVoltageOffsetGfx; 404 405 uint8_t UlvSmnclkDid; 406 uint8_t UlvMp1clkDid; 407 uint8_t UlvGfxclkBypass; 408 uint8_t Padding234; 409 410 411 uint16_t MinVoltageGfx; 412 uint16_t MinVoltageSoc; 413 uint16_t MaxVoltageGfx; 414 uint16_t MaxVoltageSoc; 415 416 uint16_t LoadLineResistanceGfx; 417 uint16_t LoadLineResistanceSoc; 418 419 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 420 421 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; 422 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; 423 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; 424 uint16_t FreqTableEclk [NUM_ECLK_DPM_LEVELS ]; 425 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; 426 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; 427 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; 428 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; 429 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; 430 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; 431 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; 432 433 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; 434 uint16_t Padding8_Clks; 435 436 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; 437 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; 438 439 440 uint16_t GfxclkFidle; 441 uint16_t GfxclkSlewRate; 442 uint16_t CksEnableFreq; 443 uint16_t Padding789; 444 QuadraticInt_t CksVoltageOffset; 445 uint8_t Padding567[4]; 446 uint16_t GfxclkDsMaxFreq; 447 uint8_t GfxclkSource; 448 uint8_t Padding456; 449 450 uint8_t LowestUclkReservedForUlv; 451 uint8_t Padding8_Uclk[3]; 452 453 454 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; 455 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; 456 uint16_t LclkFreq[NUM_LINK_LEVELS]; 457 458 459 uint16_t EnableTdpm; 460 uint16_t TdpmHighHystTemperature; 461 uint16_t TdpmLowHystTemperature; 462 uint16_t GfxclkFreqHighTempLimit; 463 464 465 uint16_t FanStopTemp; 466 uint16_t FanStartTemp; 467 468 uint16_t FanGainEdge; 469 uint16_t FanGainHotspot; 470 uint16_t FanGainLiquid; 471 uint16_t FanGainVrGfx; 472 uint16_t FanGainVrSoc; 473 uint16_t FanGainPlx; 474 uint16_t FanGainHbm; 475 uint16_t FanPwmMin; 476 uint16_t FanAcousticLimitRpm; 477 uint16_t FanThrottlingRpm; 478 uint16_t FanMaximumRpm; 479 uint16_t FanTargetTemperature; 480 uint16_t FanTargetGfxclk; 481 uint8_t FanZeroRpmEnable; 482 uint8_t FanTachEdgePerRev; 483 484 485 486 int16_t FuzzyFan_ErrorSetDelta; 487 int16_t FuzzyFan_ErrorRateSetDelta; 488 int16_t FuzzyFan_PwmSetDelta; 489 uint16_t FuzzyFan_Reserved; 490 491 492 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 493 uint8_t Padding8_Avfs[2]; 494 495 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; 496 DroopInt_t dBtcGbGfxCksOn; 497 DroopInt_t dBtcGbGfxCksOff; 498 DroopInt_t dBtcGbGfxAfll; 499 DroopInt_t dBtcGbSoc; 500 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; 501 502 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; 503 504 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; 505 506 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 507 uint8_t Padding8_GfxBtc[2]; 508 509 int16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; 510 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; 511 512 513 uint8_t XgmiLinkSpeed [NUM_XGMI_LEVELS]; 514 uint8_t XgmiLinkWidth [NUM_XGMI_LEVELS]; 515 uint16_t XgmiFclkFreq [NUM_XGMI_LEVELS]; 516 uint16_t XgmiUclkFreq [NUM_XGMI_LEVELS]; 517 uint16_t XgmiSocclkFreq [NUM_XGMI_LEVELS]; 518 uint16_t XgmiSocVoltage [NUM_XGMI_LEVELS]; 519 520 uint32_t DebugOverrides; 521 QuadraticInt_t ReservedEquation0; 522 QuadraticInt_t ReservedEquation1; 523 QuadraticInt_t ReservedEquation2; 524 QuadraticInt_t ReservedEquation3; 525 526 uint16_t MinVoltageUlvGfx; 527 uint16_t MinVoltageUlvSoc; 528 529 uint16_t MGpuFanBoostLimitRpm; 530 uint16_t padding16_Fan; 531 532 uint16_t FanGainVrMem0; 533 uint16_t FanGainVrMem1; 534 535 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; 536 537 uint32_t Reserved[11]; 538 539 uint32_t Padding32[3]; 540 541 uint16_t MaxVoltageStepGfx; 542 uint16_t MaxVoltageStepSoc; 543 544 uint8_t VddGfxVrMapping; 545 uint8_t VddSocVrMapping; 546 uint8_t VddMem0VrMapping; 547 uint8_t VddMem1VrMapping; 548 549 uint8_t GfxUlvPhaseSheddingMask; 550 uint8_t SocUlvPhaseSheddingMask; 551 uint8_t ExternalSensorPresent; 552 uint8_t Padding8_V; 553 554 555 uint16_t GfxMaxCurrent; 556 int8_t GfxOffset; 557 uint8_t Padding_TelemetryGfx; 558 559 uint16_t SocMaxCurrent; 560 int8_t SocOffset; 561 uint8_t Padding_TelemetrySoc; 562 563 uint16_t Mem0MaxCurrent; 564 int8_t Mem0Offset; 565 uint8_t Padding_TelemetryMem0; 566 567 uint16_t Mem1MaxCurrent; 568 int8_t Mem1Offset; 569 uint8_t Padding_TelemetryMem1; 570 571 572 uint8_t AcDcGpio; 573 uint8_t AcDcPolarity; 574 uint8_t VR0HotGpio; 575 uint8_t VR0HotPolarity; 576 577 uint8_t VR1HotGpio; 578 uint8_t VR1HotPolarity; 579 uint8_t Padding1; 580 uint8_t Padding2; 581 582 583 584 uint8_t LedPin0; 585 uint8_t LedPin1; 586 uint8_t LedPin2; 587 uint8_t padding8_4; 588 589 590 uint8_t PllGfxclkSpreadEnabled; 591 uint8_t PllGfxclkSpreadPercent; 592 uint16_t PllGfxclkSpreadFreq; 593 594 uint8_t UclkSpreadEnabled; 595 uint8_t UclkSpreadPercent; 596 uint16_t UclkSpreadFreq; 597 598 uint8_t FclkSpreadEnabled; 599 uint8_t FclkSpreadPercent; 600 uint16_t FclkSpreadFreq; 601 602 uint8_t FllGfxclkSpreadEnabled; 603 uint8_t FllGfxclkSpreadPercent; 604 uint16_t FllGfxclkSpreadFreq; 605 606 I2cControllerConfig_t I2cControllers[I2C_CONTROLLER_NAME_COUNT]; 607 608 uint32_t BoardReserved[10]; 609 610 611 uint32_t MmHubPadding[8]; 612 613 } PPTable_t; 614 615 typedef struct { 616 617 uint16_t GfxclkAverageLpfTau; 618 uint16_t SocclkAverageLpfTau; 619 uint16_t UclkAverageLpfTau; 620 uint16_t GfxActivityLpfTau; 621 uint16_t UclkActivityLpfTau; 622 uint16_t SocketPowerLpfTau; 623 624 625 uint32_t MmHubPadding[8]; 626 } DriverSmuConfig_t; 627 628 typedef struct { 629 630 uint16_t GfxclkFmin; 631 uint16_t GfxclkFmax; 632 uint16_t GfxclkFreq1; 633 uint16_t GfxclkVolt1; 634 uint16_t GfxclkFreq2; 635 uint16_t GfxclkVolt2; 636 uint16_t GfxclkFreq3; 637 uint16_t GfxclkVolt3; 638 uint16_t UclkFmax; 639 int16_t OverDrivePct; 640 uint16_t FanMaximumRpm; 641 uint16_t FanMinimumPwm; 642 uint16_t FanTargetTemperature; 643 uint16_t MaxOpTemp; 644 uint16_t FanZeroRpmEnable; 645 uint16_t Padding; 646 647 } OverDriveTable_t; 648 649 typedef struct { 650 uint16_t CurrClock[PPCLK_COUNT]; 651 uint16_t AverageGfxclkFrequency; 652 uint16_t AverageSocclkFrequency; 653 uint16_t AverageUclkFrequency ; 654 uint16_t AverageGfxActivity ; 655 uint16_t AverageUclkActivity ; 656 uint8_t CurrSocVoltageOffset ; 657 uint8_t CurrGfxVoltageOffset ; 658 uint8_t CurrMemVidOffset ; 659 uint8_t Padding8 ; 660 uint16_t CurrSocketPower ; 661 uint16_t TemperatureEdge ; 662 uint16_t TemperatureHotspot ; 663 uint16_t TemperatureHBM ; 664 uint16_t TemperatureVrGfx ; 665 uint16_t TemperatureVrSoc ; 666 uint16_t TemperatureVrMem0 ; 667 uint16_t TemperatureVrMem1 ; 668 uint16_t TemperatureLiquid ; 669 uint16_t TemperaturePlx ; 670 uint32_t ThrottlerStatus ; 671 672 uint8_t LinkDpmLevel; 673 uint16_t AverageSocketPower; 674 uint8_t Padding; 675 676 677 uint32_t MmHubPadding[7]; 678 } SmuMetrics_t; 679 680 typedef struct { 681 uint16_t MinClock; 682 uint16_t MaxClock; 683 uint16_t MinUclk; 684 uint16_t MaxUclk; 685 686 uint8_t WmSetting; 687 uint8_t Padding[3]; 688 } WatermarkRowGeneric_t; 689 690 #define NUM_WM_RANGES 4 691 692 typedef enum { 693 WM_SOCCLK = 0, 694 WM_DCEFCLK, 695 WM_COUNT_PP, 696 } WM_CLOCK_e; 697 698 typedef struct { 699 700 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES]; 701 702 uint32_t MmHubPadding[7]; 703 } Watermarks_t; 704 705 typedef struct { 706 uint16_t avgPsmCount[45]; 707 uint16_t minPsmCount[45]; 708 float avgPsmVoltage[45]; 709 float minPsmVoltage[45]; 710 711 uint16_t avgScsPsmCount; 712 uint16_t minScsPsmCount; 713 float avgScsPsmVoltage; 714 float minScsPsmVoltage; 715 716 717 uint32_t MmHubPadding[6]; 718 } AvfsDebugTable_t; 719 720 typedef struct { 721 uint8_t AvfsVersion; 722 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 723 724 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 725 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 726 727 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 728 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 729 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 730 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 731 732 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; 733 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; 734 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; 735 736 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; 737 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; 738 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; 739 740 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; 741 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; 742 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; 743 744 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; 745 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; 746 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; 747 748 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; 749 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; 750 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; 751 752 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 753 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 754 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 755 756 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; 757 758 759 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; 760 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; 761 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; 762 763 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; 764 765 uint32_t EnabledAvfsModules; 766 767 uint32_t MmHubPadding[7]; 768 } AvfsFuseOverride_t; 769 770 typedef struct { 771 772 uint8_t Gfx_ActiveHystLimit; 773 uint8_t Gfx_IdleHystLimit; 774 uint8_t Gfx_FPS; 775 uint8_t Gfx_MinActiveFreqType; 776 uint8_t Gfx_BoosterFreqType; 777 uint8_t Gfx_UseRlcBusy; 778 uint16_t Gfx_MinActiveFreq; 779 uint16_t Gfx_BoosterFreq; 780 uint16_t Gfx_PD_Data_time_constant; 781 uint32_t Gfx_PD_Data_limit_a; 782 uint32_t Gfx_PD_Data_limit_b; 783 uint32_t Gfx_PD_Data_limit_c; 784 uint32_t Gfx_PD_Data_error_coeff; 785 uint32_t Gfx_PD_Data_error_rate_coeff; 786 787 uint8_t Soc_ActiveHystLimit; 788 uint8_t Soc_IdleHystLimit; 789 uint8_t Soc_FPS; 790 uint8_t Soc_MinActiveFreqType; 791 uint8_t Soc_BoosterFreqType; 792 uint8_t Soc_UseRlcBusy; 793 uint16_t Soc_MinActiveFreq; 794 uint16_t Soc_BoosterFreq; 795 uint16_t Soc_PD_Data_time_constant; 796 uint32_t Soc_PD_Data_limit_a; 797 uint32_t Soc_PD_Data_limit_b; 798 uint32_t Soc_PD_Data_limit_c; 799 uint32_t Soc_PD_Data_error_coeff; 800 uint32_t Soc_PD_Data_error_rate_coeff; 801 802 uint8_t Mem_ActiveHystLimit; 803 uint8_t Mem_IdleHystLimit; 804 uint8_t Mem_FPS; 805 uint8_t Mem_MinActiveFreqType; 806 uint8_t Mem_BoosterFreqType; 807 uint8_t Mem_UseRlcBusy; 808 uint16_t Mem_MinActiveFreq; 809 uint16_t Mem_BoosterFreq; 810 uint16_t Mem_PD_Data_time_constant; 811 uint32_t Mem_PD_Data_limit_a; 812 uint32_t Mem_PD_Data_limit_b; 813 uint32_t Mem_PD_Data_limit_c; 814 uint32_t Mem_PD_Data_error_coeff; 815 uint32_t Mem_PD_Data_error_rate_coeff; 816 817 uint8_t Fclk_ActiveHystLimit; 818 uint8_t Fclk_IdleHystLimit; 819 uint8_t Fclk_FPS; 820 uint8_t Fclk_MinActiveFreqType; 821 uint8_t Fclk_BoosterFreqType; 822 uint8_t Fclk_UseRlcBusy; 823 uint16_t Fclk_MinActiveFreq; 824 uint16_t Fclk_BoosterFreq; 825 uint16_t Fclk_PD_Data_time_constant; 826 uint32_t Fclk_PD_Data_limit_a; 827 uint32_t Fclk_PD_Data_limit_b; 828 uint32_t Fclk_PD_Data_limit_c; 829 uint32_t Fclk_PD_Data_error_coeff; 830 uint32_t Fclk_PD_Data_error_rate_coeff; 831 832 } DpmActivityMonitorCoeffInt_t; 833 834 #define TABLE_PPTABLE 0 835 #define TABLE_WATERMARKS 1 836 #define TABLE_AVFS 2 837 #define TABLE_AVFS_PSM_DEBUG 3 838 #define TABLE_AVFS_FUSE_OVERRIDE 4 839 #define TABLE_PMSTATUSLOG 5 840 #define TABLE_SMU_METRICS 6 841 #define TABLE_DRIVER_SMU_CONFIG 7 842 #define TABLE_ACTIVITY_MONITOR_COEFF 8 843 #define TABLE_OVERDRIVE 9 844 #define TABLE_COUNT 10 845 846 847 #define UCLK_SWITCH_SLOW 0 848 #define UCLK_SWITCH_FAST 1 849 850 851 #define SQ_Enable_MASK 0x1 852 #define SQ_IR_MASK 0x2 853 #define SQ_PCC_MASK 0x4 854 #define SQ_EDC_MASK 0x8 855 856 #define TCP_Enable_MASK 0x100 857 #define TCP_IR_MASK 0x200 858 #define TCP_PCC_MASK 0x400 859 #define TCP_EDC_MASK 0x800 860 861 #define TD_Enable_MASK 0x10000 862 #define TD_IR_MASK 0x20000 863 #define TD_PCC_MASK 0x40000 864 #define TD_EDC_MASK 0x80000 865 866 #define DB_Enable_MASK 0x1000000 867 #define DB_IR_MASK 0x2000000 868 #define DB_PCC_MASK 0x4000000 869 #define DB_EDC_MASK 0x8000000 870 871 #define SQ_Enable_SHIFT 0 872 #define SQ_IR_SHIFT 1 873 #define SQ_PCC_SHIFT 2 874 #define SQ_EDC_SHIFT 3 875 876 #define TCP_Enable_SHIFT 8 877 #define TCP_IR_SHIFT 9 878 #define TCP_PCC_SHIFT 10 879 #define TCP_EDC_SHIFT 11 880 881 #define TD_Enable_SHIFT 16 882 #define TD_IR_SHIFT 17 883 #define TD_PCC_SHIFT 18 884 #define TD_EDC_SHIFT 19 885 886 #define DB_Enable_SHIFT 24 887 #define DB_IR_SHIFT 25 888 #define DB_PCC_SHIFT 26 889 #define DB_EDC_SHIFT 27 890 891 #define REMOVE_FMAX_MARGIN_BIT 0x0 892 #define REMOVE_DCTOL_MARGIN_BIT 0x1 893 #define REMOVE_PLATFORM_MARGIN_BIT 0x2 894 895 #endif 896
Indexes created Sun Sep 21 20:09:37 GMT 2025