| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiRegisterInfo.cpp | 153 Register FrameReg = getFrameRegister(MF);
156 FrameReg = getBaseRegister();
158 FrameReg = Lanai::SP;
194 // Reg = FrameReg OP Reg
199 .addReg(FrameReg)
217 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
235 .addReg(FrameReg)
239 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 97 Register FrameReg;
100 FrameReg = Mips::SP;
104 FrameReg = Mips::S0;
108 FrameReg = MI.getOperand(OpNo+2).getReg();
110 FrameReg = Mips::SP;
131 !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) {
137 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
141 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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| MipsSERegisterInfo.cpp | 178 unsigned FrameReg;
182 FrameReg = ABI.GetStackPtr();
185 FrameReg = ABI.GetBasePtr();
187 FrameReg = getFrameRegister(MF);
189 FrameReg = ABI.GetStackPtr();
191 FrameReg = getFrameRegister(MF);
230 .addReg(FrameReg)
233 FrameReg = Reg;
247 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
250 FrameReg = Reg
[all...] |
| MipsTargetStreamer.h | 199 unsigned FrameReg;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 176 Register FrameReg;
178 Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed();
190 .addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
191 replaceFI(MF, *StMI, *StMI, dl, 0, Offset, FrameReg);
202 .addReg(FrameReg).addImm(0);
203 replaceFI(MF, *LdMI, *LdMI, dl, 1, Offset, FrameReg);
211 replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg);
|
| SparcISelLowering.cpp | 2630 unsigned FrameReg = SP::I6;
2639 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| GCRootLowering.cpp | 296 Register FrameReg; // FIXME: surely GCRoot ought to store the
298 auto FrameOffset = TFI->getFrameIndexReference(MF, RI->Num, FrameReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCRegisterInfo.cpp | 40 unsigned FrameReg, int Offset, int StackSize,
46 unsigned BaseReg = FrameReg;
69 << " for FrameReg=" << printReg(FrameReg, TRI)
77 .addReg(FrameReg)
117 .addReg(FrameReg)
188 Register FrameReg = getFrameRegister(MF);
189 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
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| ARCISelLowering.cpp | 720 Register FrameReg = ARI.getFrameRegister(MF);
721 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVRegisterInfo.cpp | 199 Register FrameReg;
201 getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg);
236 // Modify Offset and FrameReg appropriately
241 .addReg(FrameReg)
247 .addReg(FrameReg)
250 FrameReg = ScratchReg;
257 .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
264 .addReg(FrameReg, getKillRegState(FrameRegIsKill))
276 // 2. Calculate address: FrameReg + result of multiply
279 .addReg(FrameReg, getKillRegState(FrameRegIsKill)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VERegisterInfo.cpp | 138 unsigned FIOperandNum, int Offset, Register FrameReg) {
142 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
157 Register FrameReg;
159 Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed();
170 .addReg(FrameReg)
174 replaceFI(MF, II, *StMI, dl, 0, Offset, FrameReg);
186 .addReg(FrameReg)
189 replaceFI(MF, II, *StMI, dl, 1, Offset, FrameReg);
195 replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg);
|
| VEISelLowering.cpp | 1547 unsigned FrameReg = RegInfo->getFrameRegister(MF);
1549 DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, PtrVT);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 63 unsigned Reg, unsigned FrameReg, int Offset ) {
71 .addReg(FrameReg)
78 .addReg(FrameReg)
84 .addReg(FrameReg)
94 unsigned Reg, unsigned FrameReg,
107 .addReg(FrameReg)
114 .addReg(FrameReg)
120 .addReg(FrameReg)
281 Register FrameReg = getFrameRegister(MF);
285 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/ |
| DbgEntityHistoryCalculator.cpp | 456 Register FrameReg = TRI->getFrameRegister(*MF);
506 else if (MO.getReg() != FrameReg ||
|
| DwarfCompileUnit.cpp | 831 Register FrameReg;
835 TFI->getFrameIndexReference(*Asm->MF, Fragment.FI, FrameReg);
865 *Asm->MF->getSubtarget().getRegisterInfo(), Cursor, FrameReg);
|
| CodeViewDebug.cpp | 1211 Register FrameReg;
1212 StackOffset FrameOffset = TFI->getFrameIndexReference(*Asm->MF, VI.Slot, FrameReg);
1213 uint16_t CVReg = TRI->getCodeViewRegNum(FrameReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86WinCOFFTargetStreamer.cpp | 273 unsigned FrameReg = 0;
321 assert((StackAlign == 0 || FrameReg != 0) &&
325 if (FrameReg) {
326 // CFA is FrameReg + FrameRegOff.
327 FuncOS << CFAVar << ' ' << printFPOReg(MRI, FrameReg) << ' ' << FrameRegOff
422 FSM.FrameReg = Inst.RegOrOffset;
433 if (FSM.FrameReg)
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetFrameLowering.h | 300 /// returned directly, and the base register is returned via FrameReg.
302 Register &FrameReg) const;
306 /// FrameReg. This is generally used for emitting statepoint or EH tables that
312 Register &FrameReg,
315 return getFrameIndexReference(MF, FI, FrameReg);
325 Register FrameReg;
326 return getFrameIndexReference(MF, FI, FrameReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 860 Register FrameReg = getFrameRegister(MF);
862 FrameReg = getX86SubSuperRegister(FrameReg, 32);
863 return FrameReg;
|
| X86FastISel.cpp | 2688 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(*MF);
2689 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
2690 (FrameReg == X86::EBP && VT == MVT::i32)) &&
2698 TII.get(TargetOpcode::COPY), SrcReg).addReg(FrameReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 1120 Register FrameReg;
1122 MF, BaseOffset, false /*isFixed*/, false /*isSVE*/, FrameReg,
1125 Register SrcReg = FrameReg;
1129 emitFrameOffset(MBB, &MI, MI.getDebugLoc(), SrcReg, FrameReg,
|
| AArch64FrameLowering.cpp | 1957 Register &FrameReg) const {
1959 MF, FI, FrameReg,
2003 const MachineFunction &MF, int FI, Register &FrameReg, bool PreferFP,
2009 return resolveFrameOffsetReference(MF, ObjectOffset, isFixed, isSVE, FrameReg,
2015 Register &FrameReg, bool PreferFP, bool ForSimm) const {
2109 FrameReg = RegInfo->getFrameRegister(MF);
2113 FrameReg = RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister()
2125 FrameReg = RegInfo->getFrameRegister(MF);
2131 FrameReg = RegInfo->getBaseRegister();
2135 FrameReg = AArch64::SP
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 780 Register FrameReg;
782 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
789 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
804 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
807 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII, this);
836 (Register::isVirtualRegister(FrameReg) || RegClass->contains(FrameReg)))
838 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
842 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
846 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 559 MCRegister FrameReg = MFI->getFrameOffsetReg();
560 if (FrameReg) {
561 reserveRegisterTuples(Reserved, FrameReg);
562 assert(!isSubRegister(ScratchRSrcReg, FrameReg));
1278 Register FrameReg =
1292 buildSpillLoadStore(SB.MBB, SB.MI, Opc, Index, SB.TmpVGPR, false, FrameReg,
1297 buildSpillLoadStore(SB.MBB, SB.MI, Opc, Index, SB.TmpVGPR, IsKill, FrameReg,
1513 Register FrameReg = FrameInfo.isFixedObjectIndex(Index) && hasBasePointer(*MF)
1574 *MBB, MI, Opc, Index, VData->getReg(), VData->isKill(), FrameReg,
1608 *MBB, MI, Opc, Index, VData->getReg(), VData->isKill(), FrameReg,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 1106 Register FrameReg;
1108 getFrameIndexReference(MF, F->getFrameIdx(), FrameReg).getFixed();
1262 Register &FrameReg) const {
1345 FrameReg = FP;
1347 FrameReg = AP;
1349 FrameReg = SP;
|
