1 /* $NetBSD: gemreg.h,v 1.16 2021/08/17 22:00:31 andvar Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _IF_GEMREG_H 33 #define _IF_GEMREG_H 34 35 /* 36 * Register definitions for Sun GEM Gigabit Ethernet 37 * See `GEM Gigabit Ethernet ASIC Specification' 38 * http://www.sun.com/processors/manuals/ge.pdf 39 * and `Sbus GEM Specification' 40 * http://mediacast.sun.com/users/Barton808/media/gem_sbus-1.pdf 41 * section 3.1.3 GEM Register Space 42 */ 43 44 /* 45 * Global Resources 46 * Section 3.1.4.1 47 * 48 * First bank: this registers live at the start of the PCI 49 * mapping, and at the start of the second bank of the SBus 50 * version. 51 */ 52 #define GEM_SEB_STATE 0x0000 /* SEB State (R/O) */ 53 #define GEM_CONFIG 0x0004 /* Configuration */ 54 #define GEM_STATUS 0x000c /* Status */ 55 /* Note: Reading the status register auto-clears bits 0-6 */ 56 #define GEM_INTMASK 0x0010 /* Interrupt Mask */ 57 #define GEM_INTACK 0x0014 /* Interrupt Acknowledge (W/O) */ 58 #define GEM_STATUS_ALIAS 0x001c /* Status Alias */ 59 /* This is the same as GEM_STATUS but reading it does not auto-clear bits. */ 60 61 /* 62 * Second bank: this registers live at offset 0x1000 of the PCI 63 * mapping, and at the start of the first bank of the SBus 64 * version. 65 */ 66 #define GEM_PCI_BANK2_OFFSET 0x1000 67 #define GEM_PCI_BANK2_SIZE 0x14 68 #define GEM_ERROR_STATUS 0x0000 /* PCI Error Status */ 69 #define GEM_ERROR_MASK 0x0004 /* PCI Error Mask */ 70 #define GEM_BIF_CONFIG 0x0008 /* PCI BIF Configuration */ 71 #define GEM_BIF_DIAG 0x000c /* PCI BIF Diagnostic */ 72 #define GEM_RESET 0x0010 /* PCI Software Reset */ 73 74 #define GEM_SBUS_RESET 0x0000 /* SBus Reset */ 75 #define GEM_SBUS_CONFIG 0x0004 /* SBus Burst-Size Configuration */ 76 #define GEM_SBUS_ERROR_STATUS 0x0008 /* SBus Fatal Error */ 77 #define GEM_SBUS_REVISION 0x000c /* SBus Revision */ 78 /* SBus Software Reset at same offset (0x0010) as PCI Software Reset above */ 79 80 /* 81 * Bits in GEM_SEB_STATE register 82 * For diagnostic use 83 */ 84 #define GEM_SEB_ARB 0x000000002 /* Arbitration status */ 85 #define GEM_SEB_RXWON 0x000000004 86 87 /* 88 * Bits in GEM_CONFIG register 89 * Default: 0x00042 90 */ 91 #define GEM_CONFIG_BURST_64 0x000000000 /* 0->infinity, 1->64KB */ 92 #define GEM_CONFIG_BURST_INF 0x000000001 /* 0->infinity, 1->64KB */ 93 #define GEM_CONFIG_TXDMA_LIMIT 0x00000003e 94 #define GEM_CONFIG_RXDMA_LIMIT 0x0000007c0 95 /* GEM_CONFIG_RONPAULBIT and GEM_CONFIG_BUG2FIX are Apple only. */ 96 #define GEM_CONFIG_RONPAULBIT 0x000000800 /* after infinite burst use 97 * memory read multiple for 98 * PCI commands */ 99 #define GEM_CONFIG_BUG2FIX 0x000001000 /* fix RX hang after overflow */ 100 101 #define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1 102 #define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 103 104 105 /* 106 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs. 107 * Bits 0-6 auto-clear when read. 108 */ 109 #define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */ 110 #define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */ 111 #define GEM_INTR_TX_DONE 0x000000004 /* TX complete */ 112 #define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */ 113 #define GEM_INTR_RX_NOBUF 0x000000020 /* No free receive buffers */ 114 #define GEM_INTR_RX_TAG_ERR 0x000000040 /* RX Tag framing error */ 115 #define GEM_INTR_PERR 0x000000080 /* Parity error */ 116 #define GEM_INTR_PCS 0x000002000 /* PCS interrupt */ 117 #define GEM_INTR_TX_MAC 0x000004000 /* TX MAC interrupt */ 118 #define GEM_INTR_RX_MAC 0x000008000 /* RX MAC interrupt */ 119 #define GEM_INTR_MAC_CONTROL 0x000010000 /* MAC control interrupt */ 120 #define GEM_INTR_MIF 0x000020000 /* MIF interrupt */ 121 #define GEM_INTR_BERR 0x000040000 /* Bus error interrupt */ 122 #define GEM_INTR_BITS "\177\020" \ 123 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 124 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 125 "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \ 126 "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0" 127 128 /* Top part (bits 19-31) of GEM_STATUS has TX completion information */ 129 #define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */ 130 131 132 /* 133 * Bits in GEM_ERROR_STATUS and GEM_ERROR_MASK PCI registers 134 */ 135 #define GEM_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */ 136 #define GEM_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */ 137 #define GEM_ERROR_STAT_OTHERS 0x000000004 /* Other PCI errors. Read PCI 138 Status Register in PCI 139 Configuration space */ 140 #define GEM_ERROR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0" 141 142 143 /* 144 * Bits in GEM_SBUS_CONFIG register 145 */ 146 #define GEM_SBUS_CFG_BSIZE32 0x00000001 147 #define GEM_SBUS_CFG_BSIZE64 0x00000002 148 #define GEM_SBUS_CFG_BSIZE128 0x00000004 149 #define GEM_SBUS_CFG_BMODE64 0x00000008 150 #define GEM_SBUS_CFG_PARITY 0x00000200 151 152 153 /* 154 * Bits in GEM_BIF_CONFIG register 155 * Default: 0x0 156 */ 157 #define GEM_BIF_CONFIG_SLOWCLK 0x000000001 /* Parity error timing */ 158 #define GEM_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */ 159 #define GEM_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */ 160 #define GEM_BIF_CONFIG_M66EN 0x000000008 161 #define GEM_BIF_CONFIG_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \ 162 "b\2B64DIS\0b\3M66EN\0\0" 163 164 165 /* 166 * Bits in GEM_BIF_DIAG register 167 * Default: 0x00000000 168 */ 169 #define GEN_BIF_DIAG_PCIBURST 0x007f0000 /* PCI Burst Controller state 170 * machine */ 171 #define GEN_BIF_DIAG_STATE 0xff000000 /* BIF state machine */ 172 173 /* 174 * Bits in GEM_RESET register 175 * RESET_TX and RESET_RX self clear when complete. 176 */ 177 #define GEM_RESET_TX 0x000000001 /* Reset TX half */ 178 #define GEM_RESET_RX 0x000000002 /* Reset RX half */ 179 #define GEM_RESET_GLOBAL 0x000000003 /* Global Reset */ 180 #define GEM_RESET_RSTOUT 0x000000004 /* Force PCI RSTOUT# */ 181 182 183 /* 184 * TX DMA Programmable Resources 185 * Section 3.1.4.2 186 * The 53 most significant bits of the Descriptor Base Low/High registers 187 * are used as the TX descriptor ring base address. The ring base must be 188 * initialized to a 2KByte-aligned address after power-on or software reset. 189 */ 190 #define GEM_TX_KICK 0x2000 /* TX Kick */ 191 /* Note: Write last valid desc + 1 */ 192 #define GEM_TX_CONFIG 0x2004 /* TX Configuration */ 193 #define GEM_TX_RING_PTR_LO 0x2008 /* TX Descriptor Base Low */ 194 #define GEM_TX_RING_PTR_HI 0x200c /* TX Descriptor Base High */ 195 /* 0x2010 Reserved */ 196 #define GEM_TX_FIFO_WR_PTR 0x2014 /* TX FIFO Write Pointer */ 197 #define GEM_TX_FIFO_SDWR_PTR 0x2018 /* TX FIFO Shadow Write Ptr */ 198 #define GEM_TX_FIFO_RD_PTR 0x201c /* TX FIFO Read Pointer */ 199 #define GEM_TX_FIFO_SDRD_PTR 0x2020 /* TX FIFO Shadow Read Ptr */ 200 #define GEM_TX_FIFO_PKT_CNT 0x2024 /* TX FIFO Packet Counter */ 201 #define GEM_TX_STATE_MACHINE 0x2028 /* TX State Machine */ 202 /* 0x202c Unknown */ 203 #define GEM_TX_DATA_PTR_LO 0x2030 /* TX Data Pointer Low */ 204 #define GEM_TX_DATA_PTR_HI 0x2034 /* TX Data Pointer High */ 205 206 #define GEM_TX_COMPLETION 0x2100 /* TX Completion */ 207 #define GEM_TX_FIFO_ADDRESS 0x2104 /* TX FIFO Address */ 208 #define GEM_TX_FIFO_TAG 0x2108 /* TX FIFO Tag */ 209 #define GEM_TX_FIFO_DATA_LO 0x210c /* TX FIFO Data Low */ 210 #define GEM_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO Data HighT1 */ 211 #define GEM_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO Data HighT0 */ 212 #define GEM_TX_FIFO_SIZE 0x2118 /* TX FIFO Size */ 213 #define GEM_TX_DEBUG 0x3028 214 215 216 /* 217 * Bits in GEM_TX_CONFIG register 218 * Default: 0x118c10 219 * TX FIFO Threshold should be set to 0x4ff 220 */ 221 #define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 222 #define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 223 #define GEM_TX_CONFIG_TXFIFO_SL 0x00000020 /* TX DMA FIFO PIO select */ 224 #define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 225 #define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 226 227 #define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 228 #define GEM_RING_SZ_64 (1<<1) 229 #define GEM_RING_SZ_128 (2<<1) 230 #define GEM_RING_SZ_256 (3<<1) 231 #define GEM_RING_SZ_512 (4<<1) 232 #define GEM_RING_SZ_1024 (5<<1) 233 #define GEM_RING_SZ_2048 (6<<1) 234 #define GEM_RING_SZ_4096 (7<<1) 235 #define GEM_RING_SZ_8192 (8<<1) /* Default */ 236 237 238 /* 239 * Bits in GEM_TX_COMPLETION register 240 */ 241 #define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */ 242 243 244 /* 245 * RX DMA Programmable Resources 246 * Section 3.1.4.3 247 * The 53 most significant bits of the Descriptor Base Low/High registers 248 * are used as the RX descriptor ring base address. The ring base must be 249 * initialized to a 2KByte-aligned address after power-on or software reset. 250 */ 251 #define GEM_RX_CONFIG 0x4000 /* RX Configuration */ 252 #define GEM_RX_RING_PTR_LO 0x4004 /* RX Descriptor Base Low */ 253 #define GEM_RX_RING_PTR_HI 0x4008 /* RX Descriptor Base High */ 254 #define GEM_RX_FIFO_WR_PTR 0x400c /* RX FIFO Write Pointer */ 255 #define GEM_RX_FIFO_SDWR_PTR 0x4010 /* RX FIFO Shadow Write Ptr */ 256 #define GEM_RX_FIFO_RD_PTR 0x4014 /* RX FIFO Read Pointer */ 257 #define GEM_RX_FIFO_PKT_CNT 0x4018 /* RX FIFO Packet Counter */ 258 #define GEM_RX_STATE_MACHINE 0x401c /* RX State Machine */ 259 #define GEM_RX_PAUSE_THRESH 0x4020 /* Pause Thresholds */ 260 #define GEM_RX_DATA_PTR_LO 0x4024 /* RX Data Pointer Low */ 261 #define GEM_RX_DATA_PTR_HI 0x4028 /* RX Data Pointer High */ 262 263 #define GEM_RX_KICK 0x4100 /* RX Kick */ 264 /* Note: Write last valid desc + 1. Must be a multiple of 4 */ 265 #define GEM_RX_COMPLETION 0x4104 /* RX Completion */ 266 #define GEM_RX_BLANKING 0x4108 /* RX Blanking */ 267 #define GEM_RX_FIFO_ADDRESS 0x410c /* RX FIFO Address */ 268 #define GEM_RX_FIFO_TAG 0x4110 /* RX FIFO Tag */ 269 #define GEM_RX_FIFO_DATA_LO 0x4114 /* RX FIFO Data Low */ 270 #define GEM_RX_FIFO_DATA_HI_T1 0x4118 /* RX FIFO Data HighT0 */ 271 #define GEM_RX_FIFO_DATA_HI_T0 0x411c /* RX FIFO Data HighT1 */ 272 #define GEM_RX_FIFO_SIZE 0x4120 /* RX FIFO Size */ 273 274 275 /* 276 * Bits in GEM_RX_CONFIG register 277 * Default: 0x1000010 278 */ 279 #define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 280 #define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 281 #define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 282 #define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 283 #define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */ 284 #define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 285 286 #define GEM_THRSH_64 0 287 #define GEM_THRSH_128 1 288 #define GEM_THRSH_256 2 289 #define GEM_THRSH_512 3 290 #define GEM_THRSH_1024 4 291 #define GEM_THRSH_2048 5 292 293 #define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24 294 #define GEM_RX_CONFIG_FBOFF_SHFT 10 295 #define GEM_RX_CONFIG_CXM_START_SHFT 13 296 297 298 /* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */ 299 #define GEM_RX_PTH_XOFF_THRESH 0x000001ff 300 #define GEM_RX_PTH_XON_THRESH 0x001ff000 301 302 303 /* GEM_RX_BLANKING register bits */ 304 #define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */ 305 #define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */ 306 #define GEM_RX_BLANKING_TIME_SHIFT 12 307 /* One tick is 2048 PCI clocks, or 16us at 66MHz */ 308 309 310 /* 311 * MAC Programmable Resources 312 * Section 3.1.5 313 */ 314 #define GEM_MAC_TXRESET 0x6000 /* TX MAC Software Reset Cmd */ 315 #define GEM_MAC_RXRESET 0x6004 /* RX MAC Software Reset Cmd */ 316 /* Note: Store 1, cleared when done for TXRESET and RXRESET */ 317 #define GEM_MAC_SEND_PAUSE_CMD 0x6008 /* Send Pause Command */ 318 #define GEM_MAC_TX_STATUS 0x6010 /* TX MAC Status */ 319 #define GEM_MAC_RX_STATUS 0x6014 /* RX MAC Status */ 320 #define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC Control Status */ 321 #define GEM_MAC_TX_MASK 0x6020 /* TX MAC Mask */ 322 #define GEM_MAC_RX_MASK 0x6024 /* RX MAC Mask */ 323 #define GEM_MAC_CONTROL_MASK 0x6028 /* MAC Control Mask */ 324 #define GEM_MAC_TX_CONFIG 0x6030 /* TX MAC Configuration */ 325 #define GEM_MAC_RX_CONFIG 0x6034 /* XX MAC Configuration */ 326 #define GEM_MAC_CONTROL_CONFIG 0x6038 /* MAC Control Configuration */ 327 #define GEM_MAC_XIF_CONFIG 0x603c /* XIF Configuration */ 328 #define GEM_MAC_IPG0 0x6040 /* InterPacketGap0 */ 329 #define GEM_MAC_IPG1 0x6044 /* InterPacketGap1 */ 330 #define GEM_MAC_IPG2 0x6048 /* InterPacketGap2 */ 331 #define GEM_MAC_SLOT_TIME 0x604c /* SlotTime, bits 0-7 */ 332 #define GEM_MAC_MAC_MIN_FRAME 0x6050 /* MinFrameSize */ 333 #define GEM_MAC_MAC_MAX_FRAME 0x6054 /* MaxFrameSize */ 334 #define GEM_MAC_PREAMBLE_LEN 0x6058 /* PA Size */ 335 #define GEM_MAC_JAM_SIZE 0x605c /* JamSize */ 336 #define GEM_MAC_ATTEMPT_LIMIT 0x6060 /* Attempt Limit */ 337 #define GEM_MAC_CONTROL_TYPE 0x6064 /* MAC Control Type */ 338 339 #define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */ 340 #define GEM_MAC_ADDR1 0x6084 341 #define GEM_MAC_ADDR2 0x6088 342 #define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */ 343 #define GEM_MAC_ADDR4 0x6090 344 #define GEM_MAC_ADDR5 0x6094 345 #define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */ 346 #define GEM_MAC_ADDR7 0x609c 347 #define GEM_MAC_ADDR8 0x60a0 348 349 #define GEM_MAC_ADDR_FILTER0 0x60a4 /* Address Filter */ 350 #define GEM_MAC_ADDR_FILTER1 0x60a8 351 #define GEM_MAC_ADDR_FILTER2 0x60ac 352 #define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address Filter Mask 2&1 */ 353 #define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address Filter Mask 0 */ 354 355 #define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */ 356 #define GEM_MAC_HASH1 0x60c4 357 #define GEM_MAC_HASH2 0x60c8 358 #define GEM_MAC_HASH3 0x60cc 359 #define GEM_MAC_HASH4 0x60d0 360 #define GEM_MAC_HASH5 0x60d4 361 #define GEM_MAC_HASH6 0x60d8 362 #define GEM_MAC_HASH7 0x60dc 363 #define GEM_MAC_HASH8 0x60e0 364 #define GEM_MAC_HASH9 0x60e4 365 #define GEM_MAC_HASH10 0x60e8 366 #define GEM_MAC_HASH11 0x60ec 367 #define GEM_MAC_HASH12 0x60f0 368 #define GEM_MAC_HASH13 0x60f4 369 #define GEM_MAC_HASH14 0x60f8 370 #define GEM_MAC_HASH15 0x60fc 371 372 #define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal Collision Counter */ 373 #define GEM_MAC_FIRST_COLL_CNT 0x6104 /* First Attempt Successful 374 Collision Counter */ 375 #define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess Collision Counter */ 376 #define GEM_MAC_LATE_COLL_CNT 0x610c /* Late Collision Counter */ 377 #define GEM_MAC_DEFER_TMR_CNT 0x6110 /* Defer Timer */ 378 #define GEM_MAC_PEAK_ATTEMPTS 0x6114 /* Peak Attempts */ 379 #define GEM_MAC_RX_FRAME_COUNT 0x6118 /* Receive Frame Counter */ 380 #define GEM_MAC_RX_LEN_ERR_CNT 0x611c /* Length Error Counter */ 381 #define GEM_MAC_RX_ALIGN_ERR 0x6120 /* Alignment Error Counter */ 382 #define GEM_MAC_RX_CRC_ERR_CNT 0x6124 /* FCS Error Counter */ 383 #define GEM_MAC_RX_CODE_VIOL 0x6128 /* RX Code Violation Error 384 Counter */ 385 386 #define GEM_MAC_RANDOM_SEED 0x6130 /* Random Number Seed */ 387 #define GEM_MAC_MAC_STATE 0x6134 /* State Machine */ 388 389 390 /* 391 * Bits in GEM_MAC_SEND_PAUSE_CMD register 392 * Pause time is in units of Slot Times. 393 */ 394 #define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff 395 #define GEM_MAC_PAUSE_CMD_SEND 0x00010000 396 397 398 /* 399 * Bits in GEM_MAC_TX_STATUS and _MASK register 400 * Interrupt bits are auto-cleared when the status register is read and 401 * the corresponding bit is set in the mask register. 402 */ 403 #define GEM_MAC_TX_XMIT_DONE 0x00000001 /* Successful transmission */ 404 #define GEM_MAC_TX_UNDERRUN 0x00000002 /* TX "data starvation" */ 405 #define GEM_MAC_TX_PKT_TOO_LONG 0x00000004 /* Frame exceeds max. length */ 406 #define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision counter has 407 rolled over */ 408 #define GEM_MAC_TX_ECC_EXP 0x00000010 /* Excessive coll cnt rolled */ 409 #define GEM_MAC_TX_LCC_EXP 0x00000020 /* Late coll cnt rolled */ 410 #define GEM_MAC_TX_FCC_EXP 0x00000040 /* First coll cnt rolled */ 411 #define GEM_MAC_TX_DEFER_EXP 0x00000080 /* Defer timer cnt rolled */ 412 #define GEM_MAC_TX_PEAK_EXP 0x00000100 /* Peak attempts cnt rolled */ 413 414 415 /* 416 * Bits in GEM_MAC_RX_STATUS and _MASK register 417 */ 418 #define GEM_MAC_RX_DONE 0x00000001 /* Successful reception */ 419 #define GEM_MAC_RX_OVERFLOW 0x00000002 /* RX resource lack */ 420 #define GEM_MAC_RX_FRAME_CNT 0x00000004 /* Receive frame counter has 421 rolled over */ 422 #define GEM_MAC_RX_ALIGN_EXP 0x00000008 /* Alignment error cnt rolled */ 423 #define GEM_MAC_RX_CRC_EXP 0x00000010 /* CRC error cnt rolled */ 424 #define GEM_MAC_RX_LEN_EXP 0x00000020 /* Length error cnt rolled */ 425 #define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation err rolled */ 426 427 428 /* 429 * Bits in GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register 430 */ 431 #define GEM_MAC_PAUSED 0x00000001 /* Pause received */ 432 #define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ 433 #define GEM_MAC_RESUME 0x00000004 /* exit pause state */ 434 #define GEM_MAC_PAUSE_TIME 0xffff0000 /* Pause time received */ 435 #define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0" 436 437 438 /* 439 * Bits in GEM_MAC_XIF_CONFIG register 440 * Default: 0x00 441 */ 442 #define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable MII output */ 443 #define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable (G)MII loopback */ 444 #define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */ 445 #define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */ 446 #define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ 447 #define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ 448 #define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ 449 #define GEM_MAC_XIF_BITS "\177\020b\0TXMIIENA\0b\1MIILOOP\0b\2NOECHO" \ 450 "\0b\3GMII\0b\4MIIBUFENA\0b\5LINKLED\0" \ 451 "b\6FDLED\0\0" 452 453 454 /* 455 * Bits in GEM_MAC_TX_CONFIG register 456 * GEM_MAC_TX_ENABLE must be cleared and a delay imposed before writing to 457 * other bits in this register or any of the MAC parameters registers. 458 * The GEM_MAC_TX_ENABLE bit will read 0 when the transmitter has stopped. 459 * Carrier Extension must be set when operating in Half-Duplex at 1Gbps, 460 * and disabled otherwise. To enable this GEM_MAC_TX_CARR_EXTEND and 461 * GEM_MAC_RX_CARR_EXTEND must be set to 1 and the Slot Time register must 462 * be set to 0x200. 463 */ 464 #define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 465 #define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 466 #define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */ 467 #define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend Rx-to-TX IPG */ 468 #define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 469 #define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 470 #define GEM_MAC_TX_NO_BACKOFF 0x00000040 /* Never backoff on coll */ 471 #define GEM_MAC_TX_SLOWDOWN 0x00000080 /* Watch carrier sense */ 472 #define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 473 #define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 474 #define GEM_MAC_TX_CONFIG_BITS "\177\020" \ 475 "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \ 476 "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \ 477 "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \ 478 "b\x9TXCARREXT\0\0" 479 480 481 /* 482 * Bits in GEM_MAC_RX_CONFIG register 483 * The GEM_MAC_RX_ENABLE bit must be cleared and a delay of 3.2ms imposed 484 * before writing to other bits in this register or any of the MAC 485 * parameters registers. The GEM_MAC_RX_ENABLE bit will read 0 when the 486 * receiver has stopped. 487 * The GEM_MAC_RX_HASH_FILTER bit must be cleared and a delay of 3.2ms 488 * imposed before writing to any of the Hash Table registers. The 489 * GEM_MAC_RX_HASH_FILTER bit will read 0 when the registers may be written. 490 * The GEM_MAC_RX_ADDR_FILTER bit must be cleared and a delay of 3.2ms 491 * imposed before writing to any of the Address Filter registers. The 492 * GEM_MAC_RX_ADDR_FILTER bit will read 0 when the registers may be written. 493 * See "Carrier Extension" above. 494 */ 495 #define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */ 496 #define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */ 497 #define GEM_MAC_RX_STRIP_CRC 0x00000004 498 #define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */ 499 #define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */ 500 #define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */ 501 #define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */ 502 #define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error discard */ 503 #define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */ 504 #define GEM_MAC_RX_CONFIG_BITS "\177\020" \ 505 "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \ 506 "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \ 507 "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0" 508 509 510 /* 511 * Bits in GEM_MAC_CONTROL_CONFIG 512 * Default; 0x0 513 */ 514 #define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 515 #define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 516 #define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 517 #define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0" 518 519 /* GEM_MAC_MAC_STATE register bits */ 520 #define GEM_MAC_STATE_OVERFLOW 0x03800000 521 522 /* 523 * Bits in GEM_MAC_SLOT_TIME register 524 * The slot time is used as PAUSE time unit, value depends on whether carrier 525 * extension is enabled. 526 */ 527 #define GEM_MAC_SLOT_TIME_CARR_EXTEND 0x200 528 #define GEM_MAC_SLOT_TIME_NORMAL 0x40 529 530 531 /* 532 * Recommended values for MAC registers: 533 * GEM_MAC_IPG0 0x00 534 * GEM_MAC_IPG1 0x08 535 * GEM_MAC_IPG2 0x04 536 * GEM_MAC_SLOT_TIME 0x40 (see "Carrier Extension" above) 537 * Bits in GEM_MAC_MAC_MAX_FRAME register 538 * max burst size 0x7fff0000 539 * max frame size 0x00007fff 540 * GEM_MAC_MAC_MIN_FRAME 0x40 541 * GEM_MAC_MAC_MAX_FRAME 0x200005ee 542 * GEM_MAC_PREAMBLE_LEN 0x07 (minimum of 0x02) 543 * GEM_MAC_JAM_SIZE 0x04 544 * GEM_MAC_ATTEMPT_LIMIT 0x10 545 * GEM_MAC_CONTROL_TYPE 0x8808 546 */ 547 548 549 /* 550 * Address detection and filtering registers (16-bit unless noted): 551 * GEM_MAC_ADDR0 normal priority MAC address bits 32-47 552 * GEM_MAC_ADDR1 normal priority MAC address bits 16-31 553 * GEM_MAC_ADDR2 normal priority MAC address bits 0-15 554 * GEM_MAC_ADDR3 alternate MAC address bits 32-47 555 * GEM_MAC_ADDR4 alternate MAC address bits 16-31 556 * GEM_MAC_ADDR5 alternate MAC address bits 0-15 557 * GEM_MAC_ADDR6 MAC control address bits 32-47 558 * GEM_MAC_ADDR7 MAC control address bits 16-31 559 * GEM_MAC_ADDR8 MAC control address bits 0-15 560 * GEM_MAC_ADDR_FILTER0 address filter bits 32-47 561 * GEM_MAC_ADDR_FILTER1 address filter bits 16-31 562 * GEM_MAC_ADDR_FILTER2 address filter bits 0-15 563 * GEM_MAC_ADR_FLT_MASK1_2 mask for GEM_MAC_ADDR_FILTER1 and 2 (8-bit) 564 * GEM_MAC_ADR_FLT_MASK0 mask for GEM_MAC_ADDR_FILTER0 565 * GEM_MAC_HASH0 hash table bits 240-255 566 * GEM_MAC_HASH1 hash table bits 224-239 567 * GEM_MAC_HASH2 hash table bits 208-223 568 * GEM_MAC_HASH3 hash table bits 192-207 569 * GEM_MAC_HASH4 hash table bits 176-191 570 * GEM_MAC_HASH5 hash table bits 160-175 571 * GEM_MAC_HASH6 hash table bits 144-159 572 * GEM_MAC_HASH7 hash table bits 128-143 573 * GEM_MAC_HASH8 hash table bits 112-127 574 * GEM_MAC_HASH9 hash table bits 96-111 575 * GEM_MAC_HASH10 hash table bits 80-95 576 * GEM_MAC_HASH11 hash table bits 64-79 577 * GEM_MAC_HASH12 hash table bits 48-63 578 * GEM_MAC_HASH13 hash table bits 32-47 579 * GEM_MAC_HASH14 hash table bits 16-31 580 * GEM_MAC_HASH15 hash table bits 0-15 581 */ 582 583 /* 584 * Recommended values for statistic registers: 585 * GEM_MAC_NORM_COLL_CNT 0x0000 586 * GEM_MAC_FIRST_COLL_CNT 0x0000 587 * GEM_MAC_EXCESS_COLL_CNT 0x0000 588 * GEM_MAC_LATE_COLL_CNT 0x0000 589 * GEM_MAC_DEFER_TMR_CNT 0x0000 590 * GEM_MAC_PEAK_ATTEMPTS 0x0000 591 * GEM_MAC_RX_FRAME_COUNT 0x0000 592 * GEM_MAC_RX_LEN_ERR_CNT 0x0000 593 * GEM_MAC_RX_ALIGN_ERR 0x0000 594 * GEM_MAC_RX_CRC_ERR_CNT 0x0000 595 * GEM_MAC_RX_CODE_VIOL 0x0000 596 */ 597 598 599 /* 600 * MIF Programmable Resources 601 * Section 3.1.5.8 602 * Bit-bang registers use low bit only 603 */ 604 #define GEM_MIF_BB_CLOCK 0x6200 /* MIF Bit-Bang Clock */ 605 #define GEM_MIF_BB_DATA 0x6204 /* MIF Bit-Bang Data */ 606 #define GEM_MIF_BB_OUTPUT_ENAB 0x6208 /* MIF Bit-Bang Output Enable */ 607 #define GEM_MIF_FRAME 0x620c /* MIF Frame/Output */ 608 #define GEM_MIF_CONFIG 0x6210 /* MIF Configuration */ 609 #define GEM_MIF_INTERRUPT_MASK 0x6214 /* MIF Mask */ 610 #define GEM_MIF_BASIC_STATUS 0x6218 /* MIF Status */ 611 #define GEM_MIF_STATE_MACHINE 0x621c /* MIF State Machine */ 612 613 614 /* 615 * Bits in GEM_MIF_FRAME register 616 */ 617 #define GEM_MIF_FRAME_DATA 0x0000ffff /* Instruction payload */ 618 #define GEM_MIF_FRAME_TA0 0x00010000 /* TA bit, 1 for completion */ 619 #define GEM_MIF_FRAME_TA1 0x00020000 /* TA bits */ 620 #define GEM_MIF_FRAME_REG_ADDR 0x007c0000 /* Register address */ 621 #define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* PHY address, should be 0 */ 622 #define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */ 623 #define GEM_MIF_FRAME_START 0xc0000000 /* START bits */ 624 625 #define GEM_MIF_FRAME_READ 0x60020000 626 #define GEM_MIF_FRAME_WRITE 0x50020000 627 628 #define GEM_MIF_REG_SHIFT 18 629 #define GEM_MIF_PHY_SHIFT 23 630 631 632 /* 633 * Bits in GEM_MIF_CONFIG register 634 */ 635 #define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0=MDIO_0 */ 636 #define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 637 #define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 638 #define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 639 #define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 B-B data/attached */ 640 #define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 B-B data/attached */ 641 #define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ 642 /* MDIO_0 is onboard transceiver MDIO_1 is external, PHY addr for both is 0 */ 643 #define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \ 644 "b\x8MDIO0\0b\x9MDIO1\0\0" 645 646 647 /* 648 * Bits in GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK 649 * The Basic part is the last value read in the POLL field of the config 650 * register. 651 * The status part indicates the bits that have changed. 652 */ 653 #define GEM_MIF_STATUS 0x0000ffff 654 #define GEM_MIF_BASIC 0xffff0000 655 656 657 /* 658 * PCS/Serialink Registers 659 * Section 3.1.6 660 * DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. 661 */ 662 #define GEM_MII_CONTROL 0x9000 /* PCS MII Control */ 663 #define GEM_MII_STATUS 0x9004 /* PCS MII Status */ 664 #define GEM_MII_ANAR 0x9008 /* PCS MII Advertisement */ 665 #define GEM_MII_ANLPAR 0x900c /* PCS MII Link Partner 666 Ability */ 667 #define GEM_MII_CONFIG 0x9010 /* PCS Configuration */ 668 #define GEM_MII_STATE_MACHINE 0x9014 /* PCS State Machine */ 669 #define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS Interrupt Status */ 670 #define GEM_MII_DATAPATH_MODE 0x9050 /* Datapath Mode Register */ 671 #define GEM_MII_SLINK_CONTROL 0x9054 /* Serialink Control */ 672 #define GEM_MII_OUTPUT_SELECT 0x9058 /* Share Output Select */ 673 #define GEM_MII_SLINK_STATUS 0x905c /* Serialink Status */ 674 675 676 /* 677 * Bits in GEM_MII_CONTROL register 678 * PCS "BMCR" (Basic Mode Control Reg) 679 * Default: 0x1040 680 * AUTONEG and RESET self clear when relevant process is completed. 681 */ 682 #define GEM_MII_1GB_SPEED_SEL 0x00000040 /* 1000Mb/s, always 1 */ 683 #define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ 684 #define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */ 685 #define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto negotiation */ 686 #define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate PHY, ignored */ 687 #define GEM_MII_CONTROL_POWERDN 0x00000800 /* power down, ignored */ 688 #define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto negotiation enabled */ 689 #define GEM_MII_CONTROL_SPEED 0x00002000 /* speed select, ignored */ 690 #define GEM_MII_CONTROL_LOOPBK 0x00004000 /* Serialink loopback */ 691 #define GEM_MII_CONTROL_RESET 0x00008000 /* Reset PCS */ 692 #define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \ 693 "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \ 694 "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0" 695 696 697 /* 698 * Bits in GEM_MII_STATUS register. 699 * PCS "BMSR" (Basic Mode Status Reg) 700 * Default: 0x0108 701 */ 702 #define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended capability, always 0 */ 703 #define GEM_MII_STATUS_JABBER 0x00000002 /* jabber detected, always 0 */ 704 #define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status, 1=up */ 705 #define GEM_MII_STATUS_ACFG 0x00000008 /* can auto neg, always 1 */ 706 #define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 707 #define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate complete */ 708 #define GEM_MII_STATUS_EXT_STS 0x00000100 /* Is 1000Base-X, always 1 */ 709 #define GEM_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */ 710 #define GEM_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */ 711 #define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \ 712 "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0b\x9GBHDX\0" \ 713 "b\xaGBFDX\0\0" 714 715 716 /* 717 * Bits in GEM_MII_ANAR and GEM_MII_ANLPAR registers 718 * GEM_MII_ANAR contains our capabilities for auto- negotiation 719 * (Default: 0x00e0) and GEM_MII_ANLPAR contains the link partners 720 * abilities and is only valid after auto-negotiation completes. 721 */ 722 #define GEM_MII_ANEG_FUL_DUPLX 0x00000020 /* can do 1000Base-X FDX */ 723 #define GEM_MII_ANEG_HLF_DUPLX 0x00000040 /* can do 1000Base-X HDX */ 724 #define GEM_MII_ANEG_SYM_PAUSE 0x00000080 /* can do symmetric pause */ 725 #define GEM_MII_ANEG_ASYM_PAUSE 0x00000100 /* can do asymmetric pause */ 726 #define GEM_MII_ANEG_RF 0x00003000 /* advertise remote fault */ 727 #define GEM_MII_ANEG_ACK 0x00004000 /* ack reception of 728 Link Partner Capability */ 729 #define GEM_MII_ANEG_NP 0x00008000 /* next page bit, always 0 */ 730 #define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \ 731 "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \ 732 "\b\xfNPBIT\0\0" 733 734 735 /* 736 * Bits in GEM_MII_CONFIG register 737 * Default: 0x0 738 * GEM_MII_CONFIG_ENABLE must be 0 when modifiying the GEM_MII_ANAR 739 * register. To isolate the MC from the media, set this bit to 0 and 740 * restart auto-negotiation in GEM_MII_CONTROL. 741 */ 742 #define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */ 743 #define GEM_MII_CONFIG_SDO 0x00000002 /* Signal Detect Override */ 744 #define GEM_MII_CONFIG_SDL 0x00000004 /* Signal Detect active low */ 745 #define GEM_MII_CONFIG_TIMER 0x0000000e /* link monitor timer values */ 746 #define GEM_MII_CONFIG_JS 0x00000018 /* Jitter Study, 0 normal 747 * 1 high freq, 2 low freq */ 748 #define GEM_MII_CONFIG_ANTO 0x00000020 /* 10ms ANEG timer override */ 749 #define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0" 750 751 752 /* 753 * Bits in GEM_MII_STATE_MACHINE register 754 * XXX These are best guesses from observed behavior. 755 */ 756 #define GEM_MII_FSM_STOP 0x00000000 /* stopped */ 757 #define GEM_MII_FSM_RUN 0x00000001 /* running */ 758 #define GEM_MII_FSM_UNKWN 0x00000100 /* unknown */ 759 #define GEM_MII_FSM_DONE 0x00000101 /* complete */ 760 761 762 /* 763 * Bits in GEM_MII_INTERRUP_STATUS register 764 * No mask register; mask with the global interrupt mask register. 765 */ 766 #define GEM_MII_INTERRUP_LINK 0x00000004 /* PCS link status change */ 767 768 769 /* 770 * Bits in GEM_MII_DATAPATH_MODE register 771 * Default: none 772 */ 773 #define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Use internal Serialink */ 774 #define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interface */ 775 #define GEM_MII_DATAPATH_MII 0x00000004 /* Use {G}MII, not PCS */ 776 #define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* Set serial output on GMII */ 777 #define GEM_MII_DATAPATH_BITS "\177\020" \ 778 "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3MIIOUT\0\0" 779 780 781 /* 782 * Bits in GEM_MII_SLINK_CONTROL register 783 * Default: 0x000 784 */ 785 #define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback on Serialink 786 disable loopback on SERDES */ 787 #define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */ 788 #define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock reference clock */ 789 #define GEM_MII_SLINK_EMPHASIS 0x00000018 /* enable emphasis */ 790 #define GEM_MII_SLINK_SELFTEST 0x000001c0 791 #define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down Serialink block */ 792 #define GEM_MII_SLINK_RX_ZERO 0x00000c00 /* PLL input to Serialink */ 793 #define GEM_MII_SLINK_RX_POLL 0x00003000 /* PLL input to Serialink */ 794 #define GEM_MII_SLINK_TX_ZERO 0x0000c000 /* PLL input to Serialink */ 795 #define GEM_MII_SLINK_TX_POLL 0x00030000 /* PLL input to Serialink */ 796 #define GEM_MII_SLINK_CONTROL_BITS \ 797 "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \ 798 "\0b\3EMPHASIS1\0b\4EMPHASIS2\0b\x9PWRDWN\0\0" 799 800 801 /* 802 * Bits in GEM_MII_OUTPUT_SELECT register 803 * Default: 0x0 804 */ 805 #define GEM_MII_PROM_ADDR 0x00000003 /* Test output multiplexor */ 806 807 808 /* 809 * Bits in GEM_MII_SLINK_STATUS register 810 * Default: 0x0 811 */ 812 #define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */ 813 #define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us lockrefn */ 814 #define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */ 815 #define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */ 816 817 818 /* 819 * PCI Expansion ROM runtime access 820 * Sun GEMs map a 1MB space for the PCI Expansion ROM as the second half 821 * of the first register bank, although they only support up to 64KB ROMs. 822 */ 823 #define GEM_PCI_ROM_OFFSET 0x100000 824 #define GEM_PCI_ROM_SIZE 0x10000 825 826 827 /* Wired GEM PHY addresses */ 828 #define GEM_PHYAD_INTERNAL 1 829 #define GEM_PHYAD_EXTERNAL 0 830 831 /* 832 * GEM descriptor table structures. 833 */ 834 struct gem_desc { 835 volatile uint64_t gd_flags; 836 volatile uint64_t gd_addr; 837 }; 838 839 /* Transmit flags */ 840 #define GEM_TD_BUFSIZE 0x0000000000007fffLL 841 #define GEM_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */ 842 #define GEM_TD_CXSUM_STARTSHFT 15 843 #define GEM_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */ 844 #define GEM_TD_CXSUM_STUFFSHFT 21 845 #define GEM_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */ 846 #define GEM_TD_END_OF_PACKET 0x0000000040000000LL 847 #define GEM_TD_START_OF_PACKET 0x0000000080000000LL 848 #define GEM_TD_INTERRUPT_ME 0x0000000100000000LL /* Interrupt me now */ 849 #define GEM_TD_NO_CRC 0x0000000200000000LL /* do not insert crc */ 850 /* 851 * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF, 852 * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group. 853 */ 854 855 /* Receive flags */ 856 #define GEM_RD_CHECKSUM 0x000000000000ffffLL /* is the complement */ 857 #define GEM_RD_BUFSIZE 0x000000007fff0000LL 858 #define GEM_RD_OWN 0x0000000080000000LL /* 1 - owned by h/w */ 859 #define GEM_RD_HASHVAL 0x0ffff00000000000LL 860 #define GEM_RD_HASH_PASS 0x1000000000000000LL /* passed hash filter */ 861 #define GEM_RD_ALTERNATE_MAC 0x2000000000000000LL /* Alternate MAC adrs */ 862 #define GEM_RD_BAD_CRC 0x4000000000000000LL 863 864 #define GEM_RD_BUFSHIFT 16 865 #define GEM_RD_BUFLEN(x) (((x)&GEM_RD_BUFSIZE)>>GEM_RD_BUFSHIFT) 866 867 #endif 868
Indexes created Mon Sep 22 13:09:51 GMT 2025