1 /* $NetBSD: bcmgenetreg.h,v 1.4 2021/03/08 13:14:44 mlelstv Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Broadcom GENETv5 31 */ 32 33 #ifndef _BCMGENETREG_H 34 #define _BCMGENETREG_H 35 36 #define GENET_SYS_REV_CTRL 0x000 37 #define SYS_REV_MAJOR __BITS(27,24) 38 #define SYS_REV_MINOR __BITS(19,16) 39 #define GENET_SYS_PORT_CTRL 0x004 40 #define GENET_SYS_PORT_MODE_EXT_GPHY 3 41 #define GENET_SYS_RBUF_FLUSH_CTRL 0x008 42 #define GENET_SYS_RBUF_FLUSH_RESET __BIT(1) 43 #define GENET_SYS_TBUF_FLUSH_CTRL 0x00c 44 #define GENET_EXT_RGMII_OOB_CTRL 0x08c 45 #define GENET_EXT_RGMII_OOB_ID_MODE_DISABLE __BIT(16) 46 #define GENET_EXT_RGMII_OOB_RGMII_MODE_EN __BIT(6) 47 #define GENET_EXT_RGMII_OOB_OOB_DISABLE __BIT(5) 48 #define GENET_EXT_RGMII_OOB_RGMII_LINK __BIT(4) 49 #define GENET_INTRL2_CPU_STAT 0x200 50 #define GENET_INTRL2_CPU_CLEAR 0x208 51 #define GENET_INTRL2_CPU_STAT_MASK 0x20c 52 #define GENET_INTRL2_CPU_SET_MASK 0x210 53 #define GENET_INTRL2_CPU_CLEAR_MASK 0x214 54 #define GENET_IRQ_MDIO_ERROR __BIT(24) 55 #define GENET_IRQ_MDIO_DONE __BIT(23) 56 #define GENET_IRQ_TXDMA_DONE __BIT(16) 57 #define GENET_IRQ_RXDMA_DONE __BIT(13) 58 #define GENET_RBUF_CTRL 0x300 59 #define GENET_RBUF_BAD_DIS __BIT(2) 60 #define GENET_RBUF_ALIGN_2B __BIT(1) 61 #define GENET_RBUF_64B_EN __BIT(0) 62 #define GENET_RBUF_TBUF_SIZE_CTRL 0x3b4 63 #define GENET_UMAC_CMD 0x808 64 #define GENET_UMAC_CMD_LCL_LOOP_EN __BIT(15) 65 #define GENET_UMAC_CMD_SW_RESET __BIT(13) 66 #define GENET_UMAC_CMD_PROMISC __BIT(4) 67 #define GENET_UMAC_CMD_SPEED __BITS(3,2) 68 #define GENET_UMAC_CMD_SPEED_10 0 69 #define GENET_UMAC_CMD_SPEED_100 1 70 #define GENET_UMAC_CMD_SPEED_1000 2 71 #define GENET_UMAC_CMD_RXEN __BIT(1) 72 #define GENET_UMAC_CMD_TXEN __BIT(0) 73 #define GENET_UMAC_MAC0 0x80c 74 #define GENET_UMAC_MAC1 0x810 75 #define GENET_UMAC_MAX_FRAME_LEN 0x814 76 #define GENET_UMAC_TX_FLUSH 0xb34 77 #define GENET_UMAC_MIB_CTRL 0xd80 78 #define GENET_UMAC_MIB_RESET_TX __BIT(2) 79 #define GENET_UMAC_MIB_RESET_RUNT __BIT(1) 80 #define GENET_UMAC_MIB_RESET_RX __BIT(0) 81 #define GENET_MDIO_CMD 0xe14 82 #define GENET_MDIO_START_BUSY __BIT(29) 83 #define GENET_MDIO_READ __BIT(27) 84 #define GENET_MDIO_WRITE __BIT(26) 85 #define GENET_MDIO_PMD __BITS(25,21) 86 #define GENET_MDIO_REG __BITS(20,16) 87 #define GENET_UMAC_MDF_CTRL 0xe50 88 #define GENET_UMAC_MDF_ADDR0(n) (0xe54 + (n) * 0x8) 89 #define GENET_UMAC_MDF_ADDR1(n) (0xe58 + (n) * 0x8) 90 91 #define GENET_DMA_DESC_COUNT 256 92 #define GENET_DMA_DESC_SIZE 12 93 #define GENET_DMA_DEFAULT_QUEUE 16 94 95 #define GENET_DMA_RING_SIZE 0x40 96 #define GENET_DMA_RINGS_SIZE (GENET_DMA_RING_SIZE * (GENET_DMA_DEFAULT_QUEUE + 1)) 97 98 #define GENET_RX_BASE 0x2000 99 #define GENET_TX_BASE 0x4000 100 101 #define GENET_RX_DMA_RINGBASE(qid) (GENET_RX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid)) 102 #define GENET_RX_DMA_WRITE_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x00) 103 #define GENET_RX_DMA_WRITE_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x04) 104 #define GENET_RX_DMA_PROD_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x08) 105 #define GENET_RX_DMA_CONS_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x0c) 106 #define GENET_RX_DMA_RING_BUF_SIZE(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x10) 107 #define GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT __BITS(31,16) 108 #define GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0) 109 #define GENET_RX_DMA_START_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x14) 110 #define GENET_RX_DMA_START_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x18) 111 #define GENET_RX_DMA_END_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x1c) 112 #define GENET_RX_DMA_END_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x20) 113 #define GENET_RX_DMA_MBUF_DONE_THRES(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x24) 114 #define GENET_RX_DMA_XON_XOFF_THRES(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x28) 115 #define GENET_RX_DMA_XON_XOFF_THRES_LO __BITS(31,16) 116 #define GENET_RX_DMA_XON_XOFF_THRES_HI __BITS(15,0) 117 #define GENET_RX_DMA_READ_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x2c) 118 #define GENET_RX_DMA_READ_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x30) 119 120 #define GENET_TX_DMA_RINGBASE(qid) (GENET_TX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid)) 121 #define GENET_TX_DMA_READ_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x00) 122 #define GENET_TX_DMA_READ_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x04) 123 #define GENET_TX_DMA_CONS_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x08) 124 #define GENET_TX_DMA_PROD_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x0c) 125 #define GENET_TX_DMA_RING_BUF_SIZE(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x10) 126 #define GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT __BITS(31,16) 127 #define GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0) 128 #define GENET_TX_DMA_START_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x14) 129 #define GENET_TX_DMA_START_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x18) 130 #define GENET_TX_DMA_END_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x1c) 131 #define GENET_TX_DMA_END_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x20) 132 #define GENET_TX_DMA_MBUF_DONE_THRES(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x24) 133 #define GENET_TX_DMA_FLOW_PERIOD(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x28) 134 #define GENET_TX_DMA_WRITE_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x2c) 135 #define GENET_TX_DMA_WRITE_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x30) 136 137 #define GENET_RX_DESC_STATUS(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00) 138 #define GENET_RX_DESC_STATUS_BUFLEN __BITS(27,16) 139 #define GENET_RX_DESC_STATUS_OWN __BIT(15) 140 #define GENET_RX_DESC_STATUS_EOP __BIT(14) 141 #define GENET_RX_DESC_STATUS_SOP __BIT(13) 142 #define GENET_RX_DESC_STATUS_ALL_ERRS __BITS(4,0) 143 #define GENET_RX_DESC_STATUS_LEN_ERR __BIT(4) 144 #define GENET_RX_DESC_STATUS_FRAME_ERR __BIT(3) 145 #define GENET_RX_DESC_STATUS_RX_ERR __BIT(2) 146 #define GENET_RX_DESC_STATUS_CRC_ERR __BIT(1) 147 #define GENET_RX_DESC_STATUS_OVRUN_ERR __BIT(0) 148 #define GENET_RX_DESC_ADDRESS_LO(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04) 149 #define GENET_RX_DESC_ADDRESS_HI(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08) 150 151 #define GENET_TX_DESC_STATUS(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00) 152 #define GENET_TX_DESC_STATUS_BUFLEN __BITS(27,16) 153 #define GENET_TX_DESC_STATUS_OWN __BIT(15) 154 #define GENET_TX_DESC_STATUS_EOP __BIT(14) 155 #define GENET_TX_DESC_STATUS_SOP __BIT(13) 156 #define GENET_TX_DESC_STATUS_QTAG __BITS(12,7) 157 #define GENET_TX_DESC_STATUS_CRC __BIT(6) 158 #define GENET_TX_DESC_ADDRESS_LO(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04) 159 #define GENET_TX_DESC_ADDRESS_HI(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08) 160 161 #define GENET_RX_DMA_RING_CFG (GENET_RX_BASE + 0x1040 + 0x00) 162 #define GENET_RX_DMA_CTRL (GENET_RX_BASE + 0x1040 + 0x04) 163 #define GENET_RX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1) 164 #define GENET_RX_DMA_CTRL_EN __BIT(0) 165 #define GENET_RX_SCB_BURST_SIZE (GENET_RX_BASE + 0x1040 + 0x0c) 166 #define GENET_RX_DMA_RING_TIMEOUT(qid) (GENET_RX_BASE + 0x1040 + 0x2c + 4 * (qid)) 167 168 #define GENET_TX_DMA_RING_CFG (GENET_TX_BASE + 0x1040 + 0x00) 169 #define GENET_TX_DMA_CTRL (GENET_TX_BASE + 0x1040 + 0x04) 170 #define GENET_TX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1) 171 #define GENET_TX_DMA_CTRL_EN __BIT(0) 172 #define GENET_TX_SCB_BURST_SIZE (GENET_TX_BASE + 0x1040 + 0x0c) 173 #define GENET_TX_DMA_RING_TIMEOUT(qid) (GENET_TX_BASE + 0x1040 + 0x2c + 4 * (qid)) 174 175 /* GENET_RX_DMA_MBUF_DONE_THRES, GENET_TX_DMA_MBUF_DONE_THRES */ 176 #define GENET_INTR_THRESHOLD_MASK __BITS(0,8) 177 /* GENET_RX_DMA_RING_TIMEOUT, GENET_TX_DMA_RING_TIMEOUT */ 178 #define GENET_DMA_RING_TIMEOUT_MASK __BITS(0,15) 179 180 #endif /* !_BCMGENETREG_H */ 181
Indexes created Tue Sep 23 07:09:52 GMT 2025