1 /* $NetBSD: gic_reg.h,v 1.12 2020/11/22 19:53:47 jmcneill Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * ARM Generic Interrupt Controller Register Definitions 33 * 34 * These registers are accessible through a dedicated internal bus. 35 * All accesses must be done in a little-endian manner. 36 * The base address of the pages containing these registers is defined 37 * by the pins PERIPHBASE[31:13] which can be obtained by doing a 38 * MRC p15,4,<Rd>,c15,c0,0; Read Configuration Base Address Register 39 * (except cortex-A9 uniprocessor) 40 * 41 * GIC is used by all Cortex-A cores except the A8. 42 */ 43 44 #ifndef _ARM_CORTEX_GICREG_H_ 45 #define _ARM_CORTEX_GICREG_H_ 46 47 #define GICC_BASE 0x0100 // Offset in PeriphBase 48 49 #define GICC_CTRL 0x0000 // CPU Interface Control Register 50 #define GICC_PMR 0x0004 // Interrupt Priority Mask Register 51 #define GICC_BPR 0x0008 // Binary Point Register 52 #define GICC_IAR 0x000C // Interrupt Acknowledge Register 53 #define GICC_EOIR 0x0010 // End Of Interrupt Register (WO) 54 #define GICC_RPR 0x0014 // Running Priority Register 55 #define GICC_HPPIR 0x0018 // Highest Priority Pending Interrupt Registers 56 #define GICC_ABPR 0x001C // Aliased Binary Point Register 57 #define GICC_AIAR 0x0020 // Aliased Interrupt Acknowledge Register 58 #define GICC_AEOIR 0x0024 // Aliased End Of Interrupt Register 59 #define GICC_AHPPIR 0x0028 // Aliased Highest Priority Pending Interrupt Registers 60 #define GICC_APR0 0x00D0 // Active Priorites Register 0 61 #define GICC_APR1 0x00D4 // Active Priorites Register 1 62 #define GICC_APR2 0x00D8 // Active Priorites Register 2 63 #define GICC_APR3 0x00DC // Active Priorites Register 3 64 #define GICC_NSAPR0 0x00E0 // Non-secure Active Priorities Register 0 65 #define GICC_NSAPR1 0x00E4 // Non-secure Active Priorities Register 1 66 #define GICC_NSAPR2 0x00E8 // Non-secure Active Priorities Register 2 67 #define GICC_NSAPR3 0x00EC // Non-secure Active Priorities Register 3 68 #define GICC_IIDR 0x00FC // CPU Interface Identification Register 69 #define GICC_DIR 0x1000 // Deactivate Interrupt Register 70 71 72 #define GICC_CTRL_V1_Enable __BIT(0) // GICv1 73 74 #define GICC_CTRL_V2_EnableGrp0 __BIT(0) // GICv2 !Secure | Secure 75 #define GICC_CTRL_V2_EnableGrp1 __BIT(1) // GICv2 !Secure | Secure 76 77 #define GICC_CTRL_V2S_EOImodeNS __BIT(9) // GICv2 Secure 78 #define GICC_CTRL_V2S_IRQBypDisGrp1 __BIT(6) // GICv2 Secure 79 #define GICC_CTRL_V2S_FIQBypDisGrp1 __BIT(4) // GICv2 Secure 80 81 #define GICC_CTRL_V2NS_EOImodeNS __BIT(10) // GICv2 !Secure 82 #define GICC_CTRL_V2NS_EOImodeS __BIT(9) // GICv2 !Secure 83 #define GICC_CTRL_V2NS_IRQBypDisGrp1 __BIT(8) // GICv2 !Secure 84 #define GICC_CTRL_V2NS_FIQBypDisGrp1 __BIT(7) // GICv2 !Secure 85 #define GICC_CTRL_V2NS_IRQBypDisGrp0 __BIT(6) // GICv2 !Secure 86 #define GICC_CTRL_V2NS_FIQBypDisGrp0 __BIT(5) // GICv2 !Secure 87 #define GICC_CTRL_V2NS_CPBR __BIT(4) // GICv2 !Secure 88 #define GICC_CTRL_V2NS_FIQEn __BIT(3) // GICv2 !Secure 89 #define GICC_CTRL_V2NS_AckCtl __BIT(2) // GICv2 !Secure 90 91 #define GICC_PMR_PRIORITY __BITS(7,0) 92 #define GICC_PMR_PRIORITIES 256 93 #define GICC_PMR_NS_PRIORITIES 128 94 #define GICC_PMR_NONSECURE 0x80 95 #define GICC_PMR_8_LEVELS 0x1f 96 #define GICC_PMR_16_LEVELS 0x0f 97 #define GICC_PMR_32_LEVELS 0x07 98 #define GICC_PMR_64_LEVELS 0x03 99 #define GICC_PMR_128_LEVELS 0x01 100 101 #define GICC_IAR_CPUID __BITS(12,10) 102 #define GICC_IAR_IRQ __BITS(9,0) 103 #define GICC_IAR_IRQ_SPURIOUS 1023 104 #define GICC_IAR_IRQ_SSPURIOUS 1022 // Secure 105 106 #define GICC_EOIR_CPUID __BITS(12,10) 107 #define GICC_EOIR_InterruptID __BITS(9,0) 108 109 #define GICC_HPPIR_CPUID __BITS(12,10) 110 #define GICC_HPPIR_PendIntID __BITS(9,0) 111 112 #define GICC_IIDR_ProductID __BITS(31,20) 113 #define GICC_IIDR_ArchVersion __BITS(19,16) 114 #define GICC_IIDR_Revision __BITS(15,12) 115 #define GICC_IIDR_Implementer __BITS(11,0) 116 117 #define GICC_DIR_CPUID __BITS(12,10) 118 #define GICC_DIR_InterruptID __BITS(9,0) 119 120 #define GICD_BASE 0x1000 // Offset from PeriphBase 121 122 #define GICD_CTRL 0x000 // Distributor Control Register 123 #define GICD_TYPER 0x004 // Interrupt Controller Type Register 124 #define GICD_IIDR 0x008 // Distributor Implementer Identification Register 125 #define GICD_IGROUPRn(n) (0x080+4*(n)) // Interrupt Group Registers 126 #define GICD_ISENABLERn(n) (0x100+4*(n)) // Interrupt Set-Enable Registers 127 #define GICD_ICENABLERn(n) (0x180+4*(n)) // Interrupt Clear-Enable Registers 128 #define GICD_ISPENDRn(n) (0x200+4*(n)) // Interrupt Set-Pending Registers 129 #define GICD_ICPENDRn(n) (0x280+4*(n)) // Interrupt Clear-Pending Registers 130 #define GICD_ISACTIVERn(n) (0x300+4*(n)) // GICv2 Interrupt Set-Active Registers 131 #define GICD_ICACTIVERn(n) (0x380+4*(n)) // Interrupt Clear-Active Registers 132 #define GICD_IPRIORITYRn(n) (0x400+4*(n)) // Interrupt Priority Registers 133 134 #define GICD_ITARGETSRn(n) (0x800+4*(n)) // Interrupt Processor Targets Registers 135 #define GICD_ICFGRn(n) (0xC00+4*(n)) // Interrupt Configuration Registers 136 #define GICD_IGRPMODRn(n) (0xD00+4*(n)) // Interrupt Group Modifier Registers 137 #define GICD_NSACRn(n) (0xE00+4*(n)) // Non-secure Access Control Registers, optional 138 #define GICD_SGIR 0xF00 // Software Generated Interrupt Register 139 #define GICD_CPENDSGIR(n) (0xF10+4*(n)) // SGI Clear-Pending Registers 140 #define GICD_SPENDSGIR(n) (0xF20+4*(n)) // SGI Set-Pending Registers 141 #define GICD_IROUTER(n) (0x6000+8*(n)) // Interrupt Routing Registers 142 143 #define GICD_CTRL_RWP __BIT(31) // GICv3 144 #define GICD_CTRL_E1NWF __BIT(7) // GICv3 145 #define GICD_CTRL_DS __BIT(6) // GICv3 146 #define GICD_CTRL_ARE_NS __BIT(4) // GICv3 147 #define GICD_CTRL_EnableGrp1S __BIT(2) // Secure only 148 #define GICD_CTRL_EnableGrp1A __BIT(1) // GICv3 149 #define GICD_CTRL_Enable __BIT(0) 150 151 #define GICD_TYPER_No1N __BIT(25) // GICv3 152 #define GICD_TYPER_A3V __BIT(24) // GICv3 153 #define GICD_TYPER_IDbits __BITS(23,19) // GICv3 154 #define GICD_TYPER_DVIS __BIT(18) // GICv3 155 #define GICD_TYPER_LPIS __BIT(17) // GICv3 156 #define GICD_TYPER_MBIS __BIT(16) // GICv3 157 #define GICD_TYPER_LSPI __BITS(15,11) 158 #define GICD_TYPER_SecurityExtn __BIT(10) 159 #define GICD_TYPER_CPUNumber __BITS(7,5) 160 #define GICD_TYPER_ITLinesNumber __BITS(4,0) // 32*(N+1) 161 #define GICD_TYPER_LINES(n) MIN(32*(__SHIFTOUT((n), GICD_TYPER_ITLinesNumber) + 1), 1020) 162 163 #define GICD_IIDR_ProductID __BITS(31,24) 164 #define GICD_IIDR_Variant __BITS(19,16) 165 #define GICD_IIDR_Revision __BITS(15,12) 166 #define GICD_IIDR_Implementer __BITS(11,0) 167 168 /* 169 * This register is byte-accessible but always little-endian. 170 */ 171 #define GICD_IPRIORITYR_Byte3 __BITS(31,24) 172 #define GICD_IPRIORITYR_Byte1 __BITS(23,16) 173 #define GICD_IPRIORITYR_Byte2 __BITS(15,8) 174 #define GICD_IPRIORITYR_Byte0 __BITS(7,0) 175 176 /* 177 * This register is byte-accessible but always little-endian. 178 */ 179 #define GICD_ITARGETSR_Byte3 __BITS(31,24) 180 #define GICD_ITARGETSR_Byte1 __BITS(23,16) 181 #define GICD_ITARGETSR_Byte2 __BITS(15,8) 182 #define GICD_ITARGETSR_Byte0 __BITS(7,0) 183 184 #define GICD_SGIR_TargetListFilter __BITS(25,24) 185 #define GICD_SGIR_TargetListFilter_List __SHIFTIN(0, GICD_SGIR_TargetListFilter) 186 #define GICD_SGIR_TargetListFilter_NotMe __SHIFTIN(1, GICD_SGIR_TargetListFilter) 187 #define GICD_SGIR_TargetListFilter_Me __SHIFTIN(2, GICD_SGIR_TargetListFilter) 188 #define GICD_SGIR_TargetList __BITS(23,16) 189 #define GICD_SGIR_NSATT __BIT(15) 190 #define GICD_SGIR_SGIINTID __BITS(3,0) 191 192 #define GICD_IROUTER_Aff3 __BITS(39,32) 193 #define GICD_IROUTER_Interrupt_Routing_mode __BIT(31) 194 #define GICD_IROUTER_Aff2 __BITS(23,16) 195 #define GICD_IROUTER_Aff1 __BITS(15,8) 196 #define GICD_IROUTER_Aff0 __BITS(7,0) 197 198 #define GICR_CTLR 0x0000 // Redistributor Control Register 199 #define GICR_IIDR 0x0004 // Implementor Identification Register 200 #define GICR_TYPER 0x0008 // Redistributor Type Register 201 #define GICR_STATUSR 0x0010 // Error Reporting Status Register, optional 202 #define GICR_WAKER 0x0014 // Redistributor Wake Register 203 #define GICR_SETLPIR 0x0040 // Set LPI Pending Register 204 #define GICR_CLRLPIR 0x0048 // Clear LPI Pending Register 205 #define GICR_PROPBASER 0x0070 // Redistributor Properties Base Address Register 206 #define GICR_PENDBASER 0x0078 // Redistributor LPI Pending Table Base Address Register 207 #define GICR_INVLPIR 0x00A0 // Redistributor Invalidate LPI Register 208 #define GICR_INVALLR 0x00B0 // Redistributor Invalidate All Register 209 #define GICR_SYNCR 0x00C0 // Redistributor Synchronize Register 210 211 #define GICR_IGROUPR0 0x10080 // Interrupt Group Register 0 212 #define GICR_ISENABLER0 0x10100 // Interrupt Set-Enable Register 0 213 #define GICR_ICENABLER0 0x10180 // Interrupt Clear-Enable Register 0 214 #define GICR_ISPENDR0 0x10200 // Interrupt Set-Pend Register 0 215 #define GICR_ICPENDR0 0x10280 // Interrupt Clear-Pend Register 0 216 #define GICR_ISACTIVER0 0x10300 // Interrupt Set-Active Register 0 217 #define GICR_ICACTIVER0 0x10380 // Interrupt Clear-Active Register 0 218 #define GICR_IPRIORITYRn(n) (0x10400+4*(n)) // Interrupt Priority Registers 219 #define GICR_ICFGRn(n) (0x10C00+4*(n)) // SGI (0) / PPI (1) Configuration Register 220 #define GICR_IGRPMODR0 0x10D00 // Interrupt Group Modifier Register 0 221 #define GICR_NSACR 0x10E00 // Non-Secure Access Control Register 222 223 #define GICR_CTLR_UWP __BIT(31) 224 #define GICR_CTLR_DPG1S __BIT(26) 225 #define GICR_CTLR_DPG1NS __BIT(25) 226 #define GICR_CTLR_DPG0 __BIT(24) 227 #define GICR_CTLR_RWP __BIT(3) 228 #define GICR_CTLR_Enable_LPIs __BIT(0) 229 230 #define GICR_TYPER_Affinity_Value __BITS(63,32) 231 #define GICR_TYPER_Affinity_Value_Aff3 __BITS(63,56) 232 #define GICR_TYPER_Affinity_Value_Aff2 __BITS(55,48) 233 #define GICR_TYPER_Affinity_Value_Aff1 __BITS(47,40) 234 #define GICR_TYPER_Affinity_Value_Aff0 __BITS(39,32) 235 #define GICR_TYPER_CommonLPIAff __BITS(25,24) 236 #define GICR_TYPER_Processor_Number __BITS(23,8) 237 #define GICR_TYPER_DPGS __BIT(5) 238 #define GICR_TYPER_Last __BIT(4) 239 #define GICR_TYPER_DirectLPI __BIT(3) 240 #define GICR_TYPER_VLPIS __BIT(1) 241 #define GICR_TYPER_PLPIS __BIT(0) 242 243 #define GICR_WAKER_ChildrenAsleep __BIT(2) 244 #define GICR_WAKER_ProcessorSleep __BIT(1) 245 246 #define GICR_PROPBASER_OuterCache __BITS(58,56) 247 #define GICR_PROPBASER_Physical_Address __BITS(51,12) 248 #define GICR_PROPBASER_Shareability __BITS(11,10) 249 #define GICR_PROPBASER_InnerCache __BITS(9,7) 250 #define GICR_PROPBASER_IDbits __BITS(4,0) 251 252 #define GICR_PENDBASER_PTZ __BIT(62) 253 #define GICR_PENDBASER_OuterCache __BITS(58,56) 254 #define GICR_PENDBASER_Physical_Address __BITS(51,16) 255 #define GICR_PENDBASER_Shareability __BITS(11,10) 256 #define GICR_PENDBASER_InnerCache __BITS(9,7) 257 258 #define GICR_Shareability_NS 0 // Non-shareable 259 #define GICR_Shareability_IS 1 // Inner Shareable 260 #define GICR_Shareability_OS 2 // Outer Shareable 261 262 #define GICR_Cache_DEVICE_nGnRnE 0 // Device-nGnRnE 263 #define GICR_Cache_NORMAL_NC 1 // Non-cacheable 264 #define GICR_Cache_NORMAL_RA_WT 2 // Cacheable Read-allocate, Write-through 265 #define GICR_Cache_NORMAL_RA_WB 3 // Cacheable Read-allocate, Write-back 266 #define GICR_Cache_NORMAL_WA_WT 4 // Cacheable Write-allocate, Write-through 267 #define GICR_Cache_NORMAL_WA_WB 5 // Cacheable Write-allocate, Write-back 268 #define GICR_Cache_NORMAL_RA_WA_WT 6 // Cacheable Read-allocate, Write-allocate, Write-through 269 #define GICR_Cache_NORMAL_RA_WA_WB 7 // Cacheable Read-allocate, Write-allocate, Write-back 270 271 /* 272 * GICv3 Locality-specific Peripheral Interrupts 273 */ 274 275 #define GIC_LPI_BASE 0x2000 // Base LPI INTID 276 277 #define GIC_LPICONF_Priority __BITS(7,2) 278 #define GIC_LPICONF_Res1 __BIT(1) 279 #define GIC_LPICONF_Enable __BIT(0) 280 281 /* 282 * GICv1 names 283 */ 284 #define GICv1_ICDDCR GICD_CTLR 285 #define GICv1_ICDICTR GICD_TYPER 286 #define GICv1_ICDIIDR GICD_IIDR 287 #define GICv1_ICDISRn(n) GICD_IGROUPRn(n) 288 #define GICv1_ICDABRn(n) GICD_ISACTIVERn(n) 289 #define GICv1_ICDISERn(n) GICD_ISENABLERn(n) 290 #define GICv1_ICDICERn(n) GICD_ICENABLERn(n) 291 #define GICv1_ICDISPRn(n) GICD_ISPENDRn(n) 292 #define GICv1_ICDICPRn(n) GICD_ICPENDRn(n) 293 #define GICv1_ICDIPRn(n) GICD_IPRIORITYRn(n) 294 #define GICv1_ICDIPTRn(n) GICD_ITARGETSRn(n) 295 #define GICv1_ICDICRn(n) GICD_ICFGRn(n) 296 #define GICv1_ICDSGIR GICD_SGIR 297 298 #define GICv1_ICCICR GICC_CTLR 299 #define GICv1_ICCPMR GICC_PMR 300 #define GICv1_ICCBPR GICC_BPR 301 #define GICv1_ICCIAR GICC_IAR 302 #define GICv1_ICCEOIR GICC_EOIR 303 #define GICv1_ICCRPR GICC_RPR 304 #define GICv1_ICCABPR GICC_ABPR 305 #define GICv1_ICCHPIR GICC_HPPIR 306 #define GICv1_ICCIIDR GICC_IIDR 307 308 /* 309 * GICv2m (MSI) 310 */ 311 312 #define GIC_MSI_TYPER 0x0008 313 #define GIC_MSI_SETSPI 0x0040 314 #define GIC_MSI_PIDR2 0x0fe8 315 #define GIC_MSI_IIDR 0x0ffc 316 317 #define GIC_MSI_TYPER_BASE __BITS(25,16) // Starting SPI of MSIs 318 #define GIC_MSI_TYPER_NUMBER __BITS(9,0) // Count of MSIs 319 320 /* 321 * GICv3 Interrupt Translation Service (ITS) 322 */ 323 324 #define GITS_CTLR 0x00000 // ITS control register 325 #define GITS_IIDR 0x00004 // ITS Identification register 326 #define GITS_TYPER 0x00008 // ITS Type register 327 #define GITS_CBASER 0x00080 // ITS Command Queue Descriptor 328 #define GITS_CWRITER 0x00088 // ITS Write register 329 #define GITS_CREADR 0x00090 // ITS Read register 330 #define GITS_BASERn(n) (0x00100+8*(n)) // ITS Translation Table Descriptors 331 #define GITS_PIDR2 0x0FFE8 // ITS Peripheral ID2 Register 332 #define GITS_TRANSLATER 0x10040 // ITS Translation register 333 334 #define GITS_CTLR_Quiescent __BIT(31) 335 #define GITS_CTLR_ITS_Number __BITS(7,4) 336 #define GITS_CTLR_ImDe __BIT(1) 337 #define GITS_CTLR_Enabled __BIT(0) 338 339 #define GITS_IIDR_ProductID __BITS(31,24) 340 #define GITS_IIDR_Variant __BITS(19,16) 341 #define GITS_IIDR_Revision __BITS(15,12) 342 #define GITS_IIDR_Implementor __BITS(11,0) 343 344 #define GITS_TYPER_VMOVP __BIT(37) 345 #define GITS_TYPER_CIL __BIT(36) 346 #define GITS_TYPER_CIDbits __BITS(35,32) 347 #define GITS_TYPER_HCC __BITS(31,24) 348 #define GITS_TYPER_PTA __BIT(19) 349 #define GITS_TYPER_SEIS __BIT(18) 350 #define GITS_TYPER_Devbits __BITS(17,13) 351 #define GITS_TYPER_ID_bits __BITS(12,8) 352 #define GITS_TYPER_ITT_entry_size __BITS(7,4) 353 #define GITS_TYPER_CCT __BIT(2) 354 #define GITS_TYPER_Virtual __BIT(1) 355 #define GITS_TYPER_Physical __BIT(0) 356 357 #define GITS_CBASER_Valid __BIT(63) 358 #define GITS_CBASER_InnerCache __BITS(61,59) 359 #define GITS_CBASER_OuterCache __BITS(55,53) 360 #define GITS_CBASER_Physical_Address __BITS(51,12) 361 #define GITS_CBASER_Shareability __BITS(11,10) 362 #define GITS_CBASER_Size __BITS(7,0) 363 364 #define GITS_CWRITER_Offset __BITS(19,5) 365 #define GITS_CWRITER_Retry __BIT(0) 366 367 #define GITS_CREADR_Offset __BITS(19,5) 368 #define GITS_CREADR_Stalled __BIT(0) 369 370 #define GITS_BASER_Valid __BIT(63) 371 #define GITS_BASER_Indirect __BIT(62) 372 #define GITS_BASER_InnerCache __BITS(61,59) 373 #define GITS_BASER_Type __BITS(58,56) 374 #define GITS_BASER_OuterCache __BITS(55,53) 375 #define GITS_BASER_Entry_Size __BITS(52,48) 376 #define GITS_BASER_Physical_Address __BITS(47,12) 377 #define GITS_BASER_Shareability __BITS(11,10) 378 #define GITS_BASER_Page_Size __BITS(9,8) 379 #define GITS_BASER_Size __BITS(7,0) 380 381 #define GITS_Shareability_NS 0 // Non-shareable 382 #define GITS_Shareability_IS 1 // Inner Shareable 383 #define GITS_Shareability_OS 2 // Outer Shareable 384 385 #define GITS_Cache_DEVICE_nGnRnE 0 // Device-nGnRnE 386 #define GITS_Cache_NORMAL_NC 1 // Non-cacheable 387 #define GITS_Cache_NORMAL_RA_WT 2 // Cacheable Read-allocate, Write-through 388 #define GITS_Cache_NORMAL_RA_WB 3 // Cacheable Read-allocate, Write-back 389 #define GITS_Cache_NORMAL_WA_WT 4 // Cacheable Write-allocate, Write-through 390 #define GITS_Cache_NORMAL_WA_WB 5 // Cacheable Write-allocate, Write-back 391 #define GITS_Cache_NORMAL_RA_WA_WT 6 // Cacheable Read-allocate, Write-allocate, Write-through 392 #define GITS_Cache_NORMAL_RA_WA_WB 7 // Cacheable Read-allocate, Write-allocate, Write-back 393 394 #define GITS_Type_Unimplemented 0 // Unimplemented 395 #define GITS_Type_Devices 1 // Devices table 396 #define GITS_Type_vPEs 2 // vPEs table 397 #define GITS_Type_InterruptCollections 4 // Interrupt collections table 398 399 #define GITS_Page_Size_4KB 0 400 #define GITS_Page_Size_16KB 1 401 #define GITS_Page_Size_64KB 2 402 403 struct gicv3_its_command { 404 uint64_t dw[4]; 405 }; 406 407 #define GITS_CMD_MOVI 0x01 408 #define GITS_CMD_INT 0x03 409 #define GITS_CMD_CLEAR 0x04 410 #define GITS_CMD_SYNC 0x05 411 #define GITS_CMD_MAPD 0x08 412 #define GITS_CMD_MAPC 0x09 413 #define GITS_CMD_MAPTI 0x0A 414 #define GITS_CMD_MAPI 0x0B 415 #define GITS_CMD_INV 0x0C 416 #define GITS_CMD_INVALL 0x0D 417 #define GITS_CMD_MOVALL 0x0E 418 #define GITS_CMD_DISCARD 0x0F 419 #define GITS_CMD_VMOVI 0x21 420 #define GITS_CMD_VMOVP 0x22 421 #define GITS_CMD_VSYNC 0x25 422 #define GITS_CMD_VMAPP 0x29 423 #define GITS_CMD_VMAPTI 0x2A 424 #define GITS_CMD_VMAPI 0x2B 425 #define GITS_CMD_VINVALL 0x2D 426 427 #endif /* !_ARM_CORTEX_GICREG_H_ */ 428
Indexes created Sat Sep 20 22:09:52 GMT 2025