1 /* $NetBSD: vega10_hwmgr.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef _VEGA10_HWMGR_H_ 27 #define _VEGA10_HWMGR_H_ 28 29 #include "hwmgr.h" 30 #include "smu9_driver_if.h" 31 #include "ppatomctrl.h" 32 #include "ppatomfwctrl.h" 33 #include "vega10_ppsmc.h" 34 #include "vega10_powertune.h" 35 36 #define VEGA10_MAX_HARDWARE_POWERLEVELS 2 37 38 #define WaterMarksExist 1 39 #define WaterMarksLoaded 2 40 41 enum { 42 GNLD_DPM_PREFETCHER = 0, 43 GNLD_DPM_GFXCLK, 44 GNLD_DPM_UCLK, 45 GNLD_DPM_SOCCLK, 46 GNLD_DPM_UVD, 47 GNLD_DPM_VCE, 48 GNLD_ULV, 49 GNLD_DPM_MP0CLK, 50 GNLD_DPM_LINK, 51 GNLD_DPM_DCEFCLK, 52 GNLD_AVFS, 53 GNLD_DS_GFXCLK, 54 GNLD_DS_SOCCLK, 55 GNLD_DS_LCLK, 56 GNLD_PPT, 57 GNLD_TDC, 58 GNLD_THERMAL, 59 GNLD_GFX_PER_CU_CG, 60 GNLD_RM, 61 GNLD_DS_DCEFCLK, 62 GNLD_ACDC, 63 GNLD_VR0HOT, 64 GNLD_VR1HOT, 65 GNLD_FW_CTF, 66 GNLD_LED_DISPLAY, 67 GNLD_FAN_CONTROL, 68 GNLD_FEATURE_FAST_PPT_BIT, 69 GNLD_DIDT, 70 GNLD_ACG, 71 GNLD_PCC_LIMIT, 72 GNLD_FEATURES_MAX 73 }; 74 75 #define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1) 76 77 #define SMC_DPM_FEATURES 0x30F 78 79 struct smu_features { 80 bool supported; 81 bool enabled; 82 uint32_t smu_feature_id; 83 uint32_t smu_feature_bitmap; 84 }; 85 86 struct vega10_performance_level { 87 uint32_t soc_clock; 88 uint32_t gfx_clock; 89 uint32_t mem_clock; 90 }; 91 92 struct vega10_bacos { 93 uint32_t baco_flags; 94 /* struct vega10_performance_level performance_level; */ 95 }; 96 97 struct vega10_uvd_clocks { 98 uint32_t vclk; 99 uint32_t dclk; 100 }; 101 102 struct vega10_vce_clocks { 103 uint32_t evclk; 104 uint32_t ecclk; 105 }; 106 107 struct vega10_power_state { 108 uint32_t magic; 109 struct vega10_uvd_clocks uvd_clks; 110 struct vega10_vce_clocks vce_clks; 111 uint16_t performance_level_count; 112 bool dc_compatible; 113 uint32_t sclk_threshold; 114 struct vega10_performance_level performance_levels[VEGA10_MAX_HARDWARE_POWERLEVELS]; 115 }; 116 117 struct vega10_dpm_level { 118 bool enabled; 119 uint32_t value; 120 uint32_t param1; 121 }; 122 123 #define VEGA10_MAX_DEEPSLEEP_DIVIDER_ID 5 124 #define MAX_REGULAR_DPM_NUMBER 8 125 #define MAX_PCIE_CONF 2 126 #define VEGA10_MINIMUM_ENGINE_CLOCK 2500 127 128 struct vega10_dpm_state { 129 uint32_t soft_min_level; 130 uint32_t soft_max_level; 131 uint32_t hard_min_level; 132 uint32_t hard_max_level; 133 }; 134 135 struct vega10_single_dpm_table { 136 uint32_t count; 137 struct vega10_dpm_state dpm_state; 138 struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 139 }; 140 141 struct vega10_pcie_table { 142 uint16_t count; 143 uint8_t pcie_gen[MAX_PCIE_CONF]; 144 uint8_t pcie_lane[MAX_PCIE_CONF]; 145 uint32_t lclk[MAX_PCIE_CONF]; 146 }; 147 148 struct vega10_dpm_table { 149 struct vega10_single_dpm_table soc_table; 150 struct vega10_single_dpm_table gfx_table; 151 struct vega10_single_dpm_table mem_table; 152 struct vega10_single_dpm_table eclk_table; 153 struct vega10_single_dpm_table vclk_table; 154 struct vega10_single_dpm_table dclk_table; 155 struct vega10_single_dpm_table dcef_table; 156 struct vega10_single_dpm_table pixel_table; 157 struct vega10_single_dpm_table display_table; 158 struct vega10_single_dpm_table phy_table; 159 struct vega10_pcie_table pcie_table; 160 }; 161 162 #define VEGA10_MAX_LEAKAGE_COUNT 8 163 struct vega10_leakage_voltage { 164 uint16_t count; 165 uint16_t leakage_id[VEGA10_MAX_LEAKAGE_COUNT]; 166 uint16_t actual_voltage[VEGA10_MAX_LEAKAGE_COUNT]; 167 }; 168 169 struct vega10_display_timing { 170 uint32_t min_clock_in_sr; 171 uint32_t num_existing_displays; 172 }; 173 174 struct vega10_dpmlevel_enable_mask { 175 uint32_t uvd_dpm_enable_mask; 176 uint32_t vce_dpm_enable_mask; 177 uint32_t acp_dpm_enable_mask; 178 uint32_t samu_dpm_enable_mask; 179 uint32_t sclk_dpm_enable_mask; 180 uint32_t mclk_dpm_enable_mask; 181 }; 182 183 struct vega10_vbios_boot_state { 184 bool bsoc_vddc_lock; 185 uint16_t vddc; 186 uint16_t vddci; 187 uint16_t mvddc; 188 uint16_t vdd_gfx; 189 uint32_t gfx_clock; 190 uint32_t mem_clock; 191 uint32_t soc_clock; 192 uint32_t dcef_clock; 193 }; 194 195 struct vega10_smc_state_table { 196 uint32_t soc_boot_level; 197 uint32_t gfx_boot_level; 198 uint32_t dcef_boot_level; 199 uint32_t mem_boot_level; 200 uint32_t uvd_boot_level; 201 uint32_t vce_boot_level; 202 uint32_t gfx_max_level; 203 uint32_t mem_max_level; 204 uint32_t soc_max_level; 205 uint8_t vr_hot_gpio; 206 uint8_t ac_dc_gpio; 207 uint8_t therm_out_gpio; 208 uint8_t therm_out_polarity; 209 uint8_t therm_out_mode; 210 PPTable_t pp_table; 211 Watermarks_t water_marks_table; 212 AvfsTable_t avfs_table; 213 AvfsFuseOverride_t avfs_fuse_override_table; 214 }; 215 216 struct vega10_mclk_latency_entries { 217 uint32_t frequency; 218 uint32_t latency; 219 }; 220 221 struct vega10_mclk_latency_table { 222 uint32_t count; 223 struct vega10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 224 }; 225 226 struct vega10_registry_data { 227 uint8_t ac_dc_switch_gpio_support; 228 uint8_t avfs_support; 229 uint8_t cac_support; 230 uint8_t clock_stretcher_support; 231 uint8_t db_ramping_support; 232 uint8_t didt_mode; 233 uint8_t didt_support; 234 uint8_t edc_didt_support; 235 uint8_t dynamic_state_patching_support; 236 uint8_t enable_pkg_pwr_tracking_feature; 237 uint8_t enable_tdc_limit_feature; 238 uint32_t fast_watermark_threshold; 239 uint8_t force_dpm_high; 240 uint8_t fuzzy_fan_control_support; 241 uint8_t long_idle_baco_support; 242 uint8_t mclk_dpm_key_disabled; 243 uint8_t od_state_in_dc_support; 244 uint8_t pcieLaneOverride; 245 uint8_t pcieSpeedOverride; 246 uint32_t pcieClockOverride; 247 uint8_t pcie_dpm_key_disabled; 248 uint8_t dcefclk_dpm_key_disabled; 249 uint8_t power_containment_support; 250 uint8_t ppt_support; 251 uint8_t prefetcher_dpm_key_disabled; 252 uint8_t quick_transition_support; 253 uint8_t regulator_hot_gpio_support; 254 uint8_t sclk_deep_sleep_support; 255 uint8_t sclk_dpm_key_disabled; 256 uint8_t sclk_from_vbios; 257 uint8_t sclk_throttle_low_notification; 258 uint8_t show_baco_dbg_info; 259 uint8_t skip_baco_hardware; 260 uint8_t socclk_dpm_key_disabled; 261 uint8_t spll_shutdown_support; 262 uint8_t sq_ramping_support; 263 uint32_t stable_pstate_sclk_dpm_percentage; 264 uint8_t tcp_ramping_support; 265 uint8_t tdc_support; 266 uint8_t td_ramping_support; 267 uint8_t dbr_ramping_support; 268 uint8_t gc_didt_support; 269 uint8_t psm_didt_support; 270 uint8_t thermal_out_gpio_support; 271 uint8_t thermal_support; 272 uint8_t fw_ctf_enabled; 273 uint8_t fan_control_support; 274 uint8_t ulps_support; 275 uint8_t ulv_support; 276 uint32_t vddc_vddci_delta; 277 uint8_t odn_feature_enable; 278 uint8_t disable_water_mark; 279 uint8_t zrpm_stop_temp; 280 uint8_t zrpm_start_temp; 281 uint8_t led_dpm_enabled; 282 uint8_t vr0hot_enabled; 283 uint8_t vr1hot_enabled; 284 }; 285 286 struct vega10_odn_clock_voltage_dependency_table { 287 uint32_t count; 288 struct phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER]; 289 }; 290 291 struct vega10_odn_vddc_lookup_table { 292 uint32_t count; 293 struct phm_ppt_v1_voltage_lookup_record entries[MAX_REGULAR_DPM_NUMBER]; 294 }; 295 296 struct vega10_odn_dpm_table { 297 struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_sclk; 298 struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_mclk; 299 struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_socclk; 300 struct vega10_odn_vddc_lookup_table vddc_lookup_table; 301 uint32_t max_vddc; 302 uint32_t min_vddc; 303 }; 304 305 struct vega10_odn_fan_table { 306 uint32_t target_fan_speed; 307 uint32_t target_temperature; 308 uint32_t min_performance_clock; 309 uint32_t min_fan_limit; 310 }; 311 312 struct vega10_hwmgr { 313 struct vega10_dpm_table dpm_table; 314 struct vega10_dpm_table golden_dpm_table; 315 struct vega10_registry_data registry_data; 316 struct vega10_vbios_boot_state vbios_boot_state; 317 struct vega10_mclk_latency_table mclk_latency_table; 318 319 struct vega10_leakage_voltage vddc_leakage; 320 321 uint32_t vddc_control; 322 struct pp_atomfwctrl_voltage_table vddc_voltage_table; 323 uint32_t mvdd_control; 324 struct pp_atomfwctrl_voltage_table mvdd_voltage_table; 325 uint32_t vddci_control; 326 struct pp_atomfwctrl_voltage_table vddci_voltage_table; 327 328 uint32_t active_auto_throttle_sources; 329 uint32_t water_marks_bitmap; 330 struct vega10_bacos bacos; 331 332 struct vega10_odn_dpm_table odn_dpm_table; 333 struct vega10_odn_fan_table odn_fan_table; 334 335 /* ---- General data ---- */ 336 uint8_t need_update_dpm_table; 337 338 bool cac_enabled; 339 bool battery_state; 340 bool is_tlu_enabled; 341 342 uint32_t low_sclk_interrupt_threshold; 343 344 uint32_t total_active_cus; 345 346 struct vega10_display_timing display_timing; 347 348 /* ---- Vega10 Dyn Register Settings ---- */ 349 350 uint32_t debug_settings; 351 uint32_t lowest_uclk_reserved_for_ulv; 352 uint32_t gfxclk_average_alpha; 353 uint32_t socclk_average_alpha; 354 uint32_t uclk_average_alpha; 355 uint32_t gfx_activity_average_alpha; 356 uint32_t display_voltage_mode; 357 uint32_t dcef_clk_quad_eqn_a; 358 uint32_t dcef_clk_quad_eqn_b; 359 uint32_t dcef_clk_quad_eqn_c; 360 uint32_t disp_clk_quad_eqn_a; 361 uint32_t disp_clk_quad_eqn_b; 362 uint32_t disp_clk_quad_eqn_c; 363 uint32_t pixel_clk_quad_eqn_a; 364 uint32_t pixel_clk_quad_eqn_b; 365 uint32_t pixel_clk_quad_eqn_c; 366 uint32_t phy_clk_quad_eqn_a; 367 uint32_t phy_clk_quad_eqn_b; 368 uint32_t phy_clk_quad_eqn_c; 369 370 /* ---- Thermal Temperature Setting ---- */ 371 struct vega10_dpmlevel_enable_mask dpm_level_enable_mask; 372 373 /* ---- Power Gating States ---- */ 374 bool uvd_power_gated; 375 bool vce_power_gated; 376 bool need_long_memory_training; 377 378 /* Internal settings to apply the application power optimization parameters */ 379 uint32_t disable_dpm_mask; 380 381 /* ---- SMU9 ---- */ 382 struct smu_features smu_features[GNLD_FEATURES_MAX]; 383 struct vega10_smc_state_table smc_state_table; 384 385 uint32_t config_telemetry; 386 uint32_t acg_loop_state; 387 uint32_t mem_channels; 388 uint8_t custom_profile_mode[4]; 389 }; 390 391 #define VEGA10_DPM2_NEAR_TDP_DEC 10 392 #define VEGA10_DPM2_ABOVE_SAFE_INC 5 393 #define VEGA10_DPM2_BELOW_SAFE_INC 20 394 395 #define VEGA10_DPM2_LTA_WINDOW_SIZE 7 396 397 #define VEGA10_DPM2_LTS_TRUNCATE 0 398 399 #define VEGA10_DPM2_TDP_SAFE_LIMIT_PERCENT 80 400 401 #define VEGA10_DPM2_MAXPS_PERCENT_M 90 402 #define VEGA10_DPM2_MAXPS_PERCENT_H 90 403 404 #define VEGA10_DPM2_PWREFFICIENCYRATIO_MARGIN 50 405 406 #define VEGA10_DPM2_SQ_RAMP_MAX_POWER 0x3FFF 407 #define VEGA10_DPM2_SQ_RAMP_MIN_POWER 0x12 408 #define VEGA10_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 409 #define VEGA10_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E 410 #define VEGA10_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF 411 412 #define VEGA10_VOLTAGE_CONTROL_NONE 0x0 413 #define VEGA10_VOLTAGE_CONTROL_BY_GPIO 0x1 414 #define VEGA10_VOLTAGE_CONTROL_BY_SVID2 0x2 415 #define VEGA10_VOLTAGE_CONTROL_MERGED 0x3 416 /* To convert to Q8.8 format for firmware */ 417 #define VEGA10_Q88_FORMAT_CONVERSION_UNIT 256 418 419 #define VEGA10_UNUSED_GPIO_PIN 0x7F 420 421 #define VEGA10_THERM_OUT_MODE_DISABLE 0x0 422 #define VEGA10_THERM_OUT_MODE_THERM_ONLY 0x1 423 #define VEGA10_THERM_OUT_MODE_THERM_VRHOT 0x2 424 425 #define PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT 0xffffffff 426 #define PPREGKEY_VEGA10QUADRATICEQUATION_DFLT 0xffffffff 427 428 #define PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 429 #define PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 430 #define PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 431 #define PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 432 433 #define VEGA10_UMD_PSTATE_GFXCLK_LEVEL 0x3 434 #define VEGA10_UMD_PSTATE_SOCCLK_LEVEL 0x3 435 #define VEGA10_UMD_PSTATE_MCLK_LEVEL 0x2 436 437 extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); 438 extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr); 439 extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr); 440 extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr); 441 extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display); 442 int vega10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input); 443 int vega10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate); 444 int vega10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate); 445 int vega10_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate); 446 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); 447 448 #endif /* _VEGA10_HWMGR_H_ */ 449
Indexes created Thu Sep 25 16:09:42 GMT 2025