1 /* $NetBSD: gk20a.h,v 1.2 2021/12/18 23:45:39 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef __NVKM_CLK_GK20A_H__ 27 #define __NVKM_CLK_GK20A_H__ 28 29 #define KHZ (1000) 30 #define MHZ (KHZ * 1000) 31 32 #define MASK(w) ((1 << (w)) - 1) 33 34 #define GK20A_CLK_GPC_MDIV 1000 35 36 #define SYS_GPCPLL_CFG_BASE 0x00137000 37 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) 38 #define GPCPLL_CFG_ENABLE BIT(0) 39 #define GPCPLL_CFG_IDDQ BIT(1) 40 #define GPCPLL_CFG_LOCK_DET_OFF BIT(4) 41 #define GPCPLL_CFG_LOCK BIT(17) 42 43 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) 44 #define GPCPLL_CFG2_SETUP2_SHIFT 16 45 #define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 46 47 #define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) 48 #define GPCPLL_CFG3_VCO_CTRL_SHIFT 0 49 #define GPCPLL_CFG3_VCO_CTRL_WIDTH 9 50 #define GPCPLL_CFG3_VCO_CTRL_MASK \ 51 (MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT) 52 #define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 53 #define GPCPLL_CFG3_PLL_STEPB_WIDTH 8 54 55 #define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) 56 #define GPCPLL_COEFF_M_SHIFT 0 57 #define GPCPLL_COEFF_M_WIDTH 8 58 #define GPCPLL_COEFF_N_SHIFT 8 59 #define GPCPLL_COEFF_N_WIDTH 8 60 #define GPCPLL_COEFF_N_MASK \ 61 (MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT) 62 #define GPCPLL_COEFF_P_SHIFT 16 63 #define GPCPLL_COEFF_P_WIDTH 6 64 65 #define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) 66 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 67 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 68 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 69 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 70 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 71 72 #define GPC_BCAST_GPCPLL_CFG_BASE 0x00132800 73 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCAST_GPCPLL_CFG_BASE + 0xa0) 74 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 75 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ 76 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) 77 78 #define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) 79 #define SEL_VCO_GPC2CLK_OUT_SHIFT 0 80 81 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) 82 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 83 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 84 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 85 #define GPC2CLK_OUT_VCODIV_WIDTH 6 86 #define GPC2CLK_OUT_VCODIV_SHIFT 8 87 #define GPC2CLK_OUT_VCODIV1 0 88 #define GPC2CLK_OUT_VCODIV2 2 89 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ 90 GPC2CLK_OUT_VCODIV_SHIFT) 91 #define GPC2CLK_OUT_BYPDIV_WIDTH 6 92 #define GPC2CLK_OUT_BYPDIV_SHIFT 0 93 #define GPC2CLK_OUT_BYPDIV31 0x3c 94 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ 95 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ 96 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ 97 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) 98 #define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ 99 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ 100 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ 101 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) 102 103 /* All frequencies in Khz */ 104 struct gk20a_clk_pllg_params { 105 u32 min_vco, max_vco; 106 u32 min_u, max_u; 107 u32 min_m, max_m; 108 u32 min_n, max_n; 109 u32 min_pl, max_pl; 110 }; 111 112 struct gk20a_pll { 113 u32 m; 114 u32 n; 115 u32 pl; 116 }; 117 118 struct gk20a_clk { 119 struct nvkm_clk base; 120 const struct gk20a_clk_pllg_params *params; 121 struct gk20a_pll pll; 122 u32 parent_rate; 123 124 u32 (*div_to_pl)(u32); 125 u32 (*pl_to_div)(u32); 126 }; 127 #define gk20a_clk(p) container_of((p), struct gk20a_clk, base) 128 129 u32 gk20a_pllg_calc_rate(struct gk20a_clk *, struct gk20a_pll *); 130 int gk20a_pllg_calc_mnp(struct gk20a_clk *, unsigned long, struct gk20a_pll *); 131 void gk20a_pllg_read_mnp(struct gk20a_clk *, struct gk20a_pll *); 132 void gk20a_pllg_write_mnp(struct gk20a_clk *, const struct gk20a_pll *); 133 134 static inline bool 135 gk20a_pllg_is_enabled(struct gk20a_clk *clk) 136 { 137 struct nvkm_device *device = clk->base.subdev.device; 138 u32 val; 139 140 val = nvkm_rd32(device, GPCPLL_CFG); 141 return val & GPCPLL_CFG_ENABLE; 142 } 143 144 static inline u32 145 gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll) 146 { 147 return DIV_ROUND_UP(pll->m * clk->params->min_vco, 148 clk->parent_rate / KHZ); 149 } 150 151 int gk20a_clk_ctor(struct nvkm_device *, int, const struct nvkm_clk_func *, 152 const struct gk20a_clk_pllg_params *, struct gk20a_clk *); 153 void gk20a_clk_fini(struct nvkm_clk *); 154 int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src); 155 int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *); 156 int gk20a_clk_prog(struct nvkm_clk *); 157 void gk20a_clk_tidy(struct nvkm_clk *); 158 159 int gk20a_clk_setup_slide(struct gk20a_clk *); 160 161 #endif 162
Indexes created Sun Sep 21 14:09:52 GMT 2025