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      1 /*	$NetBSD: ap_ms104_sh4reg.h,v 1.2 2012/01/21 19:44:29 nonaka Exp $	*/
      2 
      3 /*-
      4  * Copyright (C) 2009 NONAKA Kimihiro <nonaka (at) netbsd.org>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 #ifndef	AP_MS104_SH4REG_H_
     29 #define	AP_MS104_SH4REG_H_
     30 
     31 #define	EXTINTR_MASK1		0xa4000000	/* R/W: 8bit */
     32 #define	EXTINTR_MASK2		0xa4100000	/* R/W: 8bit */
     33 #define	EXTINTR_MASK3		0xa4200000	/* R/W: 8bit */
     34 #define	EXTINTR_MASK4		0xa4300000	/* R/W: 8bit */
     35 #define	EXTINTR_STAT1		0xa4400000	/* R: 8bit */
     36 #define	EXTINTR_STAT2		0xa4500000	/* R: 8bit */
     37 #define	EXTINTR_STAT3		0xa4600000	/* R: 8bit */
     38 #define	EXTINTR_STAT4		0xa4700000	/* R: 8bit */
     39 #define	CFBUS_CTRL		0xa4800000	/* W: 8bit */
     40 
     41 /* EXTINTR_MASK1 */
     42 #define	MASK1_INT14		(1U << 0)
     43 #define	MASK1_INT13		(1U << 1)
     44 #define	MASK1_INT12		(1U << 2)
     45 #define	MASK1_INT11		(1U << 3)
     46 
     47 /* EXTINTR_MASK2 */
     48 #define	MASK2_INT10		(1U << 0)
     49 #define	MASK2_INT9		(1U << 1)
     50 #define	MASK2_INT8		(1U << 2)
     51 #define	MASK2_INT7		(1U << 3)
     52 
     53 /* EXTINTR_MASK3 */
     54 #define	MASK3_INT6		(1U << 0)
     55 #define	MASK3_INT5		(1U << 1)
     56 #define	MASK3_INT4		(1U << 2)
     57 #define	MASK3_INT3		(1U << 3)
     58 
     59 /* EXTINTR_MASK4 */
     60 #define	MASK4_INT2		(1U << 0)
     61 #define	MASK4_INT1		(1U << 1)
     62 
     63 /* EXTINTR_STAT1 */
     64 #define	STAT1_INT14		(1U << 0)
     65 #define	STAT1_INT13		(1U << 1)
     66 #define	STAT1_INT12		(1U << 2)
     67 #define	STAT1_INT11		(1U << 3)
     68 
     69 /* EXTINTR_STAT2 */
     70 #define	STAT2_INT10		(1U << 0)
     71 #define	STAT2_INT9		(1U << 1)
     72 #define	STAT2_INT8		(1U << 2)
     73 #define	STAT2_INT7		(1U << 3)
     74 
     75 /* EXTINTR_STAT3 */
     76 #define	STAT3_INT6		(1U << 0)
     77 #define	STAT3_INT5		(1U << 1)
     78 #define	STAT3_INT4		(1U << 2)
     79 #define	STAT3_INT3		(1U << 3)
     80 
     81 /* EXTINTR_STAT4 */
     82 #define	STAT4_INT2		(1U << 0)
     83 #define	STAT4_INT1		(1U << 1)
     84 
     85 /* CFBUS_CTRL */
     86 #define	CFBUS_CTRL_WAIT		(1U << 0)
     87 #define	CFBUS_CTRL_IOIS16	(1U << 1)
     88 
     89 /* external intr# */
     90 #define	EXTINTR_INTR_SMC91C111	8
     91 #define	EXTINTR_INTR_CFIREQ	12
     92 #define	EXTINTR_INTR_RTC	14
     93 
     94 /* GPIO pin# */
     95 #define	GPIO_PIN_CARD_CD	8	/* In */
     96 #define	GPIO_PIN_CARD_PON	9	/* Out */
     97 #define	GPIO_PIN_CARD_RESET	10	/* Out */
     98 #define	GPIO_PIN_CARD_ENABLE	11	/* Out */
     99 #define	GPIO_PIN_RTC_SIO	13	/* In/Out */
    100 #define	GPIO_PIN_RTC_SCLK	14	/* Out */
    101 #define	GPIO_PIN_RTC_CE		15	/* Out */
    102 
    103 #endif	/* AP_MS104_SH4REG_H_ */
    104