| /src/crypto/external/apache2/openssl/dist/crypto/bn/asm/ |
| ppc64-mont-fixed.pl | 332 package Mont::GPR;
460 our @ISA = ('Mont::GPR');
568 $mont = new Mont::GPR(6);
|
| /src/sys/arch/sparc/sparc/ |
| emul.c | 50 #define GPR(tf, i) ((int32_t *) &tf->tf_global)[i]
73 *(int32_t *) val = GPR(tf, i);
89 GPR(tf, i) = *(const int32_t *) val;
|
| /src/sys/arch/sparc64/sparc64/ |
| emul.c | 51 #define GPR(tf, i) ((int32_t *)(u_long)&tf->tf_global)[i]
74 *(int32_t *) val = GPR(tf, i);
90 GPR(tf, i) = *(const int32_t *) val;
|
| /src/bin/ed/ |
| ed.h | 64 #define GPR 002 /* print after command */
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonGenPredicate.cpp | 428 RegisterSubReg GPR = MI->getOperand(i);
429 RegisterSubReg Pred = getPredRegFor(GPR);
466 // a gpr register holding a result of a convertible instruction. After
468 // copied back into the original gpr.
|
| /src/sys/arch/evbarm/stand/boot2440/ |
| dm9000.c | 89 #define GPR 0x1f /* gpio control */
204 CSR_WRITE_1(l, GPR, GPR_PHYPWROFF);
217 CSR_WRITE_1(l, GPR, 0);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| MVETPAndVPTOptimisationsPass.cpp | 905 Register GPR = Copy->getOperand(1).getReg();
908 auto getImm = [&](Register GPR) -> unsigned {
909 MachineInstr *Def = MRI->getVRegDef(GPR);
915 unsigned Imm = getImm(GPR);
926 if (MRI->hasOneUse(GPR))
927 DeadInstructions.insert(MRI->getVRegDef(GPR));
943 if (MRI->hasOneUse(GPR))
944 DeadInstructions.insert(MRI->getVRegDef(GPR));
|
| /src/external/gpl3/gdb/dist/sim/d10v/ |
| d10v-sim.h | 228 #define GPR(N) (State.regs[(N)] + 0)
432 if (PSW_MD && GPR (x) == (MOD_E & test_i)) \
435 SET_GPR (x, GPR (x) + (i)); \
|
| /src/external/gpl3/gdb/dist/sim/ppc/ |
| registers.h | 264 gpreg gpr[32]; member in struct:_registers
333 #define GPR(N) cpu_registers(processor)->gpr[N]
|
| /src/external/gpl3/gdb.old/dist/sim/cr16/ |
| cr16-sim.h | 195 #define GPR(N) (State.regs[(N)] + 0)
201 : GPR (N)
|
| /src/external/gpl3/gdb.old/dist/sim/d10v/ |
| d10v-sim.h | 228 #define GPR(N) (State.regs[(N)] + 0)
432 if (PSW_MD && GPR (x) == (MOD_E & test_i)) \
435 SET_GPR (x, GPR (x) + (i)); \
|
| /src/external/gpl3/gdb.old/dist/sim/ppc/ |
| registers.h | 264 gpreg gpr[32]; member in struct:_registers
333 #define GPR(N) cpu_registers(processor)->gpr[N]
|
| /src/external/gpl3/gdb/dist/sim/cr16/ |
| cr16-sim.h | 195 #define GPR(N) (State.regs[(N)] + 0)
201 : GPR (N)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 47 // | callee-saved gpr registers | <--.
95 // platforms, the frame-record is stored at the bottom of the (gpr) callee-saved
2180 // If pairing a GPR with LR, the pair can be described by the save_lrpair
2216 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type;
2226 case GPR:
2284 RPI.Type = RegPairInfo::GPR;
2301 case RegPairInfo::GPR:
2525 case RegPairInfo::GPR:
2631 case RegPairInfo::GPR:
2875 // Adding the size of additional 64bit GPR saves
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/mips/ |
| sim-main.h | 230 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
334 #define GPR (®ISTERS[0])
|
| /src/external/gpl3/gdb/dist/sim/mips/ |
| sim-main.h | 230 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
334 #define GPR (®ISTERS[0])
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 4425 // For register list parsing, we need to map from raw GPR register numbering
4429 // If this is a GPR, we need to do it manually, otherwise we can rely
4435 default: llvm_unreachable("Invalid GPR number!");
6952 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID);
6953 if (!GPR.contains(Op2.getReg()))
6964 unsigned PairedReg = GPR.getRegister(RtEncoding + 1);
7395 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
7454 // return 'true' if register list contains non-low GPR registers,
11687 return Error(L, ".save expects GPR registers");
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| nid.h | 889 #define GPR(x) ((x) << 16)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 2875 /// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
3543 // fpr index is 1 byte after gpr
3599 // increase overflow_area by 4/8 if gpr/fpr > 8
3742 // char gpr; /* index into the array of 8 GPRs
3744 // * gpr=0 corresponds to r3,
3745 // * gpr=1 to r4, etc.
4025 // SPE passes doubles in GPR pairs.
4228 static const MCPhysReg GPR[] = {
4237 const unsigned Num_GPR_Regs = array_lengthof(GPR);
4299 /* Compute GPR index associated with argument offset. *
[all...] |
