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      1 /*	$NetBSD: intel_guc_reg.h,v 1.2 2021/12/18 23:45:31 riastradh Exp $	*/
      2 
      3 /* SPDX-License-Identifier: MIT */
      4 /*
      5  * Copyright  2014-2019 Intel Corporation
      6  */
      7 
      8 #ifndef _INTEL_GUC_REG_H_
      9 #define _INTEL_GUC_REG_H_
     10 
     11 #include <linux/compiler.h>
     12 #include <linux/types.h>
     13 
     14 #include "i915_reg.h"
     15 
     16 /* Definitions of GuC H/W registers, bits, etc */
     17 
     18 #define GUC_STATUS			_MMIO(0xc000)
     19 #define   GS_RESET_SHIFT		0
     20 #define   GS_MIA_IN_RESET		  (0x01 << GS_RESET_SHIFT)
     21 #define   GS_BOOTROM_SHIFT		1
     22 #define   GS_BOOTROM_MASK		  (0x7F << GS_BOOTROM_SHIFT)
     23 #define   GS_BOOTROM_RSA_FAILED		  (0x50 << GS_BOOTROM_SHIFT)
     24 #define   GS_BOOTROM_JUMP_PASSED	  (0x76 << GS_BOOTROM_SHIFT)
     25 #define   GS_UKERNEL_SHIFT		8
     26 #define   GS_UKERNEL_MASK		  (0xFF << GS_UKERNEL_SHIFT)
     27 #define   GS_UKERNEL_LAPIC_DONE		  (0x30 << GS_UKERNEL_SHIFT)
     28 #define   GS_UKERNEL_DPC_ERROR		  (0x60 << GS_UKERNEL_SHIFT)
     29 #define   GS_UKERNEL_EXCEPTION		  (0x70 << GS_UKERNEL_SHIFT)
     30 #define   GS_UKERNEL_READY		  (0xF0 << GS_UKERNEL_SHIFT)
     31 #define   GS_MIA_SHIFT			16
     32 #define   GS_MIA_MASK			  (0x07 << GS_MIA_SHIFT)
     33 #define   GS_MIA_CORE_STATE		  (0x01 << GS_MIA_SHIFT)
     34 #define   GS_MIA_HALT_REQUESTED		  (0x02 << GS_MIA_SHIFT)
     35 #define   GS_MIA_ISR_ENTRY		  (0x04 << GS_MIA_SHIFT)
     36 #define   GS_AUTH_STATUS_SHIFT		30
     37 #define   GS_AUTH_STATUS_MASK		  (0x03 << GS_AUTH_STATUS_SHIFT)
     38 #define   GS_AUTH_STATUS_BAD		  (0x01 << GS_AUTH_STATUS_SHIFT)
     39 #define   GS_AUTH_STATUS_GOOD		  (0x02 << GS_AUTH_STATUS_SHIFT)
     40 
     41 #define SOFT_SCRATCH(n)			_MMIO(0xc180 + (n) * 4)
     42 #define SOFT_SCRATCH_COUNT		16
     43 
     44 #define GEN11_SOFT_SCRATCH(n)		_MMIO(0x190240 + (n) * 4)
     45 #define GEN11_SOFT_SCRATCH_COUNT	4
     46 
     47 #define UOS_RSA_SCRATCH(i)		_MMIO(0xc200 + (i) * 4)
     48 #define UOS_RSA_SCRATCH_COUNT		64
     49 
     50 #define DMA_ADDR_0_LOW			_MMIO(0xc300)
     51 #define DMA_ADDR_0_HIGH			_MMIO(0xc304)
     52 #define DMA_ADDR_1_LOW			_MMIO(0xc308)
     53 #define DMA_ADDR_1_HIGH			_MMIO(0xc30c)
     54 #define   DMA_ADDRESS_SPACE_WOPCM	  (7 << 16)
     55 #define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
     56 #define DMA_COPY_SIZE			_MMIO(0xc310)
     57 #define DMA_CTRL			_MMIO(0xc314)
     58 #define   HUC_UKERNEL			  (1<<9)
     59 #define   UOS_MOVE			  (1<<4)
     60 #define   START_DMA			  (1<<0)
     61 #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
     62 #define   GUC_WOPCM_OFFSET_VALID	  (1<<0)
     63 #define   HUC_LOADING_AGENT_VCR		  (0<<1)
     64 #define   HUC_LOADING_AGENT_GUC		  (1<<1)
     65 #define   GUC_WOPCM_OFFSET_SHIFT	14
     66 #define   GUC_WOPCM_OFFSET_MASK		  (0x3ffff << GUC_WOPCM_OFFSET_SHIFT)
     67 #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
     68 
     69 #define HUC_STATUS2             _MMIO(0xD3B0)
     70 #define   HUC_FW_VERIFIED       (1<<7)
     71 
     72 #define GEN11_HUC_KERNEL_LOAD_INFO	_MMIO(0xC1DC)
     73 #define   HUC_LOAD_SUCCESSFUL		  (1 << 0)
     74 
     75 #define GUC_WOPCM_SIZE			_MMIO(0xc050)
     76 #define   GUC_WOPCM_SIZE_LOCKED		  (1<<0)
     77 #define   GUC_WOPCM_SIZE_SHIFT		12
     78 #define   GUC_WOPCM_SIZE_MASK		  (0xfffff << GUC_WOPCM_SIZE_SHIFT)
     79 
     80 #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
     81 #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
     82 #define GEN9_GT_PM_CONFIG		_MMIO(0x13816c)
     83 #define   GT_DOORBELL_ENABLE		  (1<<0)
     84 
     85 #define GEN8_GTCR			_MMIO(0x4274)
     86 #define   GEN8_GTCR_INVALIDATE		  (1<<0)
     87 
     88 #define GEN12_GUC_TLB_INV_CR		_MMIO(0xcee8)
     89 #define   GEN12_GUC_TLB_INV_CR_INVALIDATE	(1 << 0)
     90 
     91 #define GUC_ARAT_C6DIS			_MMIO(0xA178)
     92 
     93 #define GUC_SHIM_CONTROL		_MMIO(0xc064)
     94 #define   GUC_DISABLE_SRAM_INIT_TO_ZEROES	(1<<0)
     95 #define   GUC_ENABLE_READ_CACHE_LOGIC		(1<<1)
     96 #define   GUC_ENABLE_MIA_CACHING		(1<<2)
     97 #define   GUC_GEN10_MSGCH_ENABLE		(1<<4)
     98 #define   GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA	(1<<9)
     99 #define   GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	(1<<10)
    100 #define   GUC_ENABLE_MIA_CLOCK_GATING		(1<<15)
    101 #define   GUC_GEN10_SHIM_WC_ENABLE		(1<<21)
    102 
    103 #define GUC_SEND_INTERRUPT		_MMIO(0xc4c8)
    104 #define   GUC_SEND_TRIGGER		  (1<<0)
    105 #define GEN11_GUC_HOST_INTERRUPT	_MMIO(0x1901f0)
    106 
    107 #define GUC_NUM_DOORBELLS		256
    108 
    109 /* format of the HW-monitored doorbell cacheline */
    110 struct guc_doorbell_info {
    111 	u32 db_status;
    112 #define GUC_DOORBELL_DISABLED		0
    113 #define GUC_DOORBELL_ENABLED		1
    114 
    115 	u32 cookie;
    116 	u32 reserved[14];
    117 } __packed;
    118 
    119 #define GEN8_DRBREGL(x)			_MMIO(0x1000 + (x) * 8)
    120 #define   GEN8_DRB_VALID		  (1<<0)
    121 #define GEN8_DRBREGU(x)			_MMIO(0x1000 + (x) * 8 + 4)
    122 
    123 #define DE_GUCRMR			_MMIO(0x44054)
    124 
    125 #define GUC_BCS_RCS_IER			_MMIO(0xC550)
    126 #define GUC_VCS2_VCS1_IER		_MMIO(0xC554)
    127 #define GUC_WD_VECS_IER			_MMIO(0xC558)
    128 #define GUC_PM_P24C_IER			_MMIO(0xC55C)
    129 
    130 /* GuC Interrupt Vector */
    131 #define GUC_INTR_GUC2HOST		BIT(15)
    132 #define GUC_INTR_EXEC_ERROR		BIT(14)
    133 #define GUC_INTR_DISPLAY_EVENT		BIT(13)
    134 #define GUC_INTR_SEM_SIG		BIT(12)
    135 #define GUC_INTR_IOMMU2GUC		BIT(11)
    136 #define GUC_INTR_DOORBELL_RANG		BIT(10)
    137 #define GUC_INTR_DMA_DONE		BIT(9)
    138 #define GUC_INTR_FATAL_ERROR		BIT(8)
    139 #define GUC_INTR_NOTIF_ERROR		BIT(7)
    140 #define GUC_INTR_SW_INT_6		BIT(6)
    141 #define GUC_INTR_SW_INT_5		BIT(5)
    142 #define GUC_INTR_SW_INT_4		BIT(4)
    143 #define GUC_INTR_SW_INT_3		BIT(3)
    144 #define GUC_INTR_SW_INT_2		BIT(2)
    145 #define GUC_INTR_SW_INT_1		BIT(1)
    146 #define GUC_INTR_SW_INT_0		BIT(0)
    147 
    148 #endif
    149