1 /* $NetBSD: gtmpscreg.h,v 1.5 2016/01/15 12:09:15 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * gtmpscreg.h - register defines for GT-64260 MPSC 42 * 43 * creation Sun Apr 8 11:49:57 PDT 2001 cliff 44 */ 45 46 #ifndef _GTMPSCREG_H 47 #define _GTMPSCREG_H 48 49 #define GTMPSC_BASE(u) (MPSC0_BASE + ((u) << 12)) 50 #define GTMPSC_SIZE 0x1000 51 52 #define GTMPSC_NCHAN 2 /* Number of MPSC channels */ 53 54 /******************************************************************************* 55 * 56 * MPSC register address offsets relative to the base mapping 57 */ 58 #define GTMPSC_MMCR_LO 0x000 /* MPSC Main Config Register Low */ 59 #define GTMPSC_MMCR_HI 0x004 /* MPSC Main Config Register High */ 60 #define GTMPSC_MPCR 0x008 /* MPSC Protocol Config Register */ 61 #define GTMPSC_CHR_BASE 0x008 /* MPSC Channel Register Base */ 62 #define GTMPSC_CHRN(n) (GTMPSC_CHR_BASE + ((n) << 2)) 63 #define GTMPSC_NCHR 11 /* CHR 1-11? */ 64 65 #define GTMPSC_MRR 0xb400 /* MPSC Routing Register */ 66 #define GTMPSC_RCRR 0xb404 /* MPSC RX Clock Routing Register */ 67 #define GTMPSC_TCRR 0xb408 /* MPSC TX Clock Routing Register */ 68 69 70 /******************************************************************************* 71 * 72 * MPSC register values & bit defines 73 * 74 * values are provided for UART mode only 75 */ 76 /* 77 * MPSC Routing Register bits 78 */ 79 #define GTMPSC_MRR_PORT0 0 /* serial port #0 */ 80 #define GTMPSC_MRR_NONE 7 /* unconnected */ 81 /* all other "routes" resvd. */ 82 #define GTMPSC_MRR_MR0_MASK __BITS(2,0) /* routing mask for MPSC0 */ 83 #define GTMPSC_MRR_RESa __BITS(5,3) 84 #define GTMPSC_MRR_MR1_MASK __BITS(8,6) /* routing mask for MPSC1 */ 85 #define GTMPSC_MRR_RESb __BITS(30,9) 86 #define GTMPSC_MRRE_DSC __BIT(31) /* "Don't Stop Clock" */ 87 #define GTMPSC_MRR_RES (GTMPSC_MRR_RESa|GTMPSC_MRR_RESb) 88 /* 89 * MPSC Clock Routing Register bits 90 * the bitfields and route definitions are common for RCRR and TCRR 91 * except for MPSC_TCRR_TSCLK0 92 */ 93 #define GTMPSC_CRR_BRG0 0x0 /* Baud Rate Generator #0 */ 94 #define GTMPSC_CRR_BRG1 0x1 /* Baud Rate Generator #1 */ 95 #define GTMPSC_CRR_BRG2 0x2 /* Baud Rate Generator #2 */ 96 #define GTMPSC_CRR_SCLK0 0x8 /* SCLK0 */ 97 #define GTMPSC_TCRR_TSCLK0 0x9 /* TSCLK0 (for TCRR only) */ 98 /* all other values resvd. */ 99 #define GTMPSC_CRR(u, v) ((v) << GTMPSC_CRR_SHIFT(u)) 100 #define GTMPSC_CRR_SHIFT(u) ((u) * 8) 101 #define GTMPSC_CRR_MASK 0xf 102 #define GTMPSC_CRR_RESa __BITS(7,4) 103 #define GTMPSC_CRR_RESb __BITS(31,12) 104 #define GTMPSC_CRR_RES (GTMPSC_CRR_RESa|GTMPSC_CRR_RESb) 105 /* 106 * MPSC Main Configuration Register LO bits 107 */ 108 #define GTMPSC_MMCR_LO_MODE_MASK __BITS(2,0) 109 #define GTMPSC_MMCR_LO_MODE_UART (0x4 << 0) /* UART mode */ 110 #define GTMPSC_MMCR_LO_TTX __BIT(3) /* Transparent TX */ 111 #define GTMPSC_MMCR_LO_TRX __BIT(4) /* Transparent RX */ 112 #define GTMPSC_MMCR_LO_RESa __BIT(5) 113 #define GTMPSC_MMCR_LO_ET __BIT(6) /* Enable TX */ 114 #define GTMPSC_MMCR_LO_ER __BIT(7) /* Enable RX */ 115 #define GTMPSC_MMCR_LO_LPBK_MASK __BITS(9,8) /* Loop Back */ 116 #define GTMPSC_MMCR_LO_LPBK_NONE (0 << 8) /* Normal (non-loop) */ 117 #define GTMPSC_MMCR_LO_LPBK_LOOP (1 << 8) /* Loop Back */ 118 #define GTMPSC_MMCR_LO_LPBK_ECHO (2 << 8) /* Echo */ 119 #define GTMPSC_MMCR_LO_LPBK_LBE (3 << 8) /* Loop Back and Echo */ 120 #define GTMPSC_MMCR_LO_NLM __BIT(10) /* Null Modem */ 121 #define GTMPSC_MMCR_LO_RESb __BIT(11) 122 #define GTMPSC_MMCR_LO_TSYN __BIT(12) /* Transmitter sync to Rcvr. */ 123 #define GTMPSC_MMCR_LO_RESc __BIT(13) 124 #define GTMPSC_MMCR_LO_TSNS_MASK __BITS(15,14) /* Transmit Sense */ 125 #define GTMPSC_MMCR_LO_TSNS_INF (0 << 14) /* Infinite */ 126 #define GTMPSC_MMCR_LO_TIDL __BIT(16) /* TX Idles */ 127 #define GTMPSC_MMCR_LO_RTSM __BIT(17) /* RTS Mode */ 128 #define GTMPSC_MMCR_LO_RESd __BIT(18) 129 #define GTMPSC_MMCR_LO_CTSS __BIT(19) /* CTS Sampling mode */ 130 #define GTMPSC_MMCR_LO_CDS __BIT(20) /* CD Sampling mode */ 131 #define GTMPSC_MMCR_LO_CTSM __BIT(21) /* CTS operating Mode */ 132 #define GTMPSC_MMCR_LO_CDM __BIT(22) /* CD operating Mode */ 133 #define GTMPSC_MMCR_LO_CRCM_MASK __BITS(25,23) /* CRC Mode */ 134 #define GTMPSC_MMCR_LO_CRCM_NONE (0 << 23) /* CRC Mode */ 135 #define GTMPSC_MMCR_LO_RESe __BITS(27,26) 136 #define GTMPSC_MMCR_LO_TRVD __BIT(28) /* Transmit Reverse Data */ 137 #define GTMPSC_MMCR_LO_RRVD __BIT(29) /* Receive Reverse Data */ 138 #define GTMPSC_MMCR_LO_RESf __BIT(30) 139 #define GTMPSC_MMCR_LO_GDE __BIT(31) /* Glitch Detect Enable */ 140 #define GTMPSC_MMCR_LO_RES \ 141 (GTMPSC_MMCR_LO_RESa|GTMPSC_MMCR_LO_RESb|GTMPSC_MMCR_LO_RESc \ 142 |GTMPSC_MMCR_LO_RESd|GTMPSC_MMCR_LO_RESe|GTMPSC_MMCR_LO_RESf) 143 /* 144 * MPSC Main Configuration Register HI bits 145 */ 146 #define GTMPSC_MMCR_HI_TCI __BIT(0) /* TX Clock Invert */ 147 #define GTMPSC_MMCR_HI_TINV __BIT(1) /* TX Bitstream Inversion */ 148 #define GTMPSC_MMCR_HI_TPL __BITS(4,2) /* TX Preable Length */ 149 #define GTMPSC_MMCR_HI_TPL_NONE 0 /* no TX Preable (default) */ 150 #define GTMPSC_MMCR_HI_TPL_16 (6 << 2) /* 16 byte preamble */ 151 #define GTMPSC_MMCR_HI_TPPT_MASK __BITS(8,5) /* TX Preable Pattern */ 152 #define GTMPSC_MMCR_HI_TPPT_NONE (0 << 5) /* TX Preable Pattern */ 153 #define GTMPSC_MMCR_HI_TCDV_MASK __BITS(10,9) /* TX Clock Divide */ 154 #define GTMPSC_MMCR_HI_TCDV_1X (0 << 9) /* 1x clock mode */ 155 #define GTMPSC_MMCR_HI_TCDV_8X (1 << 9) /* 8x clock mode */ 156 #define GTMPSC_MMCR_HI_TCDV_16X (2 << 9) /* 16x clock mode */ 157 #define GTMPSC_MMCR_HI_TCDV_32X (3 << 9) /* 32x clock mode */ 158 #define GTMPSC_MMCR_HI_TDEC_MASK __BITS(13,11) /* TX Encoder */ 159 #define GTMPSC_MMCR_HI_TDEC_NRZ (0 << 9) /* NRZ (default) */ 160 #define GTMPSC_MMCR_HI_TDEC_NRZI (1 << 9) /* NRZI (mark) */ 161 #define GTMPSC_MMCR_HI_TDEC_FM0 (2 << 9) /* FM0 */ 162 #define GTMPSC_MMCR_HI_TDEC_MAN (4 << 9) /* Manchester */ 163 #define GTMPSC_MMCR_HI_TDEC_DMAN (6 << 9) /* Differential Manchester */ 164 /* all other values rsvd. */ 165 #define GTMPSC_MMCR_HI_RESa __BITS(15,14) 166 #define GTMPSC_MMCR_HI_RINV __BIT(16) /* RX Bitstream Inversion */ 167 #define GTMPSC_MMCR_HI_GDW __BITS(20,17) /* Clock Glitch Width */ 168 #define GTMPSC_MMCR_HI_RESb __BIT(21) 169 #define GTMPSC_MMCR_HI_RDW __BIT(22) /* Reveive Data Width */ 170 #define GTMPSC_MMCR_HI_RSYL_MASK __BITS(24,23) /* Reveive Sync Width */ 171 #define GTMPSC_MMCR_HI_RSYL_EXT (0 << 23) /* External sync */ 172 #define GTMPSC_MMCR_HI_RSYL_4BIT (1 << 23) /* 4-bit sync */ 173 #define GTMPSC_MMCR_HI_RSYL_8BIT (2 << 23) /* 8-bit sync */ 174 #define GTMPSC_MMCR_HI_RSYL_16BIT (3 << 23) /* 16-bit sync */ 175 #define GTMPSC_MMCR_HI_RCDV_MASK __BITS(26,25) /* Receive Clock Divider */ 176 #define GTMPSC_MMCR_HI_RCDV_1X (0 << 25) /* 1x clock mode (default) */ 177 #define GTMPSC_MMCR_HI_RCDV_8X (1 << 25) /* 8x clock mode (default) */ 178 #define GTMPSC_MMCR_HI_RCDV_16X (2 << 25) /* 16x clock mode (default) */ 179 #define GTMPSC_MMCR_HI_RCDV_32X (3 << 25) /* 16x clock mode (default) */ 180 #define GTMPSC_MMCR_HI_RENC_MASK __BITS(29,27) /* Receive Encoder */ 181 #define GTMPSC_MMCR_HI_RENC_NRZ (0 << 27) /* NRZ (default) */ 182 #define GTMPSC_MMCR_HI_RENC_NRZI (1 << 27) /* NRZI */ 183 #define GTMPSC_MMCR_HI_RENC_FM0 (2 << 27) /* FM0 */ 184 #define GTMPSC_MMCR_HI_RENC_MAN (4 << 27) /* Manchester */ 185 #define GTMPSC_MMCR_HI_RENC_DMAN (6 << 27) /* Differential Manchester */ 186 /* all other values rsvd. */ 187 #define GTMPSC_MMCR_HI_SEDG_MASK __BITS(31,30) /* Sync Clock Edge */ 188 #define GTMPSC_MMCR_HI_SEDG_BOTH (0 << 30) /* rising and falling (dflt) */ 189 #define GTMPSC_MMCR_HI_SEDG_RISE (1 << 30) /* rising edge */ 190 #define GTMPSC_MMCR_HI_SEDG_FALL (2 << 30) /* falling edge */ 191 #define GTMPSC_MMCR_HI_SEDG_NONE (3 << 30) /* no adjustment */ 192 /* 193 * SDMAx Command/Status Register bits for UART Mode, RX 194 * 195 * XXX these belong in sdmareg.h ? 196 */ 197 #define SDMA_CSR_RX_PE __BIT(0) /* Parity Error */ 198 #define SDMA_CSR_RX_CDL __BIT(1) /* Carrier Detect Loss */ 199 #define SDMA_CSR_RX_RESa __BIT(2) 200 #define SDMA_CSR_RX_FR __BIT(3) /* Framing Error */ 201 #define SDMA_CSR_RX_RESb __BITS(5,4) 202 #define SDMA_CSR_RX_OR __BIT(6) /* Data Overrun */ 203 #define SDMA_CSR_RX_RESc __BITS(8,7) 204 #define SDMA_CSR_RX_BR __BIT(9) /* Break Received */ 205 #define SDMA_CSR_RX_MI __BIT(10) /* Max Idle */ 206 #define SDMA_CSR_RX_ADDR __BIT(11) /* Address */ 207 #define SDMA_CSR_RX_AMATCH __BIT(12) /* Address match */ 208 #define SDMA_CSR_RX_CT __BIT(13) /* Transparency Control char */ 209 #define SDMA_CSR_RX_C __BIT(14) /* Control char */ 210 #define SDMA_CSR_RX_ES __BIT(15) /* Error Summary */ 211 #define SDMA_CSR_RX_L __BIT(16) /* Last */ 212 #define SDMA_CSR_RX_F __BIT(17) /* First */ 213 #define SDMA_CSR_RX_RESd __BITS(22,18) 214 #define SDMA_CSR_RX_EI __BIT(23) /* Enable Interrupt */ 215 #define SDMA_CSR_RX_RESe __BITS(29,24) 216 #define SDMA_CSR_RX_AUTO __BIT(30) /* Auto Mode */ 217 #define SDMA_CSR_RX_OWN __BIT(31) /* Owner */ 218 #define SDMA_CSR_RX_RES (SDMA_CSR_RX_RESa|SDMA_CSR_RX_RESb|SDMA_CSR_RX_RESc \ 219 |SDMA_CSR_RX_RESd|SDMA_CSR_RX_RESe) 220 /* 221 * SDMAx Command/Status Register bits for UART Mode, TX 222 */ 223 #define SDMA_CSR_TX_RESa __BIT(0) 224 #define SDMA_CSR_TX_CTSL __BIT(1) /* CTS Loss */ 225 #define SDMA_CSR_TX_RESb __BITS(14,2) 226 #define SDMA_CSR_TX_ES __BIT(15) /* Error Summary */ 227 #define SDMA_CSR_TX_L __BIT(16) /* Last */ 228 #define SDMA_CSR_TX_F __BIT(17) /* First */ 229 #define SDMA_CSR_TX_P __BIT(18) /* Preamble */ 230 #define SDMA_CSR_TX_ADDR __BIT(19) /* Address */ 231 #define SDMA_CSR_TX_NS __BIT(20) /* No Stop Bit */ 232 #define SDMA_CSR_TX_RESc __BITS(22,21) 233 #define SDMA_CSR_TX_EI __BIT(23) /* Enable Interrupt */ 234 #define SDMA_CSR_TX_RESd __BITS(29,24) 235 #define SDMA_CSR_TX_AUTO __BIT(30) /* Auto Mode */ 236 #define SDMA_CSR_TX_OWN __BIT(31) /* Owner */ 237 #define SDMA_CSR_TX_RES \ 238 (SDMA_CSR_TX_RESa|SDMA_CSR_TX_RESb|SDMA_CSR_TX_RESc|SDMA_CSR_TX_RESd) 239 /* 240 * MPSCx Protocol Configuration Register for UART Mode 241 */ 242 #define GTMPSC_MPCR_RESa __BITS(5,0) 243 #define GTMPSC_MPCR_DRT __BIT(6) /* Disable Rx on Tx */ 244 #define GTMPSC_MPCR_ISO __BIT(7) /* Isochronous Mode */ 245 #define GTMPSC_MPCR_RZS __BIT(8) /* Rx Zero Stop Bit(s) */ 246 #define GTMPSC_MPCR_FRZ __BIT(9) /* Freeze Tx */ 247 #define GTMPSC_MPCR_UM_MASK __BITS(11,10) /* UART Mode mask */ 248 #define GTMPSC_MPCR_UM_NORM (0 << 10) /* Normal UART Mode */ 249 #define GTMPSC_MPCR_UM_MDROP (1 << 10) /* Multi-Drop UART Mode */ 250 /* other values are resvd. */ 251 #define GTMPSC_MPCR_CLMASK __BITS(13,12) /* Character Length mask */ 252 #define GTMPSC_MPCR_CL_5 (0 << 12) /* 5 data bits */ 253 #define GTMPSC_MPCR_CL_6 (1 << 12) /* 6 data bits */ 254 #define GTMPSC_MPCR_CL_7 (2 << 12) /* 7 data bits */ 255 #define GTMPSC_MPCR_CL_8 (3 << 12) /* 8 data bits */ 256 #define GTMPSC_MPCR_SBL_1 (0 << 14) /* 1 stop bit */ 257 #define GTMPSC_MPCR_SBL_2 (1 << 14) /* 2 stop bits */ 258 #define GTMPSC_MPCR_FLC_NORM 0x0 /* Normal Flow Ctl mode */ 259 #define GTMPSC_MPCR_FLC_ASYNC __BIT(15) /* Asynchronous Flow Ctl mode */ 260 #define GTMPSC_MPCR_RESb __BITS(31,16) 261 #define GTMPSC_MPCR_RES (GTMPSC_MPCR_RESa|GTMPSC_MPCR_RESb) 262 /* 263 * MPSC Channel Register 1 for UART Mode "Break/Stuff" 264 */ 265 #define GTMPSC_CHR1_TCS __BITS(7,0) /* Constrol Stuff Character */ 266 #define GTMPSC_CHR1_BRK __BITS(23,16) /* Break Count */ 267 #define GTMPSC_CHR1_RES __BITS(15,8)|__BITS(31,24) 268 /* 269 * MPSC Channel Register 2 for UART Mode "Command" 270 */ 271 #define GTMPSC_CHR2_RESa __BIT(0) 272 #define GTMPSC_CHR2_TEV __BIT(1) /* Tx Enb. Vert. Redundancy */ 273 #define GTMPSC_CHR2_TPM_MASK __BITS(3,2) /* Tx Parity Mode mask */ 274 #define GTMPSC_CHR2_TPM_ODD (0 << 2) /* Odd Tx Parity */ 275 #define GTMPSC_CHR2_TPM_LOW (1 << 2) /* Low (always 0) Tx Parity */ 276 #define GTMPSC_CHR2_TPM_EVEN (2 << 2) /* Even Tx Parity */ 277 #define GTMPSC_CHR2_TPM_HIGH (3 << 2) /* High (always 1) Tx Parity */ 278 #define GTMPSC_CHR2_RESb __BITS(6,4) 279 #define GTMPSC_CHR2_TXABORT __BIT(7) /* Tx Abort */ 280 #define GTMPSC_CHR2_RESc __BIT(8) 281 #define GTMPSC_CHR2_TCS __BIT(9) /* Tx TCS Char */ 282 #define GTMPSC_CHR2_RESd __BITS(16,10) 283 #define GTMPSC_CHR2_REC __BIT(17) /* Rx Enb. Vert. Redundancy */ 284 #define GTMPSC_CHR2_RPM_MASK __BITS(19,18) /* Rx Parity Mode mask */ 285 #define GTMPSC_CHR2_RPM_ODD (0 << 18) /* Odd Rx Parity */ 286 #define GTMPSC_CHR2_RPM_LOW (1 << 18) /* Low (always 0) Rx Parity */ 287 #define GTMPSC_CHR2_RPM_EVEN (2 << 18) /* Even Rx Parity */ 288 #define GTMPSC_CHR2_RPM_HIGH (3 << 18) /* High (always 1) Rx Parity */ 289 #define GTMPSC_CHR2_RESe __BITS(22,20) 290 #define GTMPSC_CHR2_RXABORT __BIT(23) /* Rx Abort */ 291 #define GTMPSC_CHR2_RESf __BIT(24) 292 #define GTMPSC_CHR2_CRD __BIT(25) /* Close RX Descriptor */ 293 #define GTMPSC_CHR2_RESg __BITS(30,26) 294 #define GTMPSC_CHR2_EH __BIT(31) /* Enter Hunt */ 295 #define GTMPSC_CHR2_RES \ 296 (GTMPSC_CHR2_RESa|GTMPSC_CHR2_RESb|GTMPSC_CHR2_RESc| \ 297 GTMPSC_CHR2_RESd|GTMPSC_CHR2_RESe|GTMPSC_CHR2_RESf| \ 298 GTMPSC_CHR2_RESg) 299 /* 300 * MPSC Channel Register 3 for UART Mode "Max Idle" 301 */ 302 #define GTMPSC_CHR3_MIR __BITS(15,0) /* Max Idle Char count */ 303 #define GTMPSC_CHR3_RES __BITS(31,16) 304 /* 305 * MPSC Channel Register 4 for UART Mode "Control Filtering" 306 */ 307 #define GTMPSC_CHR4_CFR __BITS(7,0) /* Control bit compare enable */ 308 #define GTMPSC_CHR4_RES __BITS(31,8) 309 /* 310 * MPSC Channel Registers 5..8 for UART Mode "UART Control Character" 311 * 312 * NOTE: two 16 bit CHRCC fields exist in each of Channel Registers 5..8 313 */ 314 #define GTMPSC_CHRCC_SHIFT 16 315 #define GTMPSC_CHRCC_CHAR __BITS(7,0) /* the control character */ 316 #define GTMPSC_CHRCC_RES __BITS(11,8) 317 #define GTMPSC_CHRCC_INT __BIT(12) /* Interrupt */ 318 #define GTMPSC_CHRCC_CO __BIT(13) /* ISO 3309 Control Octet */ 319 #define GTMPSC_CHRCC_R __BIT(14) /* Reject */ 320 #define GTMPSC_CHRCC_V __BIT(15) /* Valid */ 321 /* 322 * MPSC Channel Register 9 for UART Mode "Address" (for multidrop operation) 323 */ 324 #define GTMPSC_CHR9_AD1 __BITS(7,0) /* address #1 */ 325 #define GTMPSC_CHR9_RESa __BITS(14,8) 326 #define GTMPSC_CHR9_MODE1 __BIT(15) /* mode #1 */ 327 #define GTMPSC_CHR9_AD2 __BITS(23,16) /* address #2 */ 328 #define GTMPSC_CHR9_RESb __BITS(30,24) 329 #define GTMPSC_CHR9_MODE2 __BIT(31) /* mode #2 */ 330 #define GTMPSC_CHR9_RES (GTMPSC_CHR9_RESa|GTMPSC_CHR9_RESb) 331 /* 332 * MPSC Channel Register 10 for UART Mode "Event Status" 333 */ 334 #define GTMPSC_CHR10_CTS __BIT(0) /* Clear To Send */ 335 #define GTMPSC_CHR10_CD __BIT(1) /* Carrier Detect */ 336 #define GTMPSC_CHR10_RESa __BIT(2) 337 #define GTMPSC_CHR10_TIDLE __BIT(3) /* Tx in Idle State */ 338 #define GTMPSC_CHR10_RESb __BIT(4) 339 #define GTMPSC_CHR10_RHS __BIT(5) /* Rx in HUNT State */ 340 #define GTMPSC_CHR10_RESc __BIT(6) 341 #define GTMPSC_CHR10_RLS __BIT(7) /* Rx Line STatus */ 342 #define GTMPSC_CHR10_RESd __BITS(10,8) 343 #define GTMPSC_CHR10_RLIDL __BIT(11) /* Rx IDLE Line */ 344 #define GTMPSC_CHR10_RESe __BITS(15,12) 345 #define GTMPSC_CHR10_RCRn __BITS(23,16) /* Received Control Char # */ 346 #define GTMPSC_CHR10_RESf __BITS(31,24) 347 #define GTMPSC_CHR10_RES \ 348 (GTMPSC_CHR10_RESa|GTMPSC_CHR10_RESb|GTMPSC_CHR10_RESc \ 349 |GTMPSC_CHR10_RESd|GTMPSC_CHR10_RESe|GTMPSC_CHR10_RESf) 350 351 352 #endif /* _GTMPSCREG_H */ 353
Indexes created Sun Sep 21 18:09:52 GMT 2025