1 /* $NetBSD: smu9_driver_if.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef SMU9_DRIVER_IF_H 27 #define SMU9_DRIVER_IF_H 28 29 #include "smu9.h" 30 31 /**** IMPORTANT *** 32 * SMU TEAM: Always increment the interface version if 33 * any structure is changed in this file 34 */ 35 #define SMU9_DRIVER_IF_VERSION 0xE 36 37 #define PPTABLE_V10_SMU_VERSION 1 38 39 #define NUM_GFXCLK_DPM_LEVELS 8 40 #define NUM_UVD_DPM_LEVELS 8 41 #define NUM_VCE_DPM_LEVELS 8 42 #define NUM_MP0CLK_DPM_LEVELS 8 43 #define NUM_UCLK_DPM_LEVELS 4 44 #define NUM_SOCCLK_DPM_LEVELS 8 45 #define NUM_DCEFCLK_DPM_LEVELS 8 46 #define NUM_LINK_LEVELS 2 47 48 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 49 #define MAX_UVD_DPM_LEVEL (NUM_UVD_DPM_LEVELS - 1) 50 #define MAX_VCE_DPM_LEVEL (NUM_VCE_DPM_LEVELS - 1) 51 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 52 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 53 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 54 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1) 55 #define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1) 56 57 #define MIN_GFXCLK_DPM_LEVEL 0 58 #define MIN_UVD_DPM_LEVEL 0 59 #define MIN_VCE_DPM_LEVEL 0 60 #define MIN_MP0CLK_DPM_LEVEL 0 61 #define MIN_UCLK_DPM_LEVEL 0 62 #define MIN_SOCCLK_DPM_LEVEL 0 63 #define MIN_DCEFCLK_DPM_LEVEL 0 64 #define MIN_LINK_DPM_LEVEL 0 65 66 #define NUM_EVV_VOLTAGE_LEVELS 8 67 #define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1) 68 #define MIN_EVV_VOLTAGE_LEVEL 0 69 70 #define NUM_PSP_LEVEL_MAP 4 71 72 /* Gemini Modes */ 73 #define PPSMC_GeminiModeNone 0 /* Single GPU board */ 74 #define PPSMC_GeminiModeMaster 1 /* Master GPU on a Gemini board */ 75 #define PPSMC_GeminiModeSlave 2 /* Slave GPU on a Gemini board */ 76 77 /* Voltage Modes for DPMs */ 78 #define VOLTAGE_MODE_AVFS_INTERPOLATE 0 79 #define VOLTAGE_MODE_AVFS_WORST_CASE 1 80 #define VOLTAGE_MODE_STATIC 2 81 82 typedef struct { 83 uint32_t FbMult; /* Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */ 84 uint32_t SsFbMult; /* Spread FB Mult: bit 8:0 int, bit 31:16 frac */ 85 uint16_t SsSlewFrac; 86 uint8_t SsOn; 87 uint8_t Did; /* DID */ 88 } PllSetting_t; 89 90 typedef struct { 91 int32_t a0; 92 int32_t a1; 93 int32_t a2; 94 95 uint8_t a0_shift; 96 uint8_t a1_shift; 97 uint8_t a2_shift; 98 uint8_t padding; 99 } GbVdroopTable_t; 100 101 typedef struct { 102 int32_t m1; 103 int32_t m2; 104 int32_t b; 105 106 uint8_t m1_shift; 107 uint8_t m2_shift; 108 uint8_t b_shift; 109 uint8_t padding; 110 } QuadraticInt_t; 111 112 #define NUM_DSPCLK_LEVELS 8 113 114 typedef enum { 115 DSPCLK_DCEFCLK = 0, 116 DSPCLK_DISPCLK, 117 DSPCLK_PIXCLK, 118 DSPCLK_PHYCLK, 119 DSPCLK_COUNT, 120 } DSPCLK_e; 121 122 typedef struct { 123 uint16_t Freq; /* in MHz */ 124 uint16_t Vid; /* min voltage in SVI2 VID */ 125 } DisplayClockTable_t; 126 127 typedef struct { 128 /* PowerTune */ 129 uint16_t SocketPowerLimit; /* Watts */ 130 uint16_t TdcLimit; /* Amps */ 131 uint16_t EdcLimit; /* Amps */ 132 uint16_t TedgeLimit; /* Celcius */ 133 uint16_t ThotspotLimit; /* Celcius */ 134 uint16_t ThbmLimit; /* Celcius */ 135 uint16_t Tvr_socLimit; /* Celcius */ 136 uint16_t Tvr_memLimit; /* Celcius */ 137 uint16_t Tliquid1Limit; /* Celcius */ 138 uint16_t Tliquid2Limit; /* Celcius */ 139 uint16_t TplxLimit; /* Celcius */ 140 uint16_t LoadLineResistance; /* in mOhms */ 141 uint32_t FitLimit; /* Failures in time (failures per million parts over the defined lifetime) */ 142 143 /* External Component Communication Settings */ 144 uint8_t Liquid1_I2C_address; 145 uint8_t Liquid2_I2C_address; 146 uint8_t Vr_I2C_address; 147 uint8_t Plx_I2C_address; 148 149 uint8_t GeminiMode; 150 uint8_t spare17[3]; 151 uint32_t GeminiApertureHigh; 152 uint32_t GeminiApertureLow; 153 154 uint8_t Liquid_I2C_LineSCL; 155 uint8_t Liquid_I2C_LineSDA; 156 uint8_t Vr_I2C_LineSCL; 157 uint8_t Vr_I2C_LineSDA; 158 uint8_t Plx_I2C_LineSCL; 159 uint8_t Plx_I2C_LineSDA; 160 uint8_t paddingx[2]; 161 162 /* ULV Settings */ 163 uint8_t UlvOffsetVid; /* SVI2 VID */ 164 uint8_t UlvSmnclkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */ 165 uint8_t UlvMp1clkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */ 166 uint8_t UlvGfxclkBypass; /* 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV */ 167 168 /* VDDCR_SOC Voltages */ 169 uint8_t SocVid[NUM_EVV_VOLTAGE_LEVELS]; 170 171 /* This is the minimum voltage needed to run the SOC. */ 172 uint8_t MinVoltageVid; /* Minimum Voltage ("Vmin") of ASIC */ 173 uint8_t MaxVoltageVid; /* Maximum Voltage allowable */ 174 uint8_t MaxVidStep; /* Max VID step that SMU will request. Multiple steps are taken if voltage change exceeds this value. */ 175 uint8_t padding8; 176 177 uint8_t UlvPhaseSheddingPsi0; /* set this to 1 to set PSI0/1 to 1 in ULV mode */ 178 uint8_t UlvPhaseSheddingPsi1; /* set this to 1 to set PSI0/1 to 1 in ULV mode */ 179 uint8_t padding8_2[2]; 180 181 /* SOC Frequencies */ 182 PllSetting_t GfxclkLevel [NUM_GFXCLK_DPM_LEVELS]; 183 184 uint8_t SocclkDid [NUM_SOCCLK_DPM_LEVELS]; /* DID */ 185 uint8_t SocDpmVoltageIndex [NUM_SOCCLK_DPM_LEVELS]; 186 187 uint8_t VclkDid [NUM_UVD_DPM_LEVELS]; /* DID */ 188 uint8_t DclkDid [NUM_UVD_DPM_LEVELS]; /* DID */ 189 uint8_t UvdDpmVoltageIndex [NUM_UVD_DPM_LEVELS]; 190 191 uint8_t EclkDid [NUM_VCE_DPM_LEVELS]; /* DID */ 192 uint8_t VceDpmVoltageIndex [NUM_VCE_DPM_LEVELS]; 193 194 uint8_t Mp0clkDid [NUM_MP0CLK_DPM_LEVELS]; /* DID */ 195 uint8_t Mp0DpmVoltageIndex [NUM_MP0CLK_DPM_LEVELS]; 196 197 DisplayClockTable_t DisplayClockTable[DSPCLK_COUNT][NUM_DSPCLK_LEVELS]; 198 QuadraticInt_t DisplayClock2Gfxclk[DSPCLK_COUNT]; 199 200 uint8_t GfxDpmVoltageMode; 201 uint8_t SocDpmVoltageMode; 202 uint8_t UclkDpmVoltageMode; 203 uint8_t UvdDpmVoltageMode; 204 205 uint8_t VceDpmVoltageMode; 206 uint8_t Mp0DpmVoltageMode; 207 uint8_t DisplayDpmVoltageMode; 208 uint8_t padding8_3; 209 210 uint16_t GfxclkSlewRate; 211 uint16_t padding; 212 213 uint32_t LowGfxclkInterruptThreshold; /* in units of 10KHz */ 214 215 /* Alpha parameters for clock averages. ("255"=1) */ 216 uint8_t GfxclkAverageAlpha; 217 uint8_t SocclkAverageAlpha; 218 uint8_t UclkAverageAlpha; 219 uint8_t GfxActivityAverageAlpha; 220 221 /* UCLK States */ 222 uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */ 223 PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */ 224 uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS]; 225 uint8_t LowestUclkReservedForUlv; /* Set this to 1 if UCLK DPM0 is reserved for ULV-mode only */ 226 uint8_t paddingUclk[3]; 227 uint16_t NumMemoryChannels; /* Used for memory bandwidth calculations */ 228 uint16_t MemoryChannelWidth; /* Used for memory bandwidth calculations */ 229 230 /* CKS Settings */ 231 uint8_t CksEnable[NUM_GFXCLK_DPM_LEVELS]; 232 uint8_t CksVidOffset[NUM_GFXCLK_DPM_LEVELS]; 233 234 /* MP0 Mapping Table */ 235 uint8_t PspLevelMap[NUM_PSP_LEVEL_MAP]; 236 237 /* Link DPM Settings */ 238 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */ 239 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ 240 uint8_t LclkDid[NUM_LINK_LEVELS]; /* Leave at 0 to use hardcoded values in FW */ 241 uint8_t paddingLinkDpm[2]; 242 243 /* Fan Control */ 244 uint16_t FanStopTemp; /* Celcius */ 245 uint16_t FanStartTemp; /* Celcius */ 246 247 uint16_t FanGainEdge; 248 uint16_t FanGainHotspot; 249 uint16_t FanGainLiquid; 250 uint16_t FanGainVrVddc; 251 uint16_t FanGainVrMvdd; 252 uint16_t FanGainPlx; 253 uint16_t FanGainHbm; 254 uint16_t FanPwmMin; 255 uint16_t FanAcousticLimitRpm; 256 uint16_t FanThrottlingRpm; 257 uint16_t FanMaximumRpm; 258 uint16_t FanTargetTemperature; 259 uint16_t FanTargetGfxclk; 260 uint8_t FanZeroRpmEnable; 261 uint8_t FanSpare; 262 263 /* The following are AFC override parameters. Leave at 0 to use FW defaults. */ 264 int16_t FuzzyFan_ErrorSetDelta; 265 int16_t FuzzyFan_ErrorRateSetDelta; 266 int16_t FuzzyFan_PwmSetDelta; 267 uint16_t FuzzyFan_Reserved; 268 269 /* GPIO Settings */ 270 uint8_t AcDcGpio; /* GPIO pin configured for AC/DC switching */ 271 uint8_t AcDcPolarity; /* GPIO polarity for AC/DC switching */ 272 uint8_t VR0HotGpio; /* GPIO pin configured for VR0 HOT event */ 273 uint8_t VR0HotPolarity; /* GPIO polarity for VR0 HOT event */ 274 uint8_t VR1HotGpio; /* GPIO pin configured for VR1 HOT event */ 275 uint8_t VR1HotPolarity; /* GPIO polarity for VR1 HOT event */ 276 uint8_t Padding1; /* replace GPIO pin configured for CTF */ 277 uint8_t Padding2; /* replace GPIO polarity for CTF */ 278 279 /* LED Display Settings */ 280 uint8_t LedPin0; /* GPIO number for LedPin[0] */ 281 uint8_t LedPin1; /* GPIO number for LedPin[1] */ 282 uint8_t LedPin2; /* GPIO number for LedPin[2] */ 283 uint8_t padding8_4; 284 285 /* AVFS */ 286 uint8_t OverrideBtcGbCksOn; 287 uint8_t OverrideAvfsGbCksOn; 288 uint8_t PaddingAvfs8[2]; 289 290 GbVdroopTable_t BtcGbVdroopTableCksOn; 291 GbVdroopTable_t BtcGbVdroopTableCksOff; 292 293 QuadraticInt_t AvfsGbCksOn; /* Replacement equation */ 294 QuadraticInt_t AvfsGbCksOff; /* Replacement equation */ 295 296 uint8_t StaticVoltageOffsetVid[NUM_GFXCLK_DPM_LEVELS]; /* This values are added on to the final voltage calculation */ 297 298 /* Ageing Guardband Parameters */ 299 uint32_t AConstant[3]; 300 uint16_t DC_tol_sigma; 301 uint16_t Platform_mean; 302 uint16_t Platform_sigma; 303 uint16_t PSM_Age_CompFactor; 304 305 uint32_t DpmLevelPowerDelta; 306 307 uint8_t EnableBoostState; 308 uint8_t AConstant_Shift; 309 uint8_t DC_tol_sigma_Shift; 310 uint8_t PSM_Age_CompFactor_Shift; 311 312 uint16_t BoostStartTemperature; 313 uint16_t BoostStopTemperature; 314 315 PllSetting_t GfxBoostState; 316 317 uint8_t AcgEnable[NUM_GFXCLK_DPM_LEVELS]; 318 GbVdroopTable_t AcgBtcGbVdroopTable; 319 QuadraticInt_t AcgAvfsGb; 320 321 /* ACG Frequency Table, in Mhz */ 322 uint32_t AcgFreqTable[NUM_GFXCLK_DPM_LEVELS]; 323 324 /* Padding - ignore */ 325 uint32_t MmHubPadding[3]; /* SMU internal use */ 326 327 } PPTable_t; 328 329 typedef struct { 330 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) 331 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) 332 uint16_t MinUclk; 333 uint16_t MaxUclk; 334 335 uint8_t WmSetting; 336 uint8_t Padding[3]; 337 } WatermarkRowGeneric_t; 338 339 #define NUM_WM_RANGES 4 340 341 typedef enum { 342 WM_SOCCLK = 0, 343 WM_DCEFCLK, 344 WM_COUNT, 345 } WM_CLOCK_e; 346 347 typedef struct { 348 /* Watermarks */ 349 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 350 351 uint32_t MmHubPadding[7]; /* SMU internal use */ 352 } Watermarks_t; 353 354 #ifdef PPTABLE_V10_SMU_VERSION 355 typedef struct { 356 float AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS]; 357 float AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS]; 358 float AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS]; 359 float AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS]; 360 float DcBtcGb; 361 362 uint32_t MmHubPadding[7]; /* SMU internal use */ 363 } AvfsTable_t; 364 #else 365 typedef struct { 366 uint32_t AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS]; 367 uint32_t AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS]; 368 uint32_t AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS]; 369 uint32_t AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS]; 370 uint32_t DcBtcGb; 371 372 uint32_t MmHubPadding[7]; /* SMU internal use */ 373 } AvfsTable_t; 374 #endif 375 376 typedef struct { 377 uint16_t avgPsmCount[30]; 378 uint16_t minPsmCount[30]; 379 float avgPsmVoltage[30]; 380 float minPsmVoltage[30]; 381 382 uint32_t MmHubPadding[7]; /* SMU internal use */ 383 } AvfsDebugTable_t; 384 385 typedef struct { 386 uint8_t AvfsEn; 387 uint8_t AvfsVersion; 388 uint8_t Padding[2]; 389 390 int32_t VFT0_m1; /* Q8.24 */ 391 int32_t VFT0_m2; /* Q12.12 */ 392 int32_t VFT0_b; /* Q32 */ 393 394 int32_t VFT1_m1; /* Q8.16 */ 395 int32_t VFT1_m2; /* Q12.12 */ 396 int32_t VFT1_b; /* Q32 */ 397 398 int32_t VFT2_m1; /* Q8.16 */ 399 int32_t VFT2_m2; /* Q12.12 */ 400 int32_t VFT2_b; /* Q32 */ 401 402 int32_t AvfsGb0_m1; /* Q8.16 */ 403 int32_t AvfsGb0_m2; /* Q12.12 */ 404 int32_t AvfsGb0_b; /* Q32 */ 405 406 int32_t AcBtcGb_m1; /* Q8.24 */ 407 int32_t AcBtcGb_m2; /* Q12.12 */ 408 int32_t AcBtcGb_b; /* Q32 */ 409 410 uint32_t AvfsTempCold; 411 uint32_t AvfsTempMid; 412 uint32_t AvfsTempHot; 413 414 uint32_t InversionVoltage; /* in mV with 2 fractional bits */ 415 416 int32_t P2V_m1; /* Q8.24 */ 417 int32_t P2V_m2; /* Q12.12 */ 418 int32_t P2V_b; /* Q32 */ 419 420 uint32_t P2VCharzFreq; /* in 10KHz units */ 421 422 uint32_t EnabledAvfsModules; 423 424 uint32_t MmHubPadding[7]; /* SMU internal use */ 425 } AvfsFuseOverride_t; 426 427 /* These defines are used with the following messages: 428 * SMC_MSG_TransferTableDram2Smu 429 * SMC_MSG_TransferTableSmu2Dram 430 */ 431 #define TABLE_PPTABLE 0 432 #define TABLE_WATERMARKS 1 433 #define TABLE_AVFS 2 434 #define TABLE_AVFS_PSM_DEBUG 3 435 #define TABLE_AVFS_FUSE_OVERRIDE 4 436 #define TABLE_PMSTATUSLOG 5 437 #define TABLE_COUNT 6 438 439 /* These defines are used with the SMC_MSG_SetUclkFastSwitch message. */ 440 #define UCLK_SWITCH_SLOW 0 441 #define UCLK_SWITCH_FAST 1 442 443 /* GFX DIDT Configuration */ 444 #define SQ_Enable_MASK 0x1 445 #define SQ_IR_MASK 0x2 446 #define SQ_PCC_MASK 0x4 447 #define SQ_EDC_MASK 0x8 448 449 #define TCP_Enable_MASK 0x100 450 #define TCP_IR_MASK 0x200 451 #define TCP_PCC_MASK 0x400 452 #define TCP_EDC_MASK 0x800 453 454 #define TD_Enable_MASK 0x10000 455 #define TD_IR_MASK 0x20000 456 #define TD_PCC_MASK 0x40000 457 #define TD_EDC_MASK 0x80000 458 459 #define DB_Enable_MASK 0x1000000 460 #define DB_IR_MASK 0x2000000 461 #define DB_PCC_MASK 0x4000000 462 #define DB_EDC_MASK 0x8000000 463 464 #define SQ_Enable_SHIFT 0 465 #define SQ_IR_SHIFT 1 466 #define SQ_PCC_SHIFT 2 467 #define SQ_EDC_SHIFT 3 468 469 #define TCP_Enable_SHIFT 8 470 #define TCP_IR_SHIFT 9 471 #define TCP_PCC_SHIFT 10 472 #define TCP_EDC_SHIFT 11 473 474 #define TD_Enable_SHIFT 16 475 #define TD_IR_SHIFT 17 476 #define TD_PCC_SHIFT 18 477 #define TD_EDC_SHIFT 19 478 479 #define DB_Enable_SHIFT 24 480 #define DB_IR_SHIFT 25 481 #define DB_PCC_SHIFT 26 482 #define DB_EDC_SHIFT 27 483 484 #define REMOVE_FMAX_MARGIN_BIT 0x0 485 #define REMOVE_DCTOL_MARGIN_BIT 0x1 486 #define REMOVE_PLATFORM_MARGIN_BIT 0x2 487 488 #endif 489
Indexes created Thu Sep 25 16:09:42 GMT 2025