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    Searched defs:GroupSize (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULowerKernelAttributes.cpp 161 Value *GroupSize = WorkGroupSizes[I];
163 if (!GroupSize || !GridSize)
166 for (User *U : GroupSize->users()) {
212 Value *GroupSize = WorkGroupSizes[I];
213 if (!GroupSize)
217 GroupSize->replaceAllUsesWith(
219 GroupSize->getType(),
SIMachineScheduler.cpp 657 unsigned GroupSize;
672 GroupSize = 2;
674 GroupSize = 3;
676 GroupSize = 4;
767 } else if (Count == GroupSize) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InterleavedAccess.cpp 458 int GroupSize = std::ceil((VF - FirstGroupElement) / 3.0);
459 SizeInfo.push_back(GroupSize);
460 FirstGroupElement = ((GroupSize)*3 + FirstGroupElement) % VF;
559 SmallVector<int, 3> GroupSize;
565 setGroupSize(VT, GroupSize);
568 DecodePALIGNRMask(VT, GroupSize[2 - i], VPAlign[i], false);
570 DecodePALIGNRMask(VT, GroupSize[2] + GroupSize[1], VPAlign2, true, true);
571 DecodePALIGNRMask(VT, GroupSize[1], VPAlign3, true, true);
638 SmallVector<int, 3> GroupSize;
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegAllocGreedy.cpp 1304 const unsigned GroupSize = 8;
1305 SpillPlacement::BlockConstraint BCS[GroupSize];
1306 unsigned TBS[GroupSize];
1313 assert(T < GroupSize && "Array overflow");
1315 if (++T == GroupSize) {
1322 assert(B < GroupSize && "Array overflow");
1344 if (++B == GroupSize) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
AMDGPUInstPrinter.cpp 1364 uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1365 if (GroupSize > 1 &&
1366 isPowerOf2_64(GroupSize) &&
1367 OrMask < GroupSize &&
1372 O << formatDec(GroupSize);

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