1 /* $NetBSD: radeonfbvar.h,v 1.23 2023/07/23 21:06:52 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 #ifndef _DEV_PCI_RADEONFBVAR_H 42 #define _DEV_PCI_RADEONFBVAR_H 43 44 #include "opt_splash.h" 45 46 #include <sys/param.h> 47 #include <sys/types.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/wscons/wsdisplayvar.h> 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wsfont/wsfont.h> 54 #include <dev/rasops/rasops.h> 55 #include <dev/wscons/wsdisplay_vconsvar.h> 56 #include <dev/wscons/wsdisplay_glyphcachevar.h> 57 #include <dev/videomode/videomode.h> 58 #include <dev/videomode/edidvar.h> 59 #ifdef SPLASHSCREEN 60 #include <dev/splash/splash.h> 61 #endif 62 #include <dev/i2c/i2cvar.h> 63 64 /* XXX: change this when we complete the support for multi HEAD */ 65 #define RADEON_NDISPLAYS (1) 66 #define RADEON_MAXX (2048) 67 #define RADEON_MAXY (1536) 68 #define RADEON_MAXBPP (32) 69 #define RADEON_STRIDEALIGN (64) 70 #define RADEON_CURSORMAXX (64) 71 #define RADEON_CURSORMAXY (64) 72 #define RADEON_PANINCREMENT (1) 73 74 struct radeonfb_softc; 75 76 struct radeonfb_port { 77 int rp_number; 78 int rp_mon_type; 79 int rp_conn_type; 80 int rp_dac_type; 81 int rp_ddc_type; 82 int rp_tmds_type; 83 int rp_edid_valid; 84 struct edid_info rp_edid; 85 }; 86 87 /* connector values used by legacy bios */ 88 #define RADEON_CONN_NONE 0 89 #define RADEON_CONN_PROPRIETARY 1 /* think LVDS ribbon cable */ 90 #define RADEON_CONN_CRT 2 91 #define RADEON_CONN_DVI_I 3 92 #define RADEON_CONN_DVI_D 4 93 #define RADEON_CONN_CTV 5 94 #define RADEON_CONN_STV 6 95 #define RADEON_CONN_UNSUPPORTED 7 96 97 /* connector values used by atom bios */ 98 #define ATOM_CONN_NONE 0 99 #define ATOM_CONN_VGA 1 100 #define ATOM_CONN_DVI_I 2 101 #define ATOM_CONN_DVI_D 3 102 #define ATOM_CONN_DVI_A 4 103 #define ATOM_CONN_STV 5 104 #define ATOM_CONN_CTV 6 105 #define ATOM_CONN_LVDS 7 106 #define ATOM_CONN_DIGITAL 8 107 #define ATOM_CONN_UNSUPPORTED 9 108 109 #define RADEON_DDC_NONE 0 110 #define RADEON_DDC_MONID 1 111 #define RADEON_DDC_DVI 2 112 #define RADEON_DDC_VGA 3 113 #define RADEON_DDC_CRT2 4 114 115 #define RADEON_DAC_UNKNOWN -1 116 #define RADEON_DAC_PRIMARY 0 117 #define RADEON_DAC_TVDAC 1 118 119 #define RADEON_TMDS_UNKNOWN -1 120 #define RADEON_TMDS_INT 0 121 #define RADEON_TMDS_EXT 1 122 123 #define RADEON_MT_UNKNOWN -1 124 #define RADEON_MT_NONE 0 125 #define RADEON_MT_CRT 1 126 #define RADEON_MT_LCD 2 /* LVDS */ 127 #define RADEON_MT_DFP 3 /* TMDS */ 128 #define RADEON_MT_CTV 4 129 #define RADEON_MT_STV 5 130 131 struct radeonfb_i2c { 132 struct radeonfb_softc *ric_softc; 133 int ric_register; 134 struct i2c_controller ric_controller; 135 }; 136 137 struct radeonfb_crtc { 138 int rc_number; 139 struct videomode rc_videomode; 140 uint16_t rc_xoffset; 141 uint16_t rc_yoffset; 142 143 struct radeonfb_port *rc_port; 144 }; 145 146 struct radeonfb_cursor { 147 int rc_visible; 148 struct wsdisplay_curpos rc_pos; 149 struct wsdisplay_curpos rc_hot; 150 struct wsdisplay_curpos rc_size; 151 uint32_t rc_cmap[2]; 152 uint8_t rc_image[512]; /* 64x64x1 bit */ 153 uint8_t rc_mask[512]; /* 64x64x1 bit */ 154 }; 155 156 struct radeonfb_display { 157 struct radeonfb_softc *rd_softc; 158 int rd_number; /* 0 .. RADEON_NDISPLAYS */ 159 160 bus_size_t rd_offset; /* offset within FB memory */ 161 vaddr_t rd_fbptr; /* framebuffer pointer */ 162 vaddr_t rd_curptr; /* cursor data pointer */ 163 size_t rd_curoff; /* cursor offset */ 164 165 uint16_t rd_bpp; 166 uint16_t rd_virtx; 167 uint16_t rd_virty; 168 uint16_t rd_stride; 169 uint16_t rd_format; /* chip pixel format */ 170 171 uint16_t rd_xoffset; 172 uint16_t rd_yoffset; 173 174 uint32_t rd_bg; /* background */ 175 bool rd_console; 176 177 struct callout rd_bl_lvds_co; /* delayed lvds operation */ 178 uint32_t rd_bl_lvds_val; /* value of delayed lvds */ 179 int rd_bl_on; 180 int rd_bl_level; 181 182 int rd_wsmode; 183 184 int rd_ncrtcs; 185 struct radeonfb_crtc rd_crtcs[2]; 186 187 struct radeonfb_cursor rd_cursor, rd_tempcursor; 188 /* XXX: this should probably be an array for CRTCs */ 189 //struct videomode rd_videomode; 190 191 struct wsscreen_list rd_wsscreenlist; 192 struct wsscreen_descr rd_wsscreens_storage[1]; 193 struct wsscreen_descr *rd_wsscreens; 194 struct vcons_screen rd_vscreen; 195 struct vcons_data rd_vd; 196 void (*rd_putchar)(void *, int, int, u_int, long); 197 glyphcache rd_gc; 198 199 uint8_t rd_cmap_red[256]; 200 uint8_t rd_cmap_green[256]; 201 uint8_t rd_cmap_blue[256]; 202 203 #ifdef SPLASHSCREEN 204 struct splash_info rd_splash; 205 #endif 206 }; 207 208 struct radeon_tmds_pll { 209 uint32_t rtp_freq; 210 uint32_t rtp_pll; 211 }; 212 213 struct radeonfb_softc { 214 device_t sc_dev; 215 uint16_t sc_family; 216 uint16_t sc_flags; 217 pcireg_t sc_id; 218 219 bus_space_tag_t sc_regt; 220 bus_space_handle_t sc_regh; 221 bus_size_t sc_regsz; 222 bus_addr_t sc_regaddr; 223 224 bus_space_tag_t sc_memt; 225 bus_space_handle_t sc_memh; 226 bus_size_t sc_memsz; 227 bus_addr_t sc_memaddr; 228 229 bus_space_tag_t sc_iot; 230 bus_space_handle_t sc_ioh; 231 bus_size_t sc_iosz; 232 bus_addr_t sc_ioaddr; 233 234 int sc_needs_unmap; 235 int sc_mapped; 236 237 /* size of a single display */ 238 int sc_maxx; 239 int sc_maxy; 240 int sc_maxbpp; 241 int sc_fboffset; 242 int sc_fbsize; 243 244 bus_space_tag_t sc_romt; 245 bus_space_handle_t sc_romh; 246 bus_size_t sc_romsz; 247 bus_addr_t sc_romaddr; 248 bus_space_handle_t sc_biosh; 249 250 bus_dma_tag_t sc_dmat; 251 252 uint16_t sc_refclk; 253 uint16_t sc_refdiv; 254 uint32_t sc_minpll; 255 uint32_t sc_maxpll; 256 257 pci_chipset_tag_t sc_pc; 258 pcitag_t sc_pt; 259 260 /* card's idea of addresses, internally */ 261 uint32_t sc_aperbase; 262 263 int sc_ndisplays; 264 struct radeonfb_display sc_displays[RADEON_NDISPLAYS]; 265 266 int sc_nports; 267 struct radeonfb_port sc_ports[2]; 268 269 struct radeon_tmds_pll sc_tmds_pll[4]; 270 271 struct radeonfb_i2c sc_i2c[4]; 272 273 uint8_t *sc_bios; 274 bus_size_t sc_biossz; 275 uint32_t sc_fp_gen_cntl; 276 277 char sc_modebuf[64]; 278 const char *sc_defaultmode; 279 }; 280 281 /* chip families */ 282 #define RADEON_R100 1 283 #define RADEON_RV100 2 284 #define RADEON_RS100 3 285 #define RADEON_RV200 4 286 #define RADEON_RS200 5 287 #define RADEON_R200 6 288 #define RADEON_RV250 7 289 #define RADEON_RS300 8 290 #define RADEON_RV280 9 291 #define RADEON_R300 10 292 #define RADEON_R350 11 293 #define RADEON_RV350 12 294 #define RADEON_RV380 13 295 #define RADEON_R420 14 296 #define RADEON_R580 15 297 #define RADEON_FAMILIES 16 298 299 /* feature flags */ 300 #define RFB_MOB (1 << 0) /* Mobility */ 301 #define RFB_NCRTC2 (1 << 1) /* No CRTC2 */ 302 #define RFB_IGP (1 << 2) 303 #define RFB_R300CG (1 << 3) 304 #define RFB_SDAC (1 << 4) /* Single DAC */ 305 #define RFB_R300 (1 << 5) /* R300 variants -- newer parts */ 306 #define RFB_RV100 (1 << 6) /* RV100 variants -- previous gen */ 307 #define RFB_ATOM (1 << 7) /* ATOM bios */ 308 #define RFB_INV_BLIGHT (1 << 8) /* backlight level inverted */ 309 #define RFB_IS_AVIVO (1 << 9) /* MC and CRTCs are different here */ 310 311 #define IS_MOBILITY(sc) ((sc)->sc_flags & RFB_MOB) 312 #define HAS_CRTC2(sc) (((sc)->sc_flags & RFB_NCRTC2) == 0) 313 314 #define IS_R300(sc) ((sc)->sc_flags & RFB_R300) 315 #define HAS_R300CG(sc) ((sc)->sc_flags & RFB_R300CG) 316 #define HAS_SDAC(sc) ((sc)->sc_flags & RFB_SDAC) 317 #define IS_RV100(sc) ((sc)->sc_flags & RFB_RV100) 318 #define IS_IGP(sc) ((sc)->sc_flags & RFB_IGP) 319 #define IS_ATOM(sc) ((sc)->sc_flags & RFB_ATOM) 320 #define IS_AVIVO(sc) ((sc)->sc_flags & RFB_IS_AVIVO) 321 322 #define RADEON_TIMEOUT 2000000 323 324 #define GET32(sc, r) radeonfb_get32(sc, r) 325 #define PUT32(sc, r, v) radeonfb_put32(sc, r, v) 326 #define PUT32S(sc, r, v) radeonfb_put32s(sc, r, v) 327 #define SET32(sc, r, v) PUT32(sc, r, GET32(sc, r) | (v)) 328 #define CLR32(sc, r, v) PUT32(sc, r, GET32(sc, r) & ~(v)) 329 #define PATCH32(sc, r, v, m) PUT32(sc, r, (GET32(sc, r) & (m)) | (v)) 330 331 332 #define GETPLL(sc, r) radeonfb_getpll(sc, r) 333 #define PUTPLL(sc, r, v) radeonfb_putpll(sc, r, v) 334 #define SETPLL(sc, r, v) PUTPLL(sc, r, GETPLL(sc, r) | (v)) 335 #define CLRPLL(sc, r, v) PUTPLL(sc, r, GETPLL(sc, r) & ~(v)) 336 #define PATCHPLL(sc, r, v, m) PUTPLL(sc, r, (GETPLL(sc, r) & (m)) | (v)) 337 338 #define GETROM32(sc, r) bus_space_read_4(sc->sc_romt, sc->sc_romh, r) 339 #define GETROM16(sc, r) bus_space_read_2(sc->sc_romt, sc->sc_romh, r) 340 #define GETROM8(sc, r) bus_space_read_1(sc->sc_romt, sc->sc_romh, r) 341 342 /* 343 * Some values in BIOS are misaligned... 344 */ 345 #define GETBIOS8(sc, r) ((sc)->sc_bios[(r)]) 346 347 #define GETBIOS16(sc, r) \ 348 ((GETBIOS8(sc, (r) + 1) << 8) | GETBIOS8(sc, (r))) 349 350 #define GETBIOS32(sc, r) \ 351 ((GETBIOS16(sc, (r) + 2) << 16) | GETBIOS16(sc, (r))) 352 353 #define XNAME(sc) device_xname(sc->sc_dev) 354 355 #define DIVIDE(x,y) (((x) + (y / 2)) / (y)) 356 357 uint32_t radeonfb_get32(struct radeonfb_softc *, uint32_t); 358 void radeonfb_put32(struct radeonfb_softc *, uint32_t, uint32_t); 359 void radeonfb_put32s(struct radeonfb_softc *, uint32_t, uint32_t); 360 void radeonfb_mask32(struct radeonfb_softc *, uint32_t, uint32_t, uint32_t); 361 362 uint32_t radeonfb_getindex(struct radeonfb_softc *, uint32_t); 363 void radeonfb_putindex(struct radeonfb_softc *, uint32_t, uint32_t); 364 void radeonfb_maskindex(struct radeonfb_softc *, uint32_t, uint32_t, uint32_t); 365 366 uint32_t radeonfb_getpll(struct radeonfb_softc *, uint32_t); 367 void radeonfb_putpll(struct radeonfb_softc *, uint32_t, uint32_t); 368 void radeonfb_maskpll(struct radeonfb_softc *, uint32_t, uint32_t, uint32_t); 369 370 int radeonfb_bios_init(struct radeonfb_softc *); 371 372 void radeonfb_i2c_init(struct radeonfb_softc *); 373 int radeonfb_i2c_read_edid(struct radeonfb_softc *, int, uint8_t *); 374 375 #endif /* _DEV_PCI_RADEONFBVAR_H */ 376
Indexes created Sat Sep 20 22:09:52 GMT 2025