Home | History | Annotate | Line # | Download | only in hpc 
      1 /*
      2  * Copyright (c) 2025 Stephen M. Rumble <rumble (at) ephemeral.org>
      3  *
      4  * Permission to use, copy, modify, and distribute this software for any
      5  * purpose with or without fee is hereby granted, provided that the above
      6  * copyright notice and this permission notice appear in all copies.
      7  *
      8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
      9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     15  */
     16 
     17 #ifndef _ARCH_SGIMIPS_HPC_HAUDREG_H_
     18 #define _ARCH_SGIMIPS_HPC_HAUDREG_H_
     19 
     20 #define HAUD_DMA_XFER_WORD_LEN	0x00000000      /* DMA transfer length (words)*/
     21 #define HAUD_GIO_ADDR_16LSB	0x00000004      /* Lower 16 bits of GIO addr */
     22 #define HAUD_GIO_ADDR_16MSB	0x00000008      /* Upper 16 bits of GIO addr */
     23 #define HAUD_PBUS_ADDR		0x0000000c      /* 16-bit PBus address */
     24 #define HAUD_DMA_CTL		0x00000010      /* DMA control register */
     25 #define   HAUD_DMA_CTL_START	       0x1      /* Start DMA engine */
     26 #define   HAUD_DMA_CTL_TO_CPU	       0x2      /* 0: DSP->CPU, 1: CPU->DSP */
     27 #define   HAUD_DMA_CTL_MODE	       0x4      /* 0: normal, 1: folded */
     28 #define HAUD_COUNTER		0x00000014      /* Read-only counter (24-bit) */
     29 #define HAUD_TX_HANDSHAKE	0x00000018      /* 16-bit tx handshake */
     30 #define HAUD_RX_HANDSHAKE	0x0000001c      /* 16-bit rx handshake */
     31 #define HAUD_CPU_INTR_STAT	0x00000020      /* CPU interrupt status */
     32 #define   HAUD_CPU_INTR_STAT_DMA       0x1      /* DSP completed DMA */
     33 #define   HAUD_CPU_INTR_STAT_TX        0x2      /* DSP wrote to TX_HANDSHAKE */
     34 #define   HAUD_CPU_INTR_STAT_RX        0x4      /* DSP read from RX_HANDSHAKE */
     35 #define HAUD_CPU_INTR_MASK	0x00000024      /* CPU interrupt mask */
     36 #define   HAUD_CPU_INTR_MASK_DMA_ENBL  0x1      /* Enable post-DMA interrupt */
     37 #define   HAUD_CPU_INTR_MASK_TX_ENBL   0x2      /* Enable post-TX interrupt */
     38 #define   HAUD_CPU_INTR_MASK_RX_ENBL   0x4      /* Enable post-RX interrupt */
     39 #define HAUD_MISC_CSR		0x00000030      /* Misc control & status */
     40 #define   HAUD_MISC_CSR_RESET	      0x01	/* Hard reset the DSP */
     41 #define   HAUD_MISC_CSR_IRQA          0x02	/* Set /IRQA line per polarity*/
     42 #define   HAUD_MISC_CSR_IRQA_POL      0x04	/* Polarity, 0: low, 1: high */
     43 #define   HAUD_MISC_CSR_32K_SRAM      0x08	/* 0: 8K-word SRAM, 1: 32K */
     44 #define   HAUD_MISC_CSR_PBUS_MASK     0x70	/* PBus sign extension bits */
     45 #define HAUD_BURST_CTL		0x00000034      /* DMA burst control */
     46 
     47 #endif /* _ARCH_SGIMIPS_HPC_HAUDREG_H_ */
     48