1 /* $NetBSD: tegra_hdmireg.h,v 1.6 2021/12/05 07:56:10 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_HDMIREG_H 30 #define _ARM_TEGRA_HDMIREG_H 31 32 /* 33 * HDMI Registers 34 */ 35 #define HDMI_CTXSW_REG 0x000 36 37 #define HDMI_NV_PDISP_SOR_STATE0_REG 0x004 38 #define HDMI_NV_PDISP_SOR_STATE0_UPDATE __BIT(0) 39 40 #define HDMI_NV_PDISP_SOR_STATE1_REG 0x008 41 #define HDMI_NV_PDISP_SOR_STATE1_ARM_SHOW_VGA __BIT(4) 42 #define HDMI_NV_PDISP_SOR_STATE1_ATTACHED __BIT(3) 43 #define HDMI_NV_PDISP_SOR_STATE1_ASY_ORMODE __BIT(2) 44 #define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE __BITS(1,0) 45 #define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_SLEEP 0 46 #define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_SNOOZE 1 47 #define HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_AWAKE 2 48 49 #define HDMI_NV_PDISP_SOR_STATE2_REG 0x00c 50 #define HDMI_NV_PDISP_SOR_STATE2_ASY_DEPOL __BIT(14) 51 #define HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL __BIT(13) 52 #define HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL __BIT(12) 53 #define HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL __BITS(11,8) 54 #define HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE __BITS(7,6) 55 #define HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER __BITS(5,4) 56 #define HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER __BITS(3,0) 57 58 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU0_REG 0x068 59 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0_REG 0x06c 60 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU1_REG 0x070 61 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU2_REG 0x074 62 63 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_REG 0x078 64 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_CHKSUM_HW __BIT(9) 65 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_SINGLE __BIT(8) 66 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_OTHER __BIT(4) 67 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE __BIT(0) 68 69 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS_REG 0x07c 70 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER_REG 0x080 71 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_REG 0x084 72 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_REG 0x088 73 74 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_REG 0x08c 75 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW __BIT(9) 76 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_SINGLE __BIT(8) 77 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_OTHER __BIT(4) 78 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_ENABLE __BIT(0) 79 80 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS_REG 0x090 81 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER_REG 0x094 82 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_REG 0x098 83 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_REG 0x09c 84 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_REG 0x0a0 85 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_REG 0x0a4 86 87 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_REG 0x0a8 88 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_AUDIO __BIT(16) 89 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_HBLANK __BIT(12) 90 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_SINGLE __BIT(8) 91 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_OTHER __BIT(4) 92 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_ENABLE __BIT(0) 93 94 #define HDMI_NV_PDISP_HDMI_GENERIC_STATUS_REG 0x0ac 95 #define HDMI_NV_PDISP_HDMI_GENERIC_HEADER_REG 0x0b0 96 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK0_LOW_REG 0x0b4 97 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK0_HIGH_REG 0x0b8 98 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK1_LOW_REG 0x0bc 99 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK1_HIGH_REG 0x0c0 100 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK2_LOW_REG 0x0c4 101 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK2_HIGH_REG 0x0c8 102 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK3_LOW_REG 0x0cc 103 #define HDMI_NV_PDISP_HDMI_GENERIC_INFOFRAME_SUBPACK3_HIGH_REG 0x0d0 104 #define HDMI_NV_PDISP_HDMI_ACR_CTRL_REG 0x0d4 105 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW_REG 0x0d8 106 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH_REG 0x0dc 107 #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW_REG 0x0e0 108 #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH_REG 0x0e4 109 #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW_REG 0x0e8 110 #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH_REG 0x0ec 111 #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW_REG 0x0f0 112 #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH_REG 0x0f4 113 #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW_REG 0x0f8 114 #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH_REG 0x0fc 115 #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW_REG 0x100 116 #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH_REG 0x104 117 #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW_REG 0x108 118 #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH_REG 0x10c 119 120 #define HDMI_NV_PDISP_HDMI_CTRL_REG 0x110 121 #define HDMI_NV_PDISP_HDMI_CTRL_ENABLE __BIT(30) 122 #define HDMI_NV_PDISP_HDMI_CTRL_CA_SELECT __BIT(28) 123 #define HDMI_NV_PDISP_HDMI_CTRL_SS_SELECT __BIT(27) 124 #define HDMI_NV_PDISP_HDMI_CTRL_SF_SELECT __BIT(26) 125 #define HDMI_NV_PDISP_HDMI_CTRL_CC_SELECT __BIT(25) 126 #define HDMI_NV_PDISP_HDMI_CTRL_CT_SELECT __BIT(24) 127 #define HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET __BITS(20,16) 128 #define HDMI_NV_PDISP_HDMI_CTRL_SAMPLE_FLAT __BIT(12) 129 #define HDMI_NV_PDISP_HDMI_CTRL_AUDIO_LAYOUT_SELECT __BIT(10) 130 #define HDMI_NV_PDISP_HDMI_CTRL_AUDIO_LAYOUT __BIT(8) 131 #define HDMI_NV_PDISP_HDMI_CTRL_REKEY __BITS(6,0) 132 133 #define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT_REG 0x114 134 #define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW_REG 0x118 135 #define HDMI_NV_PDISP_HDMI_GCP_CTRL_REG 0x11c 136 #define HDMI_NV_PDISP_HDMI_GCP_STATUS_REG 0x120 137 #define HDMI_NV_PDISP_HDMI_GCP_SUBPACK_REG 0x124 138 #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1_REG 0x128 139 #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2_REG 0x12c 140 #define HDMI_NV_PDISP_HDMI_EMU0_REG 0x130 141 #define HDMI_NV_PDISP_HDMI_EMU1_REG 0x134 142 #define HDMI_NV_PDISP_HDMI_EMU1_RDATA_REG 0x138 143 144 #define HDMI_NV_PDISP_HDMI_SPARE_REG 0x13c 145 #define HDMI_NV_PDISP_HDMI_SPARE_HW_CTS __BIT(0) 146 #define HDMI_NV_PDISP_HDMI_SPARE_FORCE_SW_CTS __BIT(1) 147 #define HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL __BITS(18,16) 148 149 #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1_REG 0x140 150 #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2_REG 0x144 151 #define HDMI_NV_PDISP_CRC_CONTROL_REG 0x258 152 153 #define HDMI_NV_PDISP_INPUT_CONTROL_REG 0x25c 154 #define HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE __BIT(1) 155 #define HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT __BIT(0) 156 157 #define HDMI_NV_PDISP_SCRATCH_REG 0x260 158 #define HDMI_NV_PDISP_PE_CURRENT_REG 0x264 159 #define HDMI_NV_PDISP_KEY_CTRL_REG 0x268 160 #define HDMI_NV_PDISP_KEY_DEBUG0_REG 0x26c 161 #define HDMI_NV_PDISP_KEY_DEBUG1_REG 0x270 162 #define HDMI_NV_PDISP_KEY_DEBUG2_REG 0x274 163 #define HDMI_NV_PDISP_KEY_HDCP_KEY_0_REG 0x278 164 #define HDMI_NV_PDISP_KEY_HDCP_KEY_1_REG 0x27c 165 #define HDMI_NV_PDISP_KEY_HDCP_KEY_2_REG 0x280 166 #define HDMI_NV_PDISP_KEY_HDCP_KEY_3_REG 0x284 167 #define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG_REG 0x288 168 #define HDMI_NV_PDISP_KEY_SKEY_INDEX_REG 0x28c 169 #define HDMI_NV_PDISP_INT_STATUS_REG 0x330 170 #define HDMI_NV_PDISP_INT_MASK_REG 0x334 171 #define HDMI_NV_PDISP_INT_ENABLE_REG 0x338 172 #define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_CTRL_REG 0x358 173 #define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_STATUS_REG 0x35c 174 #define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_HEADER_REG 0x360 175 #define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_REG 0x364 176 #define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_REG 0x368 177 #define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_REG 0x36c 178 #define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_REG 0x370 179 #define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_REG 0x374 180 #define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_REG 0x378 181 #define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_REG 0x37c 182 #define HDMI_NV_PDISP_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_REG 0x380 183 184 /* 185 * Serial Output Resource Registers 186 */ 187 #define HDMI_NV_PDISP_SOR_PWR_REG 0x154 188 #define HDMI_NV_PDISP_SOR_PWR_SETTING_NEW __BIT(31) 189 #define HDMI_NV_PDISP_SOR_PWR_MODE __BIT(28) 190 #define HDMI_NV_PDISP_SOR_PWR_HALT_DELAY __BIT(24) 191 #define HDMI_NV_PDISP_SOR_PWR_SAFE_START __BIT(17) 192 #define HDMI_NV_PDISP_SOR_PWR_SAFE_STATE __BIT(16) 193 #define HDMI_NV_PDISP_SOR_PWR_NORMAL_START __BIT(1) 194 #define HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE __BIT(0) 195 196 #define HDMI_NV_PDISP_SOR_TEST_REG 0x158 197 198 #define HDMI_NV_PDISP_SOR_PLL0_REG 0x15c 199 #define HDMI_NV_PDISP_SOR_PLL0_TX_REG_LOAD __BITS(29,28) 200 #define HDMI_NV_PDISP_SOR_PLL0_ICHPMP __BITS(27,24) 201 #define HDMI_NV_PDISP_SOR_PLL0_FILTER __BITS(19,16) 202 #define HDMI_NV_PDISP_SOR_PLL0_BG_V17_S __BITS(15,12) 203 #define HDMI_NV_PDISP_SOR_PLL0_VCOCAP __BITS(11,8) 204 #define HDMI_NV_PDISP_SOR_PLL0_PULLDOWN __BIT(5) 205 #define HDMI_NV_PDISP_SOR_PLL0_RESISTORSEL __BIT(4) 206 #define HDMI_NV_PDISP_SOR_PLL0_PDPORT __BIT(3) 207 #define HDMI_NV_PDISP_SOR_PLL0_VCOPD __BIT(2) 208 #define HDMI_NV_PDISP_SOR_PLL0_PDBG __BIT(1) 209 #define HDMI_NV_PDISP_SOR_PLL0_PWR __BIT(0) 210 211 #define HDMI_NV_PDISP_SOR_PLL1_REG 0x160 212 #define HDMI_NV_PDISP_SOR_PLL2_REG 0x164 213 214 #define HDMI_NV_PDISP_SOR_CSTM_REG 0x168 215 #define HDMI_NV_PDISP_SOR_CSTM_ROTDAT __BITS(30,28) 216 #define HDMI_NV_PDISP_SOR_CSTM_ROTCLK __BITS(27,24) 217 #define HDMI_NV_PDISP_SOR_CSTM_PLLDIV __BIT(21) 218 #define HDMI_NV_PDISP_SOR_CSTM_BALANCED __BIT(19) 219 #define HDMI_NV_PDISP_SOR_CSTM_NEW_MODE __BIT(18) 220 #define HDMI_NV_PDISP_SOR_CSTM_DUP_SYNC __BIT(17) 221 #define HDMI_NV_PDISP_SOR_CSTM_LVDS_EN __BIT(16) 222 #define HDMI_NV_PDISP_SOR_CSTM_LINKACTB __BIT(15) 223 #define HDMI_NV_PDISP_SOR_CSTM_LINKACTA __BIT(14) 224 #define HDMI_NV_PDISP_SOR_CSTM_MODE __BITS(13,12) 225 #define HDMI_NV_PDISP_SOR_CSTM_MODE_LVDS 0 226 #define HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS 1 227 #define HDMI_NV_PDISP_SOR_CSTM_UPPER __BIT(11) 228 #define HDMI_NV_PDISP_SOR_CSTM_PD_TXCB __BIT(9) 229 #define HDMI_NV_PDISP_SOR_CSTM_PD_TXCA __BIT(8) 230 #define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_3 __BIT(7) 231 #define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_2 __BIT(6) 232 #define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_1 __BIT(5) 233 #define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_0 __BIT(4) 234 #define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_3 __BIT(3) 235 #define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_2 __BIT(2) 236 #define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_1 __BIT(1) 237 #define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_0 __BIT(0) 238 239 #define HDMI_NV_PDISP_SOR_LVDS_REG 0x16c 240 #define HDMI_NV_PDISP_SOR_CRCA_REG 0x170 241 #define HDMI_NV_PDISP_SOR_CRCB_REG 0x174 242 243 #define HDMI_NV_PDISP_SOR_BLANK_REG 0x178 244 #define HDMI_NV_PDISP_SOR_BLANK_STATUS __BIT(2) 245 #define HDMI_NV_PDISP_SOR_BLANK_TRANSITION __BIT(1) 246 #define HDMI_NV_PDISP_SOR_BLANK_OVERRIDE __BIT(0) 247 248 #define HDMI_NV_PDISP_SOR_SEQ_CTL_REG 0x17c 249 #define HDMI_NV_PDISP_SOR_SEQ_CTL_SWITCH __BIT(30) 250 #define HDMI_NV_PDISP_SOR_SEQ_CTL_STATUS __BIT(28) 251 #define HDMI_NV_PDISP_SOR_SEQ_CTL_PC __BITS(19,16) 252 #define HDMI_NV_PDISP_SOR_SEQ_CTL_PD_PC_ALT __BITS(15,12) 253 #define HDMI_NV_PDISP_SOR_SEQ_CTL_PD_PC __BITS(11,8) 254 #define HDMI_NV_PDISP_SOR_SEQ_CTL_PU_PC_ALT __BITS(7,4) 255 #define HDMI_NV_PDISP_SOR_SEQ_CTL_PU_PC __BITS(3,0) 256 257 #define HDMI_NV_PDISP_SOR_SEQ_INST0_REG 0x180 258 #define HDMI_NV_PDISP_SOR_SEQ_INST1_REG 0x184 259 #define HDMI_NV_PDISP_SOR_SEQ_INST2_REG 0x188 260 #define HDMI_NV_PDISP_SOR_SEQ_INST3_REG 0x18c 261 #define HDMI_NV_PDISP_SOR_SEQ_INST4_REG 0x190 262 #define HDMI_NV_PDISP_SOR_SEQ_INST5_REG 0x194 263 #define HDMI_NV_PDISP_SOR_SEQ_INST6_REG 0x198 264 #define HDMI_NV_PDISP_SOR_SEQ_INST7_REG 0x19c 265 #define HDMI_NV_PDISP_SOR_SEQ_INST8_REG 0x1a0 266 #define HDMI_NV_PDISP_SOR_SEQ_INST9_REG 0x1a4 267 #define HDMI_NV_PDISP_SOR_SEQ_INSTA_REG 0x1a8 268 #define HDMI_NV_PDISP_SOR_SEQ_INSTB_REG 0x1ac 269 #define HDMI_NV_PDISP_SOR_SEQ_INSTC_REG 0x1b0 270 #define HDMI_NV_PDISP_SOR_SEQ_INSTD_REG 0x1b4 271 #define HDMI_NV_PDISP_SOR_SEQ_INSTE_REG 0x1b8 272 #define HDMI_NV_PDISP_SOR_SEQ_INSTF_REG 0x1bc 273 #define HDMI_NV_PDISP_SOR_SEQ_INST_PLL_PULLDOWN __BIT(31) 274 #define HDMI_NV_PDISP_SOR_SEQ_INST_POWERDOWN_MACRO __BIT(30) 275 #define HDMI_NV_PDISP_SOR_SEQ_INST_ASSERT_PLL_RESETV __BIT(29) 276 #define HDMI_NV_PDISP_SOR_SEQ_INST_BLANK_V __BIT(28) 277 #define HDMI_NV_PDISP_SOR_SEQ_INST_BLANK_H __BIT(27) 278 #define HDMI_NV_PDISP_SOR_SEQ_INST_BLANK_DE __BIT(26) 279 #define HDMI_NV_PDISP_SOR_SEQ_INST_BLACK_DATA __BIT(25) 280 #define HDMI_NV_PDISP_SOR_SEQ_INST_TRISTATE_IOS __BIT(24) 281 #define HDMI_NV_PDISP_SOR_SEQ_INST_DRIVE_PWM_OUT_LO __BIT(23) 282 #define HDMI_NV_PDISP_SOR_SEQ_INST_PIN_B __BIT(22) 283 #define HDMI_NV_PDISP_SOR_SEQ_INST_PIN_A __BIT(21) 284 #define HDMI_NV_PDISP_SOR_SEQ_INST_HALT __BIT(15) 285 #define HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS __BITS(13,12) 286 #define HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME __BITS(9,0) 287 288 #define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_REG 0x1f8 289 290 #define HDMI_NV_PDISP_SOR_REFCLK_REG 0x254 291 #define HDMI_NV_PDISP_SOR_REFCLK_DIV_INT __BITS(15,8) 292 #define HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC __BITS(7,6) 293 294 #define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_REG 0x344 295 #define HDMI_NV_PDISP_SOR_PAD_CTLS0_REG 0x348 296 #define HDMI_NV_PDISP_SOR_PAD_CTLS1_REG 0x34c 297 298 /* 299 * Audio Registers 300 */ 301 #define HDMI_NV_PDISP_AUDIO_N_REG 0x230 302 #define HDMI_NV_PDISP_AUDIO_N_LOOKUP __BIT(28) 303 #define HDMI_NV_PDISP_AUDIO_N_GENERATE __BIT(24) 304 #define HDMI_NV_PDISP_AUDIO_N_RESETF __BIT(20) 305 #define HDMI_NV_PDISP_AUDIO_N_VALUE __BITS(19,0) 306 307 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_REG 0x2b0 308 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INPUT_MODE __BIT(31) 309 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INJECT_NULLSMPL __BIT(29) 310 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT __BITS(21,20) 311 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO 0 312 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF 1 313 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL 2 314 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ __BITS(19,16) 315 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_32_0KHZ 3 316 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_44_1KHZ 0 317 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_88_2KHZ 8 318 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_176_4KHZ 12 319 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_48_0KHZ 2 320 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_96_0KHZ 10 321 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_192_0KHZ 14 322 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SAMPLING_FREQ_UNKNOWN 1 323 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_AFIFO_FLUSH __BIT(12) 324 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_PORT_CONNECTIVITY __BIT(0) 325 326 #define HDMI_NV_PDISP_SOR_AUDIO_DEBUG_REG 0x2b4 327 #define HDMI_NV_PDISP_SOR_AUDIO_SPARE0_REG 0x2b8 328 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0320_REG 0x2bc 329 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0441_REG 0x2c0 330 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0882_REG 0x2c4 331 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1764_REG 0x2c8 332 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0480_REG 0x2cc 333 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0960_REG 0x2d0 334 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1920_REG 0x2d4 335 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_REG 0x2d8 336 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_REG 0x2dc 337 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_REG 0x2e0 338 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_REG 0x2e4 339 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_REG 0x2e8 340 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_REG 0x2ec 341 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELF_BUFWR_REG 0x2f0 342 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_REG 0x2f4 343 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CP_REG 0x2f8 344 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320_REG 0x2fc 345 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441_REG 0x300 346 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882_REG 0x304 347 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764_REG 0x308 348 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_REG 0x30c 349 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960_REG 0x310 350 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920_REG 0x314 351 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_REG 0x318 352 #define HDMI_NV_PDISP_SOR_AUDIO_GEN_CTRL_REG 0x31c 353 #define HDMI_NV_HDACODEC_AUDIO_GEN_CTL_REG 0x354 354 355 #endif /* _ARM_TEGRA_HDMIREG_H */ 356
Indexes created Sun Sep 28 07:09:56 GMT 2025