1 /* $NetBSD: hdp_5_0_0_sh_mask.h,v 1.2 2021/12/18 23:45:16 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _hdp_5_0_0_SH_MASK_HEADER 24 #define _hdp_5_0_0_SH_MASK_HEADER 25 26 27 // addressBlock: hdp_hdpdec 28 //HDP_MMHUB_TLVL 29 #define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0 30 #define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4 31 #define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8 32 #define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc 33 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10 34 #define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L 35 #define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L 36 #define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L 37 #define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L 38 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L 39 //HDP_MMHUB_UNITID 40 #define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0 41 #define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8 42 #define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10 43 #define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL 44 #define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L 45 #define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L 46 //HDP_NONSURFACE_BASE 47 #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0 48 #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL 49 //HDP_NONSURFACE_INFO 50 #define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4 51 #define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8 52 #define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L 53 #define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L 54 //HDP_NONSURFACE_BASE_HI 55 #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0 56 #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL 57 //HDP_SURFACE_WRITE_FLAGS 58 #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT 0x0 59 #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT 0x1 60 #define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK 0x00000001L 61 #define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK 0x00000002L 62 //HDP_SURFACE_READ_FLAGS 63 #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT 0x0 64 #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT 0x1 65 #define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK 0x00000001L 66 #define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK 0x00000002L 67 //HDP_SURFACE_WRITE_FLAGS_CLR 68 #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT 0x0 69 #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT 0x1 70 #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK 0x00000001L 71 #define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK 0x00000002L 72 //HDP_SURFACE_READ_FLAGS_CLR 73 #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT 0x0 74 #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT 0x1 75 #define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK 0x00000001L 76 #define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK 0x00000002L 77 //HDP_NONSURF_FLAGS 78 #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 79 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 80 #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L 81 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L 82 //HDP_NONSURF_FLAGS_CLR 83 #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 84 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 85 #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L 86 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L 87 //HDP_HOST_PATH_CNTL 88 #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 89 #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb 90 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12 91 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 92 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 93 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16 94 #define HDP_HOST_PATH_CNTL__RD_CPL_BUF_EN__SHIFT 0x17 95 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d 96 #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e 97 #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f 98 #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L 99 #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L 100 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L 101 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L 102 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L 103 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L 104 #define HDP_HOST_PATH_CNTL__RD_CPL_BUF_EN_MASK 0x00800000L 105 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L 106 #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L 107 #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L 108 //HDP_SW_SEMAPHORE 109 #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 110 #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL 111 //HDP_LAST_SURFACE_HIT 112 #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 113 #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L 114 //HDP_READ_CACHE_INVALIDATE 115 #define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT 0x0 116 #define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK 0x00000001L 117 //HDP_OUTSTANDING_REQ 118 #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 119 #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 120 #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL 121 #define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L 122 //HDP_MISC_CNTL 123 #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 124 #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2 125 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 126 #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 127 #define HDP_MISC_CNTL__RAW_ADDR_CAM_ENABLE__SHIFT 0x7 128 #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT 0x8 129 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb 130 #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 131 #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT 0x16 132 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17 133 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 134 #define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT 0x19 135 #define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1a 136 #define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1b 137 #define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT 0x1c 138 #define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d 139 #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e 140 #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L 141 #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL 142 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L 143 #define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L 144 #define HDP_MISC_CNTL__RAW_ADDR_CAM_ENABLE_MASK 0x00000080L 145 #define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK 0x00000100L 146 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L 147 #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L 148 #define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK 0x00400000L 149 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L 150 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L 151 #define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK 0x02000000L 152 #define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x04000000L 153 #define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x08000000L 154 #define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK 0x10000000L 155 #define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK 0x20000000L 156 #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L 157 //HDP_MEM_POWER_CTRL 158 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN__SHIFT 0x0 159 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN__SHIFT 0x1 160 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN__SHIFT 0x2 161 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN__SHIFT 0x3 162 #define HDP_MEM_POWER_CTRL__IPH_MEM_IDLE_HYSTERESIS__SHIFT 0x4 163 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 164 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe 165 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10 166 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT 0x11 167 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT 0x12 168 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT 0x13 169 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14 170 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18 171 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0x1e 172 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 173 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 174 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK 0x00000004L 175 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK 0x00000008L 176 #define HDP_MEM_POWER_CTRL__IPH_MEM_IDLE_HYSTERESIS_MASK 0x00000070L 177 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L 178 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0x0000C000L 179 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 180 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 181 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK 0x00040000L 182 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK 0x00080000L 183 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK 0x00700000L 184 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L 185 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0xC0000000L 186 //HDP_MMHUB_CNTL 187 #define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0 188 #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1 189 #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2 190 #define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L 191 #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L 192 #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L 193 //HDP_EDC_CNT 194 #define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT 0x0 195 #define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT 0x2 196 #define HDP_EDC_CNT__MEM2_SED_COUNT__SHIFT 0x4 197 #define HDP_EDC_CNT__MEM3_SED_COUNT__SHIFT 0x6 198 #define HDP_EDC_CNT__MEM0_SED_COUNT_MASK 0x00000003L 199 #define HDP_EDC_CNT__MEM1_SED_COUNT_MASK 0x0000000CL 200 #define HDP_EDC_CNT__MEM2_SED_COUNT_MASK 0x00000030L 201 #define HDP_EDC_CNT__MEM3_SED_COUNT_MASK 0x000000C0L 202 //HDP_VERSION 203 #define HDP_VERSION__MINVER__SHIFT 0x0 204 #define HDP_VERSION__MAJVER__SHIFT 0x8 205 #define HDP_VERSION__REV__SHIFT 0x10 206 #define HDP_VERSION__MINVER_MASK 0x000000FFL 207 #define HDP_VERSION__MAJVER_MASK 0x0000FF00L 208 #define HDP_VERSION__REV_MASK 0x00FF0000L 209 //HDP_CLK_CNTL 210 #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0 211 #define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT 0x4 212 #define HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a 213 #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1b 214 #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c 215 #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d 216 #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e 217 #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f 218 #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL 219 #define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK 0x00000010L 220 #define HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L 221 #define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK 0x08000000L 222 #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L 223 #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L 224 #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L 225 #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L 226 //HDP_MEMIO_CNTL 227 #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 228 #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 229 #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 230 #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 231 #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 232 #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 233 #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe 234 #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf 235 #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 236 #define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 237 #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L 238 #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L 239 #define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL 240 #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L 241 #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L 242 #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L 243 #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L 244 #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L 245 #define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L 246 #define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L 247 //HDP_MEMIO_ADDR 248 #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 249 #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL 250 //HDP_MEMIO_STATUS 251 #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 252 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 253 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 254 #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 255 #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L 256 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L 257 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L 258 #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L 259 //HDP_MEMIO_WR_DATA 260 #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 261 #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL 262 //HDP_MEMIO_RD_DATA 263 #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 264 #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL 265 //HDP_XDP_DIRECT2HDP_FIRST 266 #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 267 #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL 268 //HDP_XDP_D2H_FLUSH 269 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 270 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 271 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 272 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb 273 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 274 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 275 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 276 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 277 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL 278 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L 279 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L 280 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L 281 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L 282 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L 283 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L 284 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L 285 //HDP_XDP_D2H_BAR_UPDATE 286 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 287 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 288 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 289 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL 290 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L 291 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L 292 //HDP_XDP_D2H_RSVD_3 293 #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 294 #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL 295 //HDP_XDP_D2H_RSVD_4 296 #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 297 #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL 298 //HDP_XDP_D2H_RSVD_5 299 #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 300 #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL 301 //HDP_XDP_D2H_RSVD_6 302 #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 303 #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL 304 //HDP_XDP_D2H_RSVD_7 305 #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 306 #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL 307 //HDP_XDP_D2H_RSVD_8 308 #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 309 #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL 310 //HDP_XDP_D2H_RSVD_9 311 #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 312 #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL 313 //HDP_XDP_D2H_RSVD_10 314 #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 315 #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL 316 //HDP_XDP_D2H_RSVD_11 317 #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 318 #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL 319 //HDP_XDP_D2H_RSVD_12 320 #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 321 #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL 322 //HDP_XDP_D2H_RSVD_13 323 #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 324 #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL 325 //HDP_XDP_D2H_RSVD_14 326 #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 327 #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL 328 //HDP_XDP_D2H_RSVD_15 329 #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 330 #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL 331 //HDP_XDP_D2H_RSVD_16 332 #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 333 #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL 334 //HDP_XDP_D2H_RSVD_17 335 #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 336 #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL 337 //HDP_XDP_D2H_RSVD_18 338 #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 339 #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL 340 //HDP_XDP_D2H_RSVD_19 341 #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 342 #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL 343 //HDP_XDP_D2H_RSVD_20 344 #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 345 #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL 346 //HDP_XDP_D2H_RSVD_21 347 #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 348 #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL 349 //HDP_XDP_D2H_RSVD_22 350 #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 351 #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL 352 //HDP_XDP_D2H_RSVD_23 353 #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 354 #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL 355 //HDP_XDP_D2H_RSVD_24 356 #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 357 #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL 358 //HDP_XDP_D2H_RSVD_25 359 #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 360 #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL 361 //HDP_XDP_D2H_RSVD_26 362 #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 363 #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL 364 //HDP_XDP_D2H_RSVD_27 365 #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 366 #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL 367 //HDP_XDP_D2H_RSVD_28 368 #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 369 #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL 370 //HDP_XDP_D2H_RSVD_29 371 #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 372 #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL 373 //HDP_XDP_D2H_RSVD_30 374 #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 375 #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL 376 //HDP_XDP_D2H_RSVD_31 377 #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 378 #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL 379 //HDP_XDP_D2H_RSVD_32 380 #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 381 #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL 382 //HDP_XDP_D2H_RSVD_33 383 #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 384 #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL 385 //HDP_XDP_D2H_RSVD_34 386 #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 387 #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL 388 //HDP_XDP_DIRECT2HDP_LAST 389 #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 390 #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL 391 //HDP_XDP_P2P_BAR_CFG 392 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 393 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 394 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL 395 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L 396 //HDP_XDP_P2P_MBX_OFFSET 397 #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 398 #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL 399 //HDP_XDP_P2P_MBX_ADDR0 400 #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 401 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3 402 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14 403 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18 404 #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L 405 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L 406 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L 407 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L 408 //HDP_XDP_P2P_MBX_ADDR1 409 #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 410 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3 411 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14 412 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18 413 #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L 414 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L 415 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L 416 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L 417 //HDP_XDP_P2P_MBX_ADDR2 418 #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 419 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3 420 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14 421 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18 422 #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L 423 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L 424 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L 425 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L 426 //HDP_XDP_P2P_MBX_ADDR3 427 #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 428 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3 429 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14 430 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18 431 #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L 432 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L 433 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L 434 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L 435 //HDP_XDP_P2P_MBX_ADDR4 436 #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 437 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3 438 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14 439 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18 440 #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L 441 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L 442 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L 443 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L 444 //HDP_XDP_P2P_MBX_ADDR5 445 #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 446 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3 447 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14 448 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18 449 #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L 450 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L 451 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L 452 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L 453 //HDP_XDP_P2P_MBX_ADDR6 454 #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 455 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3 456 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14 457 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18 458 #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L 459 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L 460 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L 461 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L 462 //HDP_XDP_HDP_MBX_MC_CFG 463 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0 464 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4 465 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8 466 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc 467 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd 468 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe 469 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL 470 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L 471 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L 472 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L 473 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L 474 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L 475 //HDP_XDP_HDP_MC_CFG 476 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3 477 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4 478 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8 479 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc 480 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd 481 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe 482 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L 483 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L 484 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L 485 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L 486 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L 487 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L 488 //HDP_XDP_HST_CFG 489 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 490 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 491 #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3 492 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4 493 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5 494 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L 495 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L 496 #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L 497 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L 498 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L 499 //HDP_XDP_HDP_IPH_CFG 500 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 501 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 502 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc 503 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd 504 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003FL 505 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000FC0L 506 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L 507 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L 508 //HDP_XDP_P2P_BAR0 509 #define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 510 #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 511 #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 512 #define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL 513 #define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L 514 #define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L 515 //HDP_XDP_P2P_BAR1 516 #define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 517 #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 518 #define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 519 #define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL 520 #define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L 521 #define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L 522 //HDP_XDP_P2P_BAR2 523 #define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 524 #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 525 #define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 526 #define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL 527 #define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L 528 #define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L 529 //HDP_XDP_P2P_BAR3 530 #define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 531 #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 532 #define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 533 #define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL 534 #define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L 535 #define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L 536 //HDP_XDP_P2P_BAR4 537 #define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 538 #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 539 #define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 540 #define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL 541 #define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L 542 #define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L 543 //HDP_XDP_P2P_BAR5 544 #define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 545 #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 546 #define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 547 #define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL 548 #define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L 549 #define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L 550 //HDP_XDP_P2P_BAR6 551 #define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 552 #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 553 #define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 554 #define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL 555 #define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L 556 #define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L 557 //HDP_XDP_P2P_BAR7 558 #define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 559 #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 560 #define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 561 #define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL 562 #define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L 563 #define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L 564 //HDP_XDP_FLUSH_ARMED_STS 565 #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 566 #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL 567 //HDP_XDP_FLUSH_CNTR0_STS 568 #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 569 #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL 570 //HDP_XDP_BUSY_STS 571 #define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 572 #define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x00FFFFFFL 573 //HDP_XDP_STICKY 574 #define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 575 #define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 576 #define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL 577 #define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L 578 //HDP_XDP_CHKN 579 #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 580 #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 581 #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 582 #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 583 #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL 584 #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L 585 #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L 586 #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L 587 //HDP_XDP_BARS_ADDR_39_36 588 #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 589 #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 590 #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 591 #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc 592 #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 593 #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 594 #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 595 #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c 596 #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL 597 #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L 598 #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L 599 #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L 600 #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L 601 #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L 602 #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L 603 #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L 604 //HDP_XDP_MC_VM_FB_LOCATION_BASE 605 #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 606 #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL 607 //HDP_XDP_GPU_IOV_VIOLATION_LOG 608 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 609 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 610 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 611 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 612 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 613 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 614 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 615 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 616 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 617 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L 618 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 619 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x01F00000L 620 //HDP_XDP_GPU_IOV_VIOLATION_LOG2 621 #define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 622 #define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL 623 //HDP_XDP_MMHUB_ERROR 624 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1 625 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2 626 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3 627 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5 628 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6 629 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7 630 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9 631 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa 632 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb 633 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd 634 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe 635 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf 636 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11 637 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12 638 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13 639 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15 640 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16 641 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17 642 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L 643 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L 644 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L 645 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L 646 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L 647 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L 648 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L 649 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L 650 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L 651 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L 652 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L 653 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L 654 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L 655 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L 656 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L 657 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L 658 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L 659 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L 660 661 #endif 662
Indexes created Sun Oct 12 22:09:51 GMT 2025