1 /* $NetBSD: hpcreg.h,v 1.21 2025/02/23 13:31:30 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Rafal K. Boni 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _ARCH_SGIMIPS_HPC_HPCREG_H_ 31 #define _ARCH_SGIMIPS_HPC_HPCREG_H_ 32 33 /* 34 * HPC locations are identical across all HPC-supported 35 * platforms. 36 */ 37 #define HPC_BASE_ADDRESS_0 0x1fb80000 /* Primary onboard */ 38 #define HPC_BASE_ADDRESS_1 0x1fb00000 39 #define HPC_BASE_ADDRESS_2 0x1f980000 40 #define HPC_BASE_ADDRESS_3 0x1f900000 /* NB: Never supported in h/w */ 41 42 /* 43 * HPC3 descriptor layout. 44 */ 45 struct hpc_dma_desc { 46 uint32_t hdd_bufptr; /* Physical address of buffer */ 47 uint32_t hdd_ctl; /* Control flags and byte count */ 48 uint32_t hdd_descptr; /* Physical address of next descr. */ 49 uint32_t hdd_pad; /* Pad out to quadword alignment */ 50 }; 51 52 /* 53 * The hdd_bufptr and hdd_ctl fields are swapped between HPC1 and 54 * HPC3. These fields are referenced by macro for readability. 55 */ 56 #define hpc1_hdd_ctl hdd_bufptr 57 #define hpc1_hdd_bufptr hdd_ctl 58 #define hpc3_hdd_ctl hdd_ctl 59 #define hpc3_hdd_bufptr hdd_bufptr 60 61 /* 62 * Control flags 63 */ 64 #define HPC3_HDD_CTL_EOCHAIN 0x80000000 /* End of descriptor chain */ 65 #define HPC3_HDD_CTL_EOPACKET 0x40000000 /* Ethernet: end of packet */ 66 #define HPC3_HDD_CTL_INTR 0x20000000 /* Interrupt when finished */ 67 #define HPC3_HDD_CTL_XMITDONE 0x00008000 /* Ethernet transmit done */ 68 #define HPC3_HDD_CTL_OWN 0x00004000 /* CPU owns this frame */ 69 70 #define HPC3_HDD_CTL_BYTECNT(x) ((x) & 0x3fff) /* Byte count: for ethernet 71 * rcv channel also doubles as 72 * length of packet received 73 */ 74 75 /* 76 * HPC memory map, as offsets from HPC base 77 * 78 * XXXrkb: should each section be used as a base and have the specific 79 * registers offset from there?? 80 * 81 * XXX: define register values as well as their offsets. 82 * 83 */ 84 #define HPC3_PBUS_DMAREGS 0x00000000 /* DMA registers for PBus */ 85 #define HPC3_PBUS_DMAREGS_SIZE 0x0000ffff /* channels 0 - 7 */ 86 87 #define HPC3_PBUS_CH0_BP 0x00000000 /* Chan 0 Buffer Ptr */ 88 #define HPC3_PBUS_CH0_DP 0x00000004 /* Chan 0 Descriptor Ptr */ 89 #define HPC3_PBUS_CH0_CTL 0x00001000 /* Chan 0 Control Register */ 90 91 #define HPC3_PBUS_CH1_BP 0x00002000 /* Chan 1 Buffer Ptr */ 92 #define HPC3_PBUS_CH1_DP 0x00002004 /* Chan 1 Descriptor Ptr */ 93 #define HPC3_PBUS_CH1_CTL 0x00003000 /* Chan 1 Control Register */ 94 95 #define HPC3_PBUS_CH2_BP 0x00004000 /* Chan 2 Buffer Ptr */ 96 #define HPC3_PBUS_CH2_DP 0x00004004 /* Chan 2 Descriptor Ptr */ 97 #define HPC3_PBUS_CH2_CTL 0x00005000 /* Chan 2 Control Register */ 98 99 #define HPC3_PBUS_CH3_BP 0x00006000 /* Chan 3 Buffer Ptr */ 100 #define HPC3_PBUS_CH3_DP 0x00006004 /* Chan 3 Descriptor Ptr */ 101 #define HPC3_PBUS_CH3_CTL 0x00007000 /* Chan 3 Control Register */ 102 103 #define HPC3_PBUS_CH4_BP 0x00008000 /* Chan 4 Buffer Ptr */ 104 #define HPC3_PBUS_CH4_DP 0x00008004 /* Chan 4 Descriptor Ptr */ 105 #define HPC3_PBUS_CH4_CTL 0x00009000 /* Chan 4 Control Register */ 106 107 #define HPC3_PBUS_CH5_BP 0x0000a000 /* Chan 5 Buffer Ptr */ 108 #define HPC3_PBUS_CH5_DP 0x0000a004 /* Chan 5 Descriptor Ptr */ 109 #define HPC3_PBUS_CH5_CTL 0x0000b000 /* Chan 5 Control Register */ 110 111 #define HPC3_PBUS_CH6_BP 0x0000c000 /* Chan 6 Buffer Ptr */ 112 #define HPC3_PBUS_CH6_DP 0x0000c004 /* Chan 6 Descriptor Ptr */ 113 #define HPC3_PBUS_CH6_CTL 0x0000d000 /* Chan 6 Control Register */ 114 115 #define HPC3_PBUS_CH7_BP 0x0000e000 /* Chan 7 Buffer Ptr */ 116 #define HPC3_PBUS_CH7_DP 0x0000e004 /* Chan 7 Descriptor Ptr */ 117 #define HPC3_PBUS_CH7_CTL 0x0000f000 /* Chan 7 Control Register */ 118 119 #define HPC3_SCSI0_REGS 0x00010000 /* SCSI channel 0 registers */ 120 #define HPC3_SCSI0_REGS_SIZE 0x00001fff 121 122 #define HPC3_SCSI0_CBP 0x00000000 /* Current buffer ptr */ 123 #define HPC3_SCSI0_NDBP 0x00000004 /* Next descriptor ptr */ 124 125 #define HPC3_SCSI0_BC 0x00001000 /* DMA byte count & flags */ 126 #define HPC3_SCSI0_CTL 0x00001004 /* DMA control flags */ 127 #define HPC3_SCSI0_GIO 0x00001008 /* GIO DMA FIFO pointer */ 128 #define HPC3_SCSI0_DEV 0x0000100c /* Device DMA FIFO pointer */ 129 #define HPC3_SCSI0_DMACFG 0x00001010 /* DMA configuration */ 130 #define HPC3_SCSI0_PIOCFG 0x00001014 /* PIO configuration */ 131 132 #define HPC3_SCSI1_REGS 0x00012000 /* SCSI channel 1 registers */ 133 #define HPC3_SCSI1_REGS_SIZE 0x00001fff 134 135 #define HPC3_SCSI1_CBP 0x00000000 /* Current buffer ptr */ 136 #define HPC3_SCSI1_NDBP 0x00000004 /* Next descriptor ptr */ 137 138 #define HPC3_SCSI1_BC 0x00001000 /* DMA byte count & flags */ 139 #define HPC3_SCSI1_CTL 0x00001004 /* DMA control flags */ 140 #define HPC3_SCSI1_GIO 0x00001008 /* GIO DMA FIFO pointer */ 141 #define HPC3_SCSI1_DEV 0x0000100c /* Device DMA FIFO pointer */ 142 #define HPC3_SCSI1_DMACFG 0x00001010 /* DMA configuration */ 143 #define HPC3_SCSI1_PIOCFG 0x00001014 /* PIO configuration */ 144 145 /* HPC3_SCSIx_CTL "SCSI control register" flags: */ 146 #define HPC3_SCSI_DMACTL_IRQ 0x01 /* IRQ asserted, dma done or parity */ 147 #define HPC3_SCSI_DMACTL_ENDIAN 0x02 /* DMA endian mode, 0=BE, 1=LE */ 148 #define HPC3_SCSI_DMACTL_DIR 0x04 /* DMA direction, 0=dev->mem, 1=mem->dev */ 149 #define HPC3_SCSI_DMACTL_FLUSH 0x08 /* Flush DMA FIFO's */ 150 #define HPC3_SCSI_DMACTL_ACTIVE 0x10 /* DMA channel is active */ 151 #define HPC3_SCSI_DMACTL_AMASK 0x20 /* DMA active inhibits PIO */ 152 #define HPC3_SCSI_DMACTL_RESET 0x40 /* Reset dma channel and ext. controller */ 153 #define HPC3_SCSI_DMACTL_PERR 0x80 /* Parity error: interface to controller */ 154 155 /* HPC_PBUS_CHx_CTL read: */ 156 #define HPC3_PBUS_DMACTL_IRQ 0x01 /* IRQ asserted, DMA done */ 157 #define HPC3_PBUS_DMACTL_ISACT 0x02 /* DMA channel is active */ 158 159 /* HPC_PBUS_CHx_CTL write: */ 160 #define HPC3_PBUS_DMACTL_ENDIAN 0x02 /* DMA endianness, 0=BE 1=LE */ 161 #define HPC3_PBUS_DMACTL_RECEIVE 0x04 /* DMA direction, 1=dev->mem, 0=mem->dev*/ 162 #define HPC3_PBUS_DMACTL_FLUSH 0x08 /* Flush DMA FIFO */ 163 #define HPC3_PBUS_DMACTL_ACT 0x10 /* Activate DMA channel */ 164 #define HPC3_PBUS_DMACTL_ACT_LD 0x20 /* Load enable for ACT */ 165 #define HPC3_PBUS_DMACTL_RT 0x40 /* Enable real time GIO service for DMA */ 166 #define HPC3_PBUS_DMACTL_HIGHWATER_SHIFT 8 167 #define HPC3_PBUS_DMACTL_FIFOBEG_SHIFT 16 168 #define HPC3_PBUS_DMACTL_FIFOEND_SHIFT 24 169 170 #define HPC3_ENET_REGS 0x00014000 /* Ethernet registers */ 171 #define HPC3_ENET_REGS_SIZE 0x00003fff 172 173 #define HPC3_ENETR_CBP 0x00000000 /* Recv: Current buffer ptr */ 174 #define HPC3_ENETR_NDBP 0x00000004 /* Recv: Next descriptor ptr */ 175 176 #define HPC3_ENETR_BC 0x00001000 /* Recv: DMA byte cnt/flags */ 177 #define HPC3_ENETR_CTL 0x00001004 /* Recv: DMA control flags */ 178 179 #define HPC3_ENETR_CTL_STAT_5_0 0x003f /* Seeq irq status: bits 0-5 */ 180 #define HPC3_ENETR_CTL_STAT_6 0x0040 /* Irq status: late_rxdc */ 181 #define HPC3_ENETR_CTL_STAT_7 0x0080 /* Irq status: old/new bit */ 182 #define HPC3_ENETR_CTL_LENDIAN 0x0100 /* DMA channel endian mode */ 183 #define HPC3_ENETR_CTL_ACTIVE 0x0200 /* DMA channel active? */ 184 #define HPC3_ENETR_CTL_ACTIVE_MSK 0x0400 /* DMA channel active? */ 185 #define HPC3_ENETR_CTL_RBO 0x0800 /* Recv buffer overflow */ 186 187 #define HPC3_ENETR_GIO 0x00001008 /* Recv: GIO DMA FIFO ptr */ 188 #define HPC3_ENETR_DEV 0x0000100c /* Recv: Device DMA FIFO ptr */ 189 #define HPC3_ENETR_RESET 0x00001014 /* Recv: Ethernet chip reset */ 190 191 #define HPC3_ENETR_RESET_CH 0x0001 /* Reset controller & chan */ 192 #define HPC3_ENETR_RESET_CLRINT 0x0002 /* Clear channel interrupt */ 193 #define HPC3_ENETR_RESET_LOOPBK 0x0004 /* External loopback enable */ 194 #define HPC3_ENETR_RESET_CLRRBO 0x0008 /* Clear RBO condition (??) */ 195 196 #define HPC3_ENETR_DMACFG 0x00001018 /* Recv: DMA configuration */ 197 198 #define HPC3_ENETR_DMACFG_D1(_x) (((_x) << 0) & 0x000f) /* D1 gio_clk cycles */ 199 #define HPC3_ENETR_DMACFG_D2(_x) (((_x) << 4) & 0x00f0) /* D2 gio_clk cycles */ 200 #define HPC3_ENETR_DMACFG_D3(_x) (((_x) << 8) & 0x0f00) /* D3 gio_clk cycles */ 201 #define HPC3_ENETR_DMACFG_WRCTL 0x01000 /* Enable IPG write */ 202 203 /* 204 * The following three bits work around bugs in the Seeq 8003; if you 205 * don't set them, the Seeq gets wonky pretty often. 206 */ 207 #define HPC3_ENETR_DMACFG_FIX_RXDC 0x02000 /* Clear EOP bits on RXDC */ 208 #define HPC3_ENETR_DMACFG_FIX_EOP 0x04000 /* Enable rxintr timeout */ 209 #define HPC3_ENETR_DMACFG_FIX_INTR 0x08000 /* Enable EOP timeout */ 210 #define HPC3_ENETR_DMACFG_TIMEOUT 0x30000 /* Timeout value for above two*/ 211 212 #define HPC3_ENETR_PIOCFG 0x0000101c /* Recv: PIO configuration */ 213 214 #define HPC3_ENETR_PIOCFG_P1(_x) (((_x) << 0) & 0x000f) /* P1 gio_clk cycles */ 215 #define HPC3_ENETR_PIOCFG_P2(_x) (((_x) << 4) & 0x00f0) /* P2 gio_clk cycles */ 216 #define HPC3_ENETR_PIOCFG_P3(_x) (((_x) << 8) & 0x0f00) /* P3 gio_clk cycles */ 217 218 #define HPC3_ENETX_CBP 0x00002000 /* Xmit: Current buffer ptr */ 219 #define HPC3_ENETX_NDBP 0x00002004 /* Xmit: Next descriptor ptr */ 220 221 #define HPC3_ENETX_BC 0x00003000 /* Xmit: DMA byte cnt/flags */ 222 #define HPC3_ENETX_CTL 0x00003004 /* Xmit: DMA control flags */ 223 224 #define HPC3_ENETX_CTL_STAT_5_0 0x003f /* Seeq irq status: bits 0-5 */ 225 #define HPC3_ENETX_CTL_STAT_6 0x0040 /* Irq status: late_rxdc */ 226 #define HPC3_ENETX_CTL_STAT_7 0x0080 /* Irq status: old/new bit */ 227 #define HPC3_ENETX_CTL_LENDIAN 0x0100 /* DMA channel endian mode */ 228 #define HPC3_ENETX_CTL_ACTIVE 0x0200 /* DMA channel active? */ 229 #define HPC3_ENETX_CTL_ACTIVE_MSK 0x0400 /* DMA channel active? */ 230 #define HPC3_ENETX_CTL_RBO 0x0800 /* Recv buffer overflow */ 231 232 #define HPC3_ENETX_GIO 0x00003008 /* Xmit: GIO DMA FIFO ptr */ 233 #define HPC3_ENETX_DEV 0x0000300c /* Xmit: Device DMA FIFO ptr */ 234 235 #define HPC3_PBUS_FIFO 0x00020000 /* PBus DMA FIFO */ 236 #define HPC3_PBUS_FIFO_SIZE 0x00007fff /* PBus DMA FIFO size */ 237 238 #define HPC3_SCSI0_FIFO 0x00028000 /* SCSI0 DMA FIFO */ 239 #define HPC3_SCSI0_FIFO_SIZE 0x00001fff /* SCSI0 DMA FIFO size */ 240 241 #define HPC3_SCSI1_FIFO 0x0002a000 /* SCSI1 DMA FIFO */ 242 #define HPC3_SCSI1_FIFO_SIZE 0x00001fff /* SCSI1 DMA FIFO size */ 243 244 #define HPC3_ENETR_FIFO 0x0002c000 /* Ether recv DMA FIFO */ 245 #define HPC3_ENETR_FIFO_SIZE 0x00001fff /* Ether recv DMA FIFO size */ 246 247 #define HPC3_ENETX_FIFO 0x0002e000 /* Ether xmit DMA FIFO */ 248 #define HPC3_ENETX_FIFO_SIZE 0x00001fff /* Ether xmit DMA FIFO size */ 249 250 /* 251 * HPCBUG: The interrupt status is split amongst two registers, and they're 252 * not even consecutive in the HPC address space. This is documented as a 253 * bug by SGI. 254 */ 255 #define HPC3_INTRSTAT_40 0x00030000 /* Interrupt stat, bits 4:0 */ 256 #define HPC3_INTRSTAT_95 0x0003000c /* Interrupt stat, bits 9:5 */ 257 258 #define HPC3_GIO_MISC 0x00030004 /* GIO64 misc register */ 259 260 #define HPC3_EEPROM_DATA 0x0003000b /* Serial EEPROM data reg. */ 261 /* (byte) */ 262 263 #define HPC3_GIO_BUSERR 0x00030010 /* GIO64 bus error intr stat */ 264 265 #define HPC3_SCSI0_DEVREGS 0x00044000 /* SCSI channel 0 chip regs */ 266 #define HPC3_SCSI0_DEVREGS_SIZE 0x000003ff /* Size of chip registers */ 267 268 #define HPC3_SCSI1_DEVREGS 0x0004c000 /* SCSI channel 1 chip regs */ 269 #define HPC3_SCSI1_DEVREGS_SIZE 0x000003ff /* Size of chip registers */ 270 271 #define HPC3_ENET_DEVREGS 0x00054000 /* Ethernet chip registers */ 272 #define HPC3_ENET_DEVREGS_SIZE 0x000004ff /* Size of chip registers */ 273 274 #define HPC3_PBUS_DEVREGS 0x00054000 /* PBus PIO chip registers */ 275 #define HPC3_PBUS_DEVREGS_SIZE 0x000003ff /* PBus PIO chip registers */ 276 277 #define HPC3_PBUS_CH0_DEVREGS 0x00058000 /* PBus ch. 0 chip registers */ 278 #define HPC3_PBUS_CH0_DEVREGS_SIZE 0x03ff 279 280 #define HPC3_PBUS_CH1_DEVREGS 0x00058400 /* PBus ch. 1 chip registers */ 281 #define HPC3_PBUS_CH1_DEVREGS_SIZE 0x03ff 282 283 #define HPC3_PBUS_CH2_DEVREGS 0x00058800 /* PBus ch. 2 chip registers */ 284 #define HPC3_PBUS_CH2_DEVREGS_SIZE 0x03ff 285 286 #define HPC3_PBUS_CH3_DEVREGS 0x00058c00 /* PBus ch. 3 chip registers */ 287 #define HPC3_PBUS_CH3_DEVREGS_SIZE 0x03ff 288 289 #define HPC3_PBUS_CH4_DEVREGS 0x00059000 /* PBus ch. 4 chip registers */ 290 #define HPC3_PBUS_CH4_DEVREGS_SIZE 0x03ff 291 292 #define HPC3_PBUS_CH5_DEVREGS 0x00059400 /* PBus ch. 5 chip registers */ 293 #define HPC3_PBUS_CH5_DEVREGS_SIZE 0x03ff 294 295 #define HPC3_PBUS_CH6_DEVREGS 0x00059800 /* PBus ch. 6 chip registers */ 296 #define HPC3_PBUS_CH6_DEVREGS_SIZE 0x03ff 297 298 #define HPC3_PBUS_CH7_DEVREGS 0x00059c00 /* PBus ch. 7 chip registers */ 299 #define HPC3_PBUS_CH7_DEVREGS_SIZE 0x03ff 300 301 #define HPC3_PBUS_CH8_DEVREGS 0x0005a000 /* PBus ch. 8 chip registers */ 302 #define HPC3_PBUS_CH8_DEVREGS_SIZE 0x03ff 303 304 #define HPC3_PBUS_CH9_DEVREGS 0x0005a400 /* PBus ch. 9 chip registers */ 305 #define HPC3_PBUS_CH9_DEVREGS_SIZE 0x03ff 306 307 #define HPC3_PBUS_CH8_DEVREGS_2 0x0005a800 /* PBus ch. 8 chip registers */ 308 #define HPC3_PBUS_CH8_DEVREGS_2_SIZE 0x03ff 309 310 #define HPC3_PBUS_CH9_DEVREGS_2 0x0005ac00 /* PBus ch. 9 chip registers */ 311 #define HPC3_PBUS_CH9_DEVREGS_2_SIZE 0x03ff 312 313 #define HPC3_PBUS_CH8_DEVREGS_3 0x0005b000 /* PBus ch. 8 chip registers */ 314 #define HPC3_PBUS_CH8_DEVREGS_3_SIZE 0x03ff 315 316 #define HPC3_PBUS_CH9_DEVREGS_3 0x0005b400 /* PBus ch. 9 chip registers */ 317 #define HPC3_PBUS_CH9_DEVREGS_3_SIZE 0x03ff 318 319 #define HPC3_PBUS_CH8_DEVREGS_4 0x0005b800 /* PBus ch. 8 chip registers */ 320 #define HPC3_PBUS_CH8_DEVREGS_4_SIZE 0x03ff 321 322 #define HPC3_PBUS_CH9_DEVREGS_4 0x0005bc00 /* PBus ch. 9 chip registers */ 323 #define HPC3_PBUS_CH9_DEVREGS_4_SIZE 0x03ff 324 325 #define HPC3_PBUS_CFGDMA_REGS 0x0005c000 /* PBus DMA config registers */ 326 #define HPC3_PBUS_CFGDMA_REGS_SIZE 0x0fff 327 328 #define HPC3_PBUS_CH0_CFGDMA 0x0005c000 /* PBus Ch. 0 DMA config */ 329 #define HPC3_PBUS_CH0_CFGDMA_SIZE 0x01ff 330 331 #define HPC3_PBUS_CH1_CFGDMA 0x0005c200 /* PBus Ch. 1 DMA config */ 332 #define HPC3_PBUS_CH1_CFGDMA_SIZE 0x01ff 333 334 #define HPC3_PBUS_CH2_CFGDMA 0x0005c400 /* PBus Ch. 2 DMA config */ 335 #define HPC3_PBUS_CH2_CFGDMA_SIZE 0x01ff 336 337 #define HPC3_PBUS_CH3_CFGDMA 0x0005c600 /* PBus Ch. 3 DMA config */ 338 #define HPC3_PBUS_CH3_CFGDMA_SIZE 0x01ff 339 340 #define HPC3_PBUS_CH4_CFGDMA 0x0005c800 /* PBus Ch. 4 DMA config */ 341 #define HPC3_PBUS_CH4_CFGDMA_SIZE 0x01ff 342 343 #define HPC3_PBUS_CH5_CFGDMA 0x0005ca00 /* PBus Ch. 5 DMA config */ 344 #define HPC3_PBUS_CH5_CFGDMA_SIZE 0x01ff 345 346 #define HPC3_PBUS_CH6_CFGDMA 0x0005cc00 /* PBus Ch. 6 DMA config */ 347 #define HPC3_PBUS_CH6_CFGDMA_SIZE 0x01ff 348 349 #define HPC3_PBUS_CH7_CFGDMA 0x0005ce00 /* PBus Ch. 7 DMA config */ 350 #define HPC3_PBUS_CH7_CFGDMA_SIZE 0x01ff 351 352 #define HPC3_PBUS_CFGPIO_REGS 0x0005d000 /* PBus PIO config registers */ 353 #define HPC3_PBUS_CFGPIO_REGS_SIZE 0x0fff 354 355 #define HPC3_PBUS_CH0_CFGPIO 0x0005d000 /* PBus Ch. 0 PIO config */ 356 #define HPC3_PBUS_CH1_CFGPIO 0x0005d100 /* PBus Ch. 1 PIO config */ 357 #define HPC3_PBUS_CH2_CFGPIO 0x0005d200 /* PBus Ch. 2 PIO config */ 358 #define HPC3_PBUS_CH3_CFGPIO 0x0005d300 /* PBus Ch. 3 PIO config */ 359 #define HPC3_PBUS_CH4_CFGPIO 0x0005d400 /* PBus Ch. 4 PIO config */ 360 #define HPC3_PBUS_CH5_CFGPIO 0x0005d500 /* PBus Ch. 5 PIO config */ 361 #define HPC3_PBUS_CH6_CFGPIO 0x0005d600 /* PBus Ch. 6 PIO config */ 362 #define HPC3_PBUS_CH7_CFGPIO 0x0005d700 /* PBus Ch. 7 PIO config */ 363 #define HPC3_PBUS_CH8_CFGPIO 0x0005d800 /* PBus Ch. 8 PIO config */ 364 #define HPC3_PBUS_CH9_CFGPIO 0x0005d900 /* PBus Ch. 9 PIO config */ 365 #define HPC3_PBUS_CH8_CFGPIO_2 0x0005da00 /* PBus Ch. 8 PIO config */ 366 #define HPC3_PBUS_CH9_CFGPIO_2 0x0005db00 /* PBus Ch. 9 PIO config */ 367 #define HPC3_PBUS_CH8_CFGPIO_3 0x0005dc00 /* PBus Ch. 8 PIO config */ 368 #define HPC3_PBUS_CH9_CFGPIO_3 0x0005dd00 /* PBus Ch. 9 PIO config */ 369 #define HPC3_PBUS_CH8_CFGPIO_4 0x0005de00 /* PBus Ch. 8 PIO config */ 370 #define HPC3_PBUS_CH9_CFGPIO_4 0x0005df00 /* PBus Ch. 9 PIO config */ 371 372 #define HPC3_PBUS_PROM_WE 0x0005e000 /* PBus boot-prom write 373 * enable register 374 */ 375 376 #define HPC3_PBUS_PROM_SWAP 0x0005e800 /* PBus boot-prom chip-select 377 * swap register 378 */ 379 380 #define HPC3_PBUS_GEN_OUT 0x0005f000 /* PBus general-purpose output 381 * register 382 */ 383 384 #define HPC3_PBUS_BBRAM 0x00060000 /* PBus battery-backed RAM 385 * external registers 386 */ 387 388 /* HPC1/HPC1.5 differs from HPC3 in several details. */ 389 390 #define HPC1_HDD_CTL_EOCHAIN 0x80000000 /* End of descriptor chain */ 391 #define HPC1_HDD_CTL_EOPACKET 0x80000000 /* Ethernet: end of packet */ 392 #define HPC1_HDD_CTL_INTR 0x00008000 /* Interrupt when finished */ 393 #define HPC1_HDD_CTL_OWN 0x40000000 /* CPU owns this frame */ 394 #define HPC1_HDD_CTL_BYTECNT(x) ((x) & 0x1fff) /* Byte count: for ethernet */ 395 #define HPC1_BIGENDIAN 0x000000c0 /* Endianness:5 revision:2 */ 396 #define HPC1_REVSHIFT 0x00000006 /* Revision rshft */ 397 #define HPC1_REVMASK 0x00000003 /* Revision mask */ 398 #define HPC1_REV15 0x00000001 /* HPC Revision 1.5 */ 399 #define HPC1_SCSI0_REGS 0x00000088 400 #define HPC1_SCSI0_REGS_SIZE 0x00000018 401 #define HPC1_SCSI0_CBP 0x00000004 /* Current buffer ptr */ 402 #define HPC1_SCSI0_NDBP 0x00000008 /* Next descriptor ptr */ 403 #define HPC1_SCSI0_BC 0x00000000 /* DMA byte count & flags */ 404 #define HPC1_SCSI0_CTL 0x0000000c /* DMA control flags */ 405 #define HPC1_SCSI0_DEV 0x00000014 /* Device DMA FIFO pointer */ 406 #define HPC1_SCSI0_DMACFG 0x00000010 /* DMA configuration */ 407 #define HPC1_SCSI0_GIO 0x00001008 /* GIO DMA FIFO pointer */ 408 #define HPC1_SCSI0_PIOCFG 0x00001014 /* PIO configuration */ 409 #define HPC1_SCSI_DMACTL_RESET 0x01 /* Reset dma channel and ext. controller */ 410 #define HPC1_SCSI_DMACTL_FLUSH 0x02 /* Flush DMA FIFO's */ 411 #define HPC1_SCSI_DMACTL_DIR 0x10 /* DMA direction: 1=dev->mem, 0=mem->dev */ 412 #define HPC1_SCSI_DMACTL_ACTIVE 0x80 /* DMA channel is active */ 413 #define HPC1_ENET_REGS 0x00000000 /* Ethernet registers */ 414 #define HPC1_ENET_REGS_SIZE 0x00000100 415 #define HPC1_ENET_INTDELAY 0x0000002c /* Interrupt Delay Count */ 416 #define HPC1_ENET_INTDELAY_OFF 0x01000000 /* Disable Interrupt Delay */ 417 #define HPC1_ENETR_CBP 0x00000054 /* Recv: Current buffer ptr */ 418 #define HPC1_ENETR_NDBP 0x00000050 /* Recv: Next descriptor ptr */ 419 #define HPC1_ENETR_BC 0x00000048 /* Recv: DMA byte cnt/flags */ 420 #define HPC1_ENETR_CTL 0x00000038 /* Recv: DMA control flags */ 421 #define HPC1_ENETR_CTL_ACTIVE 0x00004000 /* DMA channel active? */ 422 #define HPC1_ENETR_RESET 0x0000003c /* Recv: Ethernet chip reset */ 423 #define HPC1_ENETR_RESET_CH 0x0001 /* Reset controller & chan */ 424 #define HPC1_ENETR_RESET_CLRINT 0x0002 /* Clear channel interrupt */ 425 #define HPC1_ENETR_RESET_LOOPBK 0x0004 /* External loopback enable */ 426 #define HPC1_ENETR_RESET_CLRRBO 0x0008 /* Clear RBO condition (??) */ 427 #define HPC1_ENETX_CBP 0x00000020 /* Xmit: Current buffer ptr */ 428 #define HPC1_ENETX_NDBP 0x00000010 /* Xmit: Next descriptor ptr */ 429 #define HPC1_ENETX_CFXBP 0x00000024 /* Xmit: Current first buf */ 430 #define HPC1_ENETX_PFXBP 0x00000028 /* Xmit: Prev. first buf */ 431 #define HPC1_ENETX_BC 0x00000014 /* Xmit: DMA byte cnt/flags */ 432 #define HPC1_ENETX_CTL 0x00000034 /* Xmit: DMA control flags */ 433 #define HPC1_ENETX_CTL_ACTIVE 0x00400000 434 #define HPC1_ENETR_FIFO 0x0002c000 /* Ether recv DMA FIFO */ 435 #define HPC1_ENETR_FIFO_SIZE 0x00001fff /* Ether recv DMA FIFO size */ 436 #define HPC1_ENETX_FIFO 0x0002e000 /* Ether xmit DMA FIFO */ 437 #define HPC1_ENETX_FIFO_SIZE 0x00001fff /* Ether xmit DMA FIFO size */ 438 #define HPC1_SCSI0_DEVREGS 0x0000011f 439 #define HPC1_SCSI0_DEVREGS_SIZE 0x00000008 440 #define HPC1_ENET_DEVREGS 0x00000100 /* Ethernet chip registers */ 441 #define HPC1_ENET_DEVREGS_SIZE 0x00000020 /* Size of chip registers */ 442 #define HPC1_PBUS_BBRAM 0x00000e00 /* PBus battery-backed RAM */ 443 #define HPC1_LPT_REGS 0x000000a8 /* LPT HPC Registers */ 444 #define HPC1_LPT_REGS_SIZE 0x00000018 445 #define HPC1_LPT_BC 0x00000000 /* Byte Count */ 446 #define HPC1_LPT_CBP 0x00000004 /* Current Buffer Ptr */ 447 #define HPC1_LPT_NDBP 0x00000008 /* Next Buffer Ptr */ 448 #define HPC1_LPT_CTL 0x0000000c /* DMA Control Flags */ 449 #define HPC1_LPT_DEV 0x00000010 /* DMA Fifo Ptr */ 450 #define HPC1_LPT_DMACFG 0x00000014 /* DMA Configuration */ 451 #define HPC1_LPT_DEVREGS 0x00000132 /* Ext. Parallel Registers */ 452 #define HPC1_LPT_DEVREGS_SIZE 0x00000001 /* Size of External Registers */ 453 454 /* AUX regs on the primary HPC */ 455 #define HPC1_AUX_REGS 0x000001bf /* EEPROM/LED Control (byte) */ 456 #define HPC1_AUX_CONSLED 0x01 /* Console LED */ 457 458 #endif /* _ARCH_SGIMIPS_HPC_HPCREG_H_ */ 459
Indexes created Sun Sep 21 15:09:59 GMT 2025