1 /* $NetBSD: dcn21_hubbub.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 #ifndef DAL_DC_DCN21_DCN21_HUBBUB_H_ 28 #define DAL_DC_DCN21_DCN21_HUBBUB_H_ 29 30 #include "dcn20/dcn20_hubbub.h" 31 32 #define HUBBUB_HVM_REG_LIST() \ 33 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ 34 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ 35 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ 36 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ 37 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ 38 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ 39 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ 40 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ 41 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ 42 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\ 43 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\ 44 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\ 45 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 46 SR(DCHVM_CTRL0), \ 47 SR(DCHVM_MEM_CTRL), \ 48 SR(DCHVM_CLK_CTRL), \ 49 SR(DCHVM_RIOMMU_CTRL0), \ 50 SR(DCHVM_RIOMMU_STAT0) 51 52 #define HUBBUB_REG_LIST_DCN21()\ 53 HUBBUB_REG_LIST_DCN20_COMMON(), \ 54 HUBBUB_SR_WATERMARK_REG_LIST(), \ 55 HUBBUB_HVM_REG_LIST() 56 57 #define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \ 58 HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh), \ 59 HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \ 60 HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \ 61 HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \ 62 HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \ 63 HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \ 64 HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \ 65 HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \ 66 HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \ 67 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, mask_sh), \ 68 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, mask_sh), \ 69 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, mask_sh), \ 70 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, mask_sh), \ 71 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \ 72 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \ 73 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \ 74 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \ 75 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \ 76 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \ 77 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \ 78 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D, mask_sh), \ 79 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \ 80 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \ 81 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \ 82 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh), \ 83 HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh), \ 84 HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \ 85 HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh), \ 86 HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh), \ 87 HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh), \ 88 HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh), \ 89 HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh), \ 90 HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh), \ 91 HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh), \ 92 HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh), \ 93 HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh), \ 94 HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh), \ 95 HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh), \ 96 HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh), \ 97 HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh), \ 98 HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \ 99 HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \ 100 HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \ 101 HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh) 102 103 #define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\ 104 HUBBUB_MASK_SH_LIST_HVM(mask_sh), \ 105 HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ 106 HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ 107 HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 108 HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \ 109 HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \ 110 HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ 111 HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ 112 HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ 113 HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh) 114 115 void dcn21_dchvm_init(struct hubbub *hubbub); 116 int hubbub21_init_dchub(struct hubbub *hubbub, 117 struct dcn_hubbub_phys_addr_config *pa_config); 118 void hubbub21_program_watermarks( 119 struct hubbub *hubbub, 120 struct dcn_watermark_set *watermarks, 121 unsigned int refclk_mhz, 122 bool safe_to_lower); 123 void hubbub21_program_urgent_watermarks( 124 struct hubbub *hubbub, 125 struct dcn_watermark_set *watermarks, 126 unsigned int refclk_mhz, 127 bool safe_to_lower); 128 void hubbub21_program_stutter_watermarks( 129 struct hubbub *hubbub, 130 struct dcn_watermark_set *watermarks, 131 unsigned int refclk_mhz, 132 bool safe_to_lower); 133 void hubbub21_program_pstate_watermarks( 134 struct hubbub *hubbub, 135 struct dcn_watermark_set *watermarks, 136 unsigned int refclk_mhz, 137 bool safe_to_lower); 138 139 void hubbub21_wm_read_state(struct hubbub *hubbub, 140 struct dcn_hubbub_wm *wm); 141 142 void hubbub21_construct(struct dcn20_hubbub *hubbub, 143 struct dc_context *ctx, 144 const struct dcn_hubbub_registers *hubbub_regs, 145 const struct dcn_hubbub_shift *hubbub_shift, 146 const struct dcn_hubbub_mask *hubbub_mask); 147 148 #endif /* DAL_DC_DCN21_DCN21_HUBBUB_H_ */ 149
Indexes created Wed Oct 01 19:09:53 GMT 2025