1 /* $NetBSD: dcn20_hubp.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-17 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DC_MEM_INPUT_DCN20_H__ 29 #define __DC_MEM_INPUT_DCN20_H__ 30 31 #include "../dcn10/dcn10_hubp.h" 32 33 #define TO_DCN20_HUBP(hubp)\ 34 container_of(hubp, struct dcn20_hubp, base) 35 36 #define HUBP_REG_LIST_DCN2_COMMON(id)\ 37 HUBP_REG_LIST_DCN(id),\ 38 HUBP_REG_LIST_DCN_VM(id),\ 39 SRI(PREFETCH_SETTINGS, HUBPREQ, id),\ 40 SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\ 41 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\ 42 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\ 43 SRI(CURSOR_SETTINGS, HUBPREQ, id), \ 44 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \ 45 SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \ 46 SRI(CURSOR_SIZE, CURSOR0_, id), \ 47 SRI(CURSOR_CONTROL, CURSOR0_, id), \ 48 SRI(CURSOR_POSITION, CURSOR0_, id), \ 49 SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \ 50 SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \ 51 SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \ 52 SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \ 53 SRI(DMDATA_CNTL, CURSOR0_, id), \ 54 SRI(DMDATA_SW_CNTL, CURSOR0_, id), \ 55 SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \ 56 SRI(DMDATA_SW_DATA, CURSOR0_, id), \ 57 SRI(DMDATA_STATUS, CURSOR0_, id),\ 58 SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\ 59 SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\ 60 SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\ 61 SRI(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),\ 62 SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\ 63 SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \ 64 SRI(VMID_SETTINGS_0, HUBPREQ, id) 65 66 #define HUBP_REG_LIST_DCN20(id)\ 67 HUBP_REG_LIST_DCN2_COMMON(id),\ 68 SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 69 SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB) 70 71 #define HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh)\ 72 HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ 73 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ 74 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ 75 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ 76 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ 77 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ 78 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ 79 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ 80 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ 81 HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ 82 HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ 83 HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ 84 HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ 85 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ 86 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ 87 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ 88 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ 89 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ 90 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ 91 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ 92 HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ 93 HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ 94 HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ 95 HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ 96 HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ 97 HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ 98 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ 99 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ 100 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ 101 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ 102 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ 103 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ 104 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ 105 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ 106 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ 107 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ 108 HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\ 109 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ 110 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ 111 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ 112 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ 113 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ 114 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ 115 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ 116 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ 117 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ 118 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh) 119 120 /*DCN2.x and DCN1.x*/ 121 #define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\ 122 HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh),\ 123 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ 124 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ 125 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) 126 127 /*DCN2.0 specific*/ 128 #define HUBP_MASK_SH_LIST_DCN20(mask_sh)\ 129 HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\ 130 HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ 131 HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ 132 HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh) 133 134 /*DCN2.x */ 135 #define DCN2_HUBP_REG_COMMON_VARIABLE_LIST \ 136 HUBP_COMMON_REG_VARIABLE_LIST; \ 137 uint32_t DMDATA_ADDRESS_HIGH; \ 138 uint32_t DMDATA_ADDRESS_LOW; \ 139 uint32_t DMDATA_CNTL; \ 140 uint32_t DMDATA_SW_CNTL; \ 141 uint32_t DMDATA_QOS_CNTL; \ 142 uint32_t DMDATA_SW_DATA; \ 143 uint32_t DMDATA_STATUS;\ 144 uint32_t DCSURF_FLIP_CONTROL2;\ 145 uint32_t FLIP_PARAMETERS_0;\ 146 uint32_t FLIP_PARAMETERS_1;\ 147 uint32_t FLIP_PARAMETERS_2;\ 148 uint32_t DCN_CUR1_TTU_CNTL0;\ 149 uint32_t DCN_CUR1_TTU_CNTL1;\ 150 uint32_t VMID_SETTINGS_0 151 152 153 #define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \ 154 DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \ 155 uint32_t FLIP_PARAMETERS_3;\ 156 uint32_t FLIP_PARAMETERS_4;\ 157 uint32_t FLIP_PARAMETERS_5;\ 158 uint32_t FLIP_PARAMETERS_6;\ 159 uint32_t VBLANK_PARAMETERS_5;\ 160 uint32_t VBLANK_PARAMETERS_6 161 162 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ 163 DCN_HUBP_REG_FIELD_BASE_LIST(type); \ 164 type DMDATA_ADDRESS_HIGH;\ 165 type DMDATA_MODE;\ 166 type DMDATA_UPDATED;\ 167 type DMDATA_REPEAT;\ 168 type DMDATA_SIZE;\ 169 type DMDATA_SW_UPDATED;\ 170 type DMDATA_SW_REPEAT;\ 171 type DMDATA_SW_SIZE;\ 172 type DMDATA_QOS_MODE;\ 173 type DMDATA_QOS_LEVEL;\ 174 type DMDATA_DL_DELTA;\ 175 type DMDATA_DONE;\ 176 type DST_Y_PER_VM_FLIP;\ 177 type DST_Y_PER_ROW_FLIP;\ 178 type REFCYC_PER_PTE_GROUP_FLIP_L;\ 179 type REFCYC_PER_META_CHUNK_FLIP_L;\ 180 type HUBP_VREADY_AT_OR_AFTER_VSYNC;\ 181 type HUBP_DISABLE_STOP_DATA_DURING_VM;\ 182 type HUBPREQ_MASTER_UPDATE_LOCK_STATUS;\ 183 type SURFACE_GSL_ENABLE;\ 184 type SURFACE_TRIPLE_BUFFER_ENABLE;\ 185 type VMID 186 187 #define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \ 188 DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\ 189 type REFCYC_PER_VM_GROUP_FLIP;\ 190 type REFCYC_PER_VM_REQ_FLIP;\ 191 type REFCYC_PER_VM_GROUP_VBLANK;\ 192 type REFCYC_PER_VM_REQ_VBLANK;\ 193 type REFCYC_PER_PTE_GROUP_FLIP_C; \ 194 type REFCYC_PER_META_CHUNK_FLIP_C; \ 195 type VM_GROUP_SIZE 196 197 198 struct dcn_hubp2_registers { 199 DCN21_HUBP_REG_COMMON_VARIABLE_LIST; 200 }; 201 202 struct dcn_hubp2_shift { 203 DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); 204 }; 205 206 struct dcn_hubp2_mask { 207 DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); 208 }; 209 210 struct dcn20_hubp { 211 struct hubp base; 212 struct dcn_hubp_state state; 213 const struct dcn_hubp2_registers *hubp_regs; 214 const struct dcn_hubp2_shift *hubp_shift; 215 const struct dcn_hubp2_mask *hubp_mask; 216 }; 217 218 bool hubp2_construct( 219 struct dcn20_hubp *hubp2, 220 struct dc_context *ctx, 221 uint32_t inst, 222 const struct dcn_hubp2_registers *hubp_regs, 223 const struct dcn_hubp2_shift *hubp_shift, 224 const struct dcn_hubp2_mask *hubp_mask); 225 226 void hubp2_setup_interdependent( 227 struct hubp *hubp, 228 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 229 struct _vcs_dpi_display_ttu_regs_st *ttu_attr); 230 231 void hubp2_vready_at_or_After_vsync(struct hubp *hubp, 232 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); 233 234 void hubp2_cursor_set_attributes( 235 struct hubp *hubp, 236 const struct dc_cursor_attributes *attr); 237 238 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, 239 struct vm_system_aperture_param *apt); 240 241 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( 242 unsigned int cursor_width, 243 enum dc_cursor_color_format cursor_mode); 244 245 void hubp2_dmdata_set_attributes( 246 struct hubp *hubp, 247 const struct dc_dmdata_attributes *attr); 248 249 void hubp2_dmdata_load( 250 struct hubp *hubp, 251 uint32_t dmdata_sw_size, 252 const uint32_t *dmdata_sw_data); 253 254 bool hubp2_dmdata_status_done(struct hubp *hubp); 255 256 void hubp2_enable_triplebuffer( 257 struct hubp *hubp, 258 bool enable); 259 260 bool hubp2_is_triplebuffer_enabled( 261 struct hubp *hubp); 262 263 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable); 264 265 void hubp2_program_deadline( 266 struct hubp *hubp, 267 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 268 struct _vcs_dpi_display_ttu_regs_st *ttu_attr); 269 270 bool hubp2_program_surface_flip_and_addr( 271 struct hubp *hubp, 272 const struct dc_plane_address *address, 273 bool flip_immediate); 274 275 void hubp2_dcc_control(struct hubp *hubp, bool enable, 276 enum hubp_ind_block_size independent_64b_blks); 277 278 void hubp2_program_size( 279 struct hubp *hubp, 280 enum surface_pixel_format format, 281 const struct plane_size *plane_size, 282 struct dc_plane_dcc_param *dcc); 283 284 void hubp2_program_rotation( 285 struct hubp *hubp, 286 enum dc_rotation_angle rotation, 287 bool horizontal_mirror); 288 289 void hubp2_program_pixel_format( 290 struct hubp *hubp, 291 enum surface_pixel_format format); 292 293 void hubp2_program_surface_config( 294 struct hubp *hubp, 295 enum surface_pixel_format format, 296 union dc_tiling_info *tiling_info, 297 struct plane_size *plane_size, 298 enum dc_rotation_angle rotation, 299 struct dc_plane_dcc_param *dcc, 300 bool horizontal_mirror, 301 unsigned int compat_level); 302 303 bool hubp2_is_flip_pending(struct hubp *hubp); 304 305 void hubp2_set_blank(struct hubp *hubp, bool blank); 306 307 void hubp2_cursor_set_position( 308 struct hubp *hubp, 309 const struct dc_cursor_position *pos, 310 const struct dc_cursor_mi_param *param); 311 312 void hubp2_clk_cntl(struct hubp *hubp, bool enable); 313 314 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst); 315 316 void hubp2_clear_underflow(struct hubp *hubp); 317 318 void hubp2_read_state_common(struct hubp *hubp); 319 320 void hubp2_read_state(struct hubp *hubp); 321 322 #endif /* __DC_MEM_INPUT_DCN20_H__ */ 323 324 325
Indexes created Mon Sep 29 03:10:08 GMT 2025