1 /* $NetBSD: inbmphyreg.h,v 1.20 2020/09/16 15:04:01 msaitoh Exp $ */ 2 /******************************************************************************* 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 *******************************************************************************/ 32 33 /* 34 * Copied from the Intel code, and then modified to match NetBSD 35 * style for MII registers more. 36 */ 37 38 #ifndef _DEV_MII_INBMPHYREG_H_ 39 #define _DEV_MII_INBMPHYREG_H_ 40 41 /* Bits... 42 * 31-16: register offset (high) 43 * 15-5: page 44 * 4-0: register offset (low) 45 */ 46 #define BME1000_PAGE_SHIFT 5 47 #define BM_PHY_UPPER_SHIFT 21 48 #define BME1000_REG(page, reg) \ 49 (((reg) & MII_ADDRMASK) | \ 50 (((page) & 0xffff) << BME1000_PAGE_SHIFT) | \ 51 (((reg) & ~MII_ADDRMASK) << (BM_PHY_UPPER_SHIFT - BME1000_PAGE_SHIFT))) 52 53 #define BME1000_MAX_MULTI_PAGE_REG 0xf /* Registers equal on all pages */ 54 55 #define BM_PHY_REG_PAGE(offset) \ 56 ((uint16_t)(((offset) >> BME1000_PAGE_SHIFT) & 0xffff)) 57 #define BM_PHY_REG_NUM(offset) \ 58 ((uint16_t)((offset) & MII_ADDRMASK) \ 59 | (((offset) >> (BM_PHY_UPPER_SHIFT - BME1000_PAGE_SHIFT)) & ~MII_ADDRMASK)) 60 61 /* BME1000 Specific Registers */ 62 #define BME1000_PHY_SPEC_CTRL BME1000_REG(0, 16) /* PHY Specific Control */ 63 #define BME1000_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */ 64 #define BME1000_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */ 65 #define BME1000_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */ 66 #define BME1000_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */ 67 #define BME1000_PSCR_CROSSOVER_MODE_MASK 0x0060 68 #define BME1000_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */ 69 #define BME1000_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */ 70 #define BME1000_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */ 71 #define BME1000_PSCR_ENABLE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */ 72 #define BME1000_PSCR_ENERGY_DETECT_MASK 0x0300 73 #define BME1000_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */ 74 #define BME1000_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */ 75 #define BME1000_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */ 76 #define BME1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */ 77 #define BME1000_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */ 78 #define BME1000_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000 79 #define BME1000_PSCR_DOWNSHIFT_COUNTER_SHIFT 12 80 81 /* Extended Management Interface (EMI) Registers */ 82 #define I82579_EMI_ADDR 0x10 83 #define I82579_EMI_DATA 0x11 84 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ 85 #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ 86 #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ 87 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ 88 #define I82579_EEE_ADVERTISEMENT 0x040e /* IEEE MMD Register 7.60 */ 89 #define I82579_EEE_LP_ABILITY 0x040f /* IEEE MMD Register 7.61 */ 90 #define I82579_EEE_PCS_STATUS 0x182e 91 #define I82579_RX_CONFIG 0x3412 /* Receive configuration */ 92 #define I82579_LPI_PLL_SHUT 0x4412 93 #define I82579_LPI_PLL_SHUT_100 __BIT(2) /* 100M LPI PLL Shut Enable */ 94 #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ 95 #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ 96 #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ 97 #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ 98 #define I217_RX_CONFIG 0xb20c /* Receive configuration */ 99 100 /* BM PHY Copper Specific Status */ 101 #define BM_CS_STATUS BME1000_REG(0, 17) 102 #define BM_CS_STATUS_LINK_UP 0x0400 103 #define BM_CS_STATUS_RESOLVED 0x0800 104 #define BM_CS_STATUS_SPEED_MASK 0xC000 105 #define BM_CS_STATUS_SPEED_1000 0x8000 106 107 #define BME1000_PHY_PAGE_SELECT BME1000_REG(0, 22) /* Page Select */ 108 109 #define BME1000_BIAS_SETTING 29 110 #define BME1000_BIAS_SETTING2 30 111 112 #define I82578_ADDR_REG 29 113 #define I82577_ADDR_REG 16 114 #define I82577_CFG_REG 22 115 116 #define HV_INTC_FC_PAGE_START 768 117 #define BM_PORT_CTRL_PAGE 769 118 119 #define HV_OEM_BITS BME1000_REG(0, 25) 120 #define HV_OEM_BITS_LPLU (1 << 2) 121 #define HV_OEM_BITS_A1KDIS (1 << 6) 122 #define HV_OEM_BITS_ANEGNOW (1 << 10) 123 124 /* 82577 Mobile Phy Status Register */ 125 #define HV_M_STATUS BME1000_REG(0, 26) 126 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 127 #define HV_M_STATUS_SPEED_MASK 0x0300 128 #define HV_M_STATUS_SPEED_1000 0x0200 129 #define HV_M_STATUS_SPEED_100 0x0100 130 #define HV_M_STATUS_LINK_UP 0x0040 131 132 #define HV_LED_CONFIG BME1000_REG(0, 30) 133 134 #define HV_KMRN_MODE_CTRL BME1000_REG(BM_PORT_CTRL_PAGE, 16) 135 #define HV_KMRN_MDIO_SLOW 0x0400 136 137 #define BM_PORT_GEN_CFG BME1000_REG(BM_PORT_CTRL_PAGE, 17) 138 139 #define I82579_DFT_CTRL BME1000_REG(BM_PORT_CTRL_PAGE, 20) 140 141 #define CV_SMB_CTRL BME1000_REG(BM_PORT_CTRL_PAGE, 23) 142 #define CV_SMB_CTRL_FORCE_SMBUS __BIT(0) 143 144 #define BM_RATE_ADAPTATION_CTRL BME1000_REG(BM_PORT_CTRL_PAGE, 25) 145 #define BM_RATE_ADAPTATION_CTRL_RX_RXDV_PRE __BIT(8) 146 #define BM_RATE_ADAPTATION_CTRL_RX_CRS_PRE __BIT(7) 147 148 /* KMRN FIFO Control and Status */ 149 #define HV_KMRN_FIFO_CTRLSTA BME1000_REG(770, 16) 150 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 151 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 152 153 #define HV_PM_CTRL BME1000_REG(770, 17) 154 #define HV_PM_CTRL_K1_CLK_REQ __BIT(9) 155 #define HV_PM_CTRL_K1_ENA __BIT(14) 156 157 #define I217_INBAND_CTRL BME1000_REG(770, 18) 158 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3f00 159 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8 160 161 #define IGP3_KMRN_DIAG BME1000_REG(770, 19) 162 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS (1 << 1) 163 164 #define I217_LPI_GPIO_CTRL BME1000_REG(772, 18) 165 #define I217_LPI_GPIO_CTRL_AUTO_EN_LPI __BIT(11) 166 167 #define I82579_LPI_CTRL BME1000_REG(772, 20) 168 #define I82579_LPI_CTRL_ENABLE __BITS(14, 13) 169 #define I82579_LPI_CTRL_EN_100 __BIT(13) 170 #define I82579_LPI_CTRL_EN_1000 __BIT(14) 171 172 #define I217_MEMPWR BME1000_REG(772, 26) 173 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 174 175 #define I217_PLL_CLOCK_GATE_REG BME1000_REG(772, 28) 176 #define I217_PLL_CLOCK_GATE_MASK 0x07FF 177 178 #define I217_CFGREG BME1000_REG(772, 29) 179 #define I217_CGFREG_ENABLE_MTA_RESET 0x0002 180 181 #define HV_MUX_DATA_CTRL BME1000_REG(776, 16) 182 #define HV_MUX_DATA_CTRL_FORCE_SPEED (1 << 2) 183 #define HV_MUX_DATA_CTRL_GEN_TO_MAC (1 << 10) 184 185 #define I82579_UNKNOWN1 BME1000_REG(776, 20) 186 #define I82579_TX_PTR_GAP 0x1f 187 188 #define I218_ULP_CONFIG1 BME1000_REG(779, 16) 189 #define I218_ULP_CONFIG1_START __BIT(0) 190 #define I218_ULP_CONFIG1_IND __BIT(2) 191 #define I218_ULP_CONFIG1_STICKY_ULP __BIT(4) 192 #define I218_ULP_CONFIG1_INBAND_EXIT __BIT(5) 193 #define I218_ULP_CONFIG1_WOL_HOST __BIT(6) 194 #define I218_ULP_CONFIG1_RESET_TO_SMBUS __BIT(8) 195 #define I218_ULP_CONFIG1_EN_ULP_LANPHYPC __BIT(10) 196 #define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST __BIT(11) 197 #define I218_ULP_CONFIG1_DIS_SMB_PERST __BIT(12) 198 199 #define BM_WUC_PAGE 800 200 201 #define BM_RCTL BME1000_REG(BM_WUC_PAGE, 0) 202 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 203 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 204 #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 205 #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 206 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 207 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 208 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 209 210 #define BM_WUC BME1000_REG(BM_WUC_PAGE, 1) 211 #define BM_WUC_ADDRESS_OPCODE 0x11 212 #define BM_WUC_DATA_OPCODE 0x12 213 #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 214 #define BM_WUC_ENABLE_REG 17 215 #define BM_WUC_ENABLE_BIT (1 << 2) 216 #define BM_WUC_HOST_WU_BIT (1 << 4) 217 #define BM_WUC_ME_WU_BIT (1 << 5) 218 219 #define BM_WUFC BME1000_REG(BM_WUC_PAGE, 2) 220 221 #define I217_PROXY_CTRL BME1000_REG(BM_WUC_PAGE, 70) 222 #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 223 224 #define BM_RAR_L(_i) (BME1000_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 225 #define BM_RAR_M(_i) (BME1000_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 226 #define BM_RAR_H(_i) (BME1000_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 227 #define BM_RAR_CTRL(_i) (BME1000_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 228 #define BM_MTA(_i) (BME1000_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 229 230 #endif /* _DEV_MII_INBMPHYREG_H_ */ 231
Indexes created Sat Sep 20 22:09:52 GMT 2025