1 /* $NetBSD: wii.h,v 1.10 2025/02/12 11:31:04 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Nintendo Wii platform definitions. 31 */ 32 33 #ifndef _WII_H 34 #define _WII_H 35 36 #include <powerpc/pio.h> 37 38 #define WII_MEM1_BASE 0x00000000 39 #define WII_MEM1_SIZE 0x01800000 /* 24 MB */ 40 #define WII_MEM2_BASE 0x10000000 41 #define WII_MEM2_SIZE 0x04000000 /* 64 MB */ 42 43 #define WII_IOMEM_BASE 0x0c000000 44 45 #define GLOBAL_BASE 0x00000000 46 #define GLOBAL_SIZE 0x00003400 47 48 #define EFB_BASE 0x08000000 49 #define EFB_SIZE 0x00300000 /* 3 MB */ 50 51 #define BROADWAY_BASE 0x0c000000 52 #define BROADWAY_SIZE 0x00000004 53 54 #define CP_BASE 0x0c000000 55 #define CP_SIZE 0x0c000080 56 57 #define PE_BASE 0x0c001000 58 #define PE_SIZE 0x00000100 59 60 #define VI_BASE 0x0c002000 61 #define VI_SIZE 0x00000100 62 63 #define PI_BASE 0x0c003000 64 #define PI_SIZE 0x00000100 65 66 #define DSP_BASE 0x0c005000 67 #define DSP_SIZE 0x00000200 68 69 #define WGPIPE_BASE 0x0c008000 70 #define WGPIPE_SIZE 0x00000004 71 72 #define EXI_BASE 0x0d006800 73 #define EXI_SIZE 0x00000080 74 75 #define AI_BASE 0x0d006c00 76 #define AI_SIZE 0x00000020 77 78 #define HOLLYWOOD_BASE 0x0d000000 79 #define HOLLYWOOD_PRIV_BASE 0x0d800000 80 #define HOLLYWOOD_SIZE 0x00008000 81 82 #define XFB_START 0x01698000 83 #define XFB_SIZE 0x00168000 84 85 #define DSP_MEM_START 0x10000000 86 #define DSP_MEM_SIZE 0x00004000 87 88 #define IPC_START 0x133e0000 89 #define IPC_SIZE 0x00020000 90 91 #define ARM_START 0x13400000 92 #define ARM_SIZE 0x00c00000 93 94 #define BUS_FREQ_HZ 243000000 95 #define CPU_FREQ_HZ (BUS_FREQ_HZ * 3) 96 #define TIMEBASE_FREQ_HZ (BUS_FREQ_HZ / 4) 97 98 /* Global memory structure */ 99 #define GLOBAL_MEM1_SIZE (GLOBAL_BASE + 0x0028) 100 #define GLOBAL_CUR_VID_MODE (GLOBAL_BASE + 0x00cc) 101 #define GLOBAL_BUS_SPEED (GLOBAL_BASE + 0x00f8) 102 #define GLOBAL_CPU_SPEED (GLOBAL_BASE + 0x00fc) 103 #define GLOBAL_SYSTEM_TIME (GLOBAL_BASE + 0x30d8) 104 #define GLOBAL_MEM2_SIZE (GLOBAL_BASE + 0x3118) 105 #define GLOBAL_MEM2_AVAIL_START (GLOBAL_BASE + 0x3124) 106 #define GLOBAL_MEM2_AVAIL_END (GLOBAL_BASE + 0x3128) 107 #define GLOBAL_IOS_VERSION (GLOBAL_BASE + 0x3140) 108 109 /* Processor interface registers */ 110 #define PI_INTSR (PI_BASE + 0x00) 111 #define PI_INTMR (PI_BASE + 0x04) 112 113 /* GX registers */ 114 #define GX_WGPIPE (GX_BASE + 0x00) 115 116 /* Processor IRQs */ 117 #define PI_IRQ_EXI 4 118 #define PI_IRQ_AI 5 119 #define PI_IRQ_DSP 6 120 #define PI_IRQ_HOLLYWOOD 14 121 122 /* Hollywood registers */ 123 #define HW_VIDIM (HOLLYWOOD_PRIV_BASE + 0x01c) 124 #define VIDIM_E __BIT(7) 125 #define VIDIM_Y __BITS(5,3) 126 #define VIDIM_C __BITS(2,0) 127 #define HW_PPCIRQFLAGS (HOLLYWOOD_BASE + 0x030) 128 #define HW_PPCIRQMASK (HOLLYWOOD_BASE + 0x034) 129 #define HW_ARMIRQFLAGS (HOLLYWOOD_PRIV_BASE + 0x038) 130 #define HW_ARMIRQMASK (HOLLYWOOD_PRIV_BASE + 0x03c) 131 #define HW_AHBPROT (HOLLYWOOD_PRIV_BASE + 0x064) 132 #define IOPSD1EN __BIT(24) 133 #define IOPSD0EN __BIT(23) 134 #define IOPOH1EN __BIT(22) 135 #define IOPOH0EN __BIT(21) 136 #define IOPEHCEN __BIT(20) 137 #define HW_AIPPROT (HOLLYWOOD_PRIV_BASE + 0x070) 138 #define ENAHBIOPI __BIT(0) 139 #define HW_GPIOB_OUT (HOLLYWOOD_BASE + 0x0c0) 140 #define HW_GPIOB_DIR (HOLLYWOOD_BASE + 0x0c4) 141 #define HW_GPIOB_IN (HOLLYWOOD_BASE + 0x0c8) 142 #define HW_GPIO_OWNER (HOLLYWOOD_PRIV_BASE + 0x0fc) 143 #define HW_COMPAT (HOLLYWOOD_PRIV_BASE + 0x180) 144 #define DVDVIDEO __BIT(21) 145 #define HW_RESETS (HOLLYWOOD_PRIV_BASE + 0x194) 146 #define RSTB_IOP __BIT(23) 147 #define RSTB_IODI __BIT(17) 148 #define RSTBINB __BIT(0) 149 #define HW_VERSION (HOLLYWOOD_BASE + 0x214) 150 #define HWVER_MASK __BITS(7,4) 151 #define HWREV_MASK __BITS(3,0) 152 153 /* GPIOs */ 154 #define GPIO_SHUTDOWN 1 155 #define GPIO_DI_SPIN 4 156 #define GPIO_SLOT_LED 5 157 #define GPIO_DO_EJECT 9 158 159 /* Command line protocol */ 160 #define WII_ARGV_MAGIC 0x5f617267 161 struct wii_argv { 162 uint32_t magic; 163 uint32_t cmdline; 164 uint32_t length; 165 uint32_t unused[3]; 166 }; 167 168 /* Blink the slot LED forever at the specified interval. */ 169 static inline void __dead 170 wii_slot_led_blink(u_int interval_us) 171 { 172 uint32_t val; 173 174 for (val = in32(HW_GPIOB_OUT); ; val ^= __BIT(GPIO_SLOT_LED)) { 175 delay(interval_us); 176 out32(HW_GPIOB_OUT, val); 177 } 178 } 179 180 /* Enable or disable the slot LED. */ 181 static inline void 182 wii_slot_led(bool enable) 183 { 184 uint32_t val; 185 186 val = in32(HW_GPIOB_OUT); 187 if (enable) { 188 val |= __BIT(GPIO_SLOT_LED); 189 } else { 190 val &= ~__BIT(GPIO_SLOT_LED); 191 } 192 out32(HW_GPIOB_OUT, val); 193 } 194 195 #endif /* !_WII_H */ 196
Indexes created Sat Sep 20 22:09:52 GMT 2025