1 /* $Id: imx23_icollreg.h,v 1.3 2013/03/03 10:33:56 jkunz Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_IMX_IMX23_ICOLLREG_H_ 33 #define _ARM_IMX_IMX23_ICOLLREG_H_ 34 35 #include <sys/cdefs.h> 36 37 #define HW_ICOLL_BASE 0x80000000 38 #define HW_ICOLL_SIZE 0x2000 39 40 /* 41 * IRQ numbers known to i.MX23. 42 */ 43 #define IRQ_DEBUG_UART 0 /* Non DMA on the debug UART */ 44 #define IRQ_COMMS_RX 1 /* JTAG debug communications port */ 45 #define IRQ_COMMS_TX 1 46 #define IRQ_SSP2_ERROR 2 /* SSP2 device-level error and status */ 47 #define IRQ_VDD5V 3 /* IRQ on 5V connect or disconnect. Shared 48 * with DCDC status, Linear Regulator status, 49 * PSWITCH, and Host 4.2V */ 50 #define IRQ_HEADPHONE_SHORT 4 /* HEADPHONE_SHORT */ 51 #define IRQ_DAC_DMA 5 /* DAC DMA channel */ 52 #define IRQ_DAC_ERROR 6 /* DAC FIFO buffer underflow */ 53 #define IRQ_ADC_DMA 7 /* ADC DMA channel */ 54 #define IRQ_ADC_ERROR 8 /* ADC FIFO buffer overflow */ 55 #define IRQ_SPDIF_DMA 9 /* SPDIF DMA channel, SAIF2 DMA channel */ 56 #define IRQ_SAIF2_DMA 9 57 #define IRQ_SPDIF_ERROR 10 /* SPDIF, SAIF1, SAIF2 FIFO 58 * underflow/overflow */ 59 #define IRQ_SAIF1_IRQ 10 60 #define IRQ_SAIF2_IRQ 10 61 #define IRQ_USB_CTRL 11 /* USB controller */ 62 #define IRQ_USB_WAKEUP 12 /* USB wakeup. Also ARC core to remain 63 * suspended. */ 64 #define IRQ_GPMI_DMA 13 /* From DMA channel for GPMI */ 65 #define IRQ_SSP1_DMA 14 /* From DMA channel for SSP1 */ 66 #define IRQ_SSP1_ERROR 15 /* SSP1 device-level error and status */ 67 #define IRQ_GPIO0 16 /* GPIO bank 0 interrupt */ 68 #define IRQ_GPIO1 17 /* GPIO bank 1 interrupt */ 69 #define IRQ_GPIO2 18 /* GPIO bank 2 interrupt */ 70 #define IRQ_SAIF1_DMA 19 /* SAIF1 DMA channel */ 71 #define IRQ_SSP2_DMA 20 /* From DMA channel for SSP2 */ 72 #define IRQ_ECC8_IRQ 21 /* ECC8 completion interrupt */ 73 #define IRQ_RTC_ALARM 22 /* RTC alarm event */ 74 #define IRQ_UARTAPP_TX_DMA 23 /* Application UART1 transmitter DMA */ 75 #define IRQ_UARTAPP_INTERNAL 24 /* Application UART1 internal error */ 76 #define IRQ_UARTAPP_RX_DMA 25 /* Application UART1 receiver DMA */ 77 #define IRQ_I2C_DMA 26 /* From DMA channel for I2C */ 78 #define IRQ_I2C_ERROR 27 /* From I2C device detected errors and line 79 * conditions. */ 80 #define IRQ_TIMER0 28 /* TIMROT Timer0, recommend to set as FIQ. */ 81 #define IRQ_TIMER1 29 /* TIMROT Timer1, recommend to set as FIQ. */ 82 #define IRQ_TIMER2 30 /* TIMROT Timer2, recommend to set as FIQ. */ 83 #define IRQ_TIMER3 31 /* TIMROT Timer3, recommend to set as FIQ. */ 84 #define IRQ_BATT_BRNOUT 32 /* Power module battery brownout detect, 85 * recommend to set as FIQ. */ 86 #define IRQ_VDDD_BRNOUT 33 /* Power module VDDD brownout detect, 87 * recommend to set as FIQ. */ 88 #define IRQ_VDDIO_BRNOUT 34 /* Power module VDDIO brownout detect, 89 * recommend to set as FIQ. */ 90 #define IRQ_VDD18_BRNOUT 35 /* Power module VDD18 brownout detect, 91 * recommend to set as FIQ. */ 92 #define IRQ_TOUCH_DETECT 36 /* Touch detection. */ 93 #define IRQ_LRADC_CH0 37 /* Channel 0 complete. */ 94 #define IRQ_LRADC_CH1 38 /* Channel 1 complete. */ 95 #define IRQ_LRADC_CH2 39 /* Channel 2 complete. */ 96 #define IRQ_LRADC_CH3 40 /* Channel 3 complete. */ 97 #define IRQ_LRADC_CH4 41 /* Channel 4 complete. */ 98 #define IRQ_LRADC_CH5 42 /* Channel 5 complete. */ 99 #define IRQ_LRADC_CH6 43 /* Channel 6 complete. */ 100 #define IRQ_LRADC_CH7 44 /* Channel 7 complete. */ 101 #define IRQ_LCDIF_DMA 45 /* From DMA channel for LCDIF. */ 102 #define IRQ_LCDIF_ERROR 46 /* LCDIF error. */ 103 #define IRQ_DIGCTL_DEBUG_TRAP 47 /* AHB arbiter debug trap. */ 104 #define IRQ_RTC_1MSEC 48 /* RTC 1 ms tick interrupt. */ 105 #define IRQ_RSVD49 49 /* Reserved */ 106 #define IRQ_RSVD50 50 /* Reserved */ 107 #define IRQ_GPMI 51 /* From GPMI internal error and status IRQ.*/ 108 #define IRQ_RSVD52 52 /* Reserved */ 109 #define IRQ_DCP_VMI 53 /* DCP Channel 0 virtual memory page copy. */ 110 #define IRQ_DCP 54 /* DCP */ 111 #define IRQ_RSVD55 55 /* Reserved. */ 112 #define IRQ_BCH 56 /* BCH consolidated Interrupt */ 113 #define IRQ_PXP 57 /* Pixel Pipeline consolidated Interrupt */ 114 #define IRQ_UARTAPP2_TX_DMA 58 /* Application UART2 transmitter DMA */ 115 #define IRQ_UARTAPP2_INTERNAL 59 /* Application UART2 internal error */ 116 #define IRQ_UARTAPP2_RX_DMA 60 /* Application UART2 receiver DMA */ 117 #define IRQ_VDAC_DETECT 61 /* Video dac, jack presence auto-detect */ 118 #define IRQ_RSVD62 62 /* Reserved. */ 119 #define IRQ_RSVD63 63 /* Reserved. */ 120 #define IRQ_VDD5V_DROOP 64 /* 5V Droop, recommend to be set as FIQ. */ 121 #define IRQ_DCDC4P2_BO 65 /* 4.2V regulated supply brown-out, 122 * recommend to be set as FIQ. */ 123 124 #define IRQ_LAST IRQ_DCDC4P2_BO 125 126 /* IRQ's 66-127 are reserved. */ 127 128 #define IRQ_MAX 127 /* Number or IRQ registers on i.MX23. */ 129 130 131 /* 132 * Interrupt Collector Interrupt Vector Address Register. 133 */ 134 #define HW_ICOLL_VECTOR 0x000 135 #define HW_ICOLL_VECTOR_SET 0x004 136 #define HW_ICOLL_VECTOR_CLR 0x008 137 #define HW_ICOLL_VECTOR_TOG 0x00C 138 139 #define HW_ICOLL_VECTOR_IRQVECTOR __BITS(32, 2) 140 #define HW_ICOLL_VECTOR_RSRVD1 __BITS(1, 0) 141 142 /* 143 * Interrupt Collector Level Acknowledge Register. 144 */ 145 #define HW_ICOLL_LEVELACK 0x010 146 147 #define HW_ICOLL_LEVELACK_RSRVD1 __BITS(31, 4) 148 #define HW_ICOLL_LEVELACK_IRQLEVELACK __BIT(3, 0) 149 150 /* 151 * Interrupt Collector Control Register. 152 */ 153 #define HW_ICOLL_CTRL 0x020 154 #define HW_ICOLL_CTRL_SET 0x024 155 #define HW_ICOLL_CTRL_CLR 0x028 156 #define HW_ICOLL_CTRL_TOG 0x02C 157 158 #define HW_ICOLL_CTRL_SFTRST __BIT(31) 159 #define HW_ICOLL_CTRL_CLKGATE __BIT(30) 160 #define HW_ICOLL_CTRL_RSRVD3 __BITS(29, 24) 161 #define HW_ICOLL_CTRL_VECTOR_PITCH __BITS(23, 21) 162 #define HW_ICOLL_CTRL_BYPASS_FSM __BIT(20) 163 #define HW_ICOLL_CTRL_NO_NESTING __BIT(19) 164 #define HW_ICOLL_CTRL_ARM_RSE_MODE __BIT(18) 165 #define HW_ICOLL_CTRL_FIQ_FINAL_ENABLE __BIT(17) 166 #define HW_ICOLL_CTRL_IRQ_FINAL_ENABLE __BIT(16) 167 #define HW_ICOLL_CTRL_RSRVD1 __BITS(15, 0) 168 169 /* 170 * Interrupt Collector Interrupt Vector Base Address Register. 171 */ 172 #define HW_ICOLL_VBASE 0x040 173 #define HW_ICOLL_VBASE_SET 0x044 174 #define HW_ICOLL_VBASE_CLR 0x048 175 #define HW_ICOLL_VBASE_TOG 0x04C 176 177 #define HW_ICOLL_VBASE_TABLE_ADDRESS __BITS(32, 2) 178 #define HW_ICOLL_VBASE_RSRVD1 __BITS(1, 0) 179 180 /* 181 * Interrupt Collector Status Register. 182 */ 183 #define HW_ICOLL_STAT 0x070 184 185 #define HW_ICOLL_STAT_RSRVD1 __BITS(31, 7) 186 #define HW_ICOLL_STAT_VECTOR_NUMBER __BITS(6, 0) 187 188 /* 189 * Interrupt Collector Raw Interrupt Input Register. 190 */ 191 #define HW_ICOLL_RAW0 0x0A0 192 #define HW_ICOLL_RAW0_SET 0x0A4 193 #define HW_ICOLL_RAW0_CLR 0x0A8 194 #define HW_ICOLL_RAW0_TOG 0x0AC 195 196 #define HW_ICOLL_RAW0_RAW_IRQS __BITS(31, 0) 197 198 /* 199 * Interrupt Collector Raw Interrupt Input Register 1. 200 */ 201 #define HW_ICOLL_RAW1 0x0B0 202 #define HW_ICOLL_RAW1_SET 0x0B4 203 #define HW_ICOLL_RAW1_CLR 0x0B8 204 #define HW_ICOLL_RAW1_TOG 0x0BC 205 206 #define HW_ICOLL_RAW1_RAW_IRQS __BITS(31, 0) 207 208 /* 209 * Interrupt Collector Raw Interrupt Input Register 2. 210 */ 211 #define HW_ICOLL_RAW2 0x0C0 212 #define HW_ICOLL_RAW2_SET 0x0C4 213 #define HW_ICOLL_RAW2_CLR 0x0C8 214 #define HW_ICOLL_RAW2_TOG 0x0CC 215 216 #define HW_ICOLL_RAW2_RAW_IRQS __BITS(31, 0) 217 218 /* 219 * Interrupt Collector Raw Interrupt Input Register 3. 220 */ 221 #define HW_ICOLL_RAW3 0x0D0 222 #define HW_ICOLL_RAW3_SET 0x0D4 223 #define HW_ICOLL_RAW3_CLR 0x0D8 224 #define HW_ICOLL_RAW3_TOG 0x0DC 225 226 #define HW_ICOLL_RAW3_RAW_IRQS __BITS(31, 0) 227 228 /* 229 * Interrupt Collector Interrupt common registers. 230 */ 231 #define HW_ICOLL_INTERRUPT_RSRVD1 __BITS(31, 5) 232 #define HW_ICOLL_INTERRUPT_ENFIQ __BIT(4) 233 #define HW_ICOLL_INTERRUPT_SOFTIRQ __BIT(3) 234 #define HW_ICOLL_INTERRUPT_ENABLE __BIT(2) 235 #define HW_ICOLL_INTERRUPT_PRIORITY __BITS(1, 0) 236 237 /* 238 * Interrupt Collector Interrupt Register 0. 239 */ 240 #define HW_ICOLL_INTERRUPT0 0x120 241 #define HW_ICOLL_INTERRUPT0_SET 0x124 242 #define HW_ICOLL_INTERRUPT0_CLR 0x128 243 #define HW_ICOLL_INTERRUPT0_TOG 0x12C 244 245 #define HW_ICOLL_INTERRUPT0_RSRVD1 __BITS(31, 5) 246 #define HW_ICOLL_INTERRUPT0_ENFIQ __BIT(4) 247 #define HW_ICOLL_INTERRUPT0_SOFTIRQ __BIT(3) 248 #define HW_ICOLL_INTERRUPT0_ENABLE __BIT(2) 249 #define HW_ICOLL_INTERRUPT0_PRIORITY __BITS(1, 0) 250 251 /* 252 * Interrupt Collector Interrupt Register 127. 253 */ 254 #define HW_ICOLL_INTERRUPT127 0x910 255 #define HW_ICOLL_INTERRUPT127_SET 0x914 256 #define HW_ICOLL_INTERRUPT127_CLR 0x918 257 #define HW_ICOLL_INTERRUPT127_TOG 0x91C 258 259 #define HW_ICOLL_INTERRUPT127_RSRVD1 __BITS(31, 5) 260 #define HW_ICOLL_INTERRUPT127_ENFIQ __BIT(4) 261 #define HW_ICOLL_INTERRUPT127_SOFTIRQ __BIT(3) 262 #define HW_ICOLL_INTERRUPT127_ENABLE __BIT(2) 263 #define HW_ICOLL_INTERRUPT127_PRIORITY __BITS(1, 0) 264 265 /* 266 * Interrupt Collector Debug Register 0. 267 */ 268 #define HW_ICOLL_DEBUG 0x1120 269 #define HW_ICOLL_DEBUG_SET 0x1124 270 #define HW_ICOLL_DEBUG_CLR 0x1128 271 #define HW_ICOLL_DEBUG_TOG 0x112C 272 273 #define HW_ICOLL_DEBUG_INSERVICE __BITS(31, 28) 274 #define HW_ICOLL_DEBUG_LEVEL_REQUESTS __BITS(27, 24) 275 #define HW_ICOLL_DEBUG_REQUESTS_BY_LEVEL __BITS(23, 20) 276 #define HW_ICOLL_DEBUG_RSRVD2 __BITS(19, 18) 277 #define HW_ICOLL_DEBUG_FIQ __BIT(17) 278 #define HW_ICOLL_DEBUG_IRQ __BIT(16) 279 #define HW_ICOLL_DEBUG_RSRVD1 __BITS(15, 10) 280 #define HW_ICOLL_DEBUG_VECTOR_FSM __BITS(9, 0) 281 282 /* 283 * Interrupt Collector Debug Read Register 0. 284 */ 285 #define HW_ICOLL_DBGREAD0 0x1130 286 #define HW_ICOLL_DBGREAD0_SET 0x1134 287 #define HW_ICOLL_DBGREAD0_CLR 0x1138 288 #define HW_ICOLL_DBGREAD0_TOG 0x113C 289 290 #define HW_ICOLL_DBGREAD0_VALUE __BITS(31, 0) 291 292 /* 293 * Interrupt Collector Debug Read Register 1. 294 */ 295 #define HW_ICOLL_DBGREAD1 0x1140 296 #define HW_ICOLL_DBGREAD1_SET 0x1144 297 #define HW_ICOLL_DBGREAD1_CLR 0x1148 298 #define HW_ICOLL_DBGREAD1_TOG 0x114C 299 300 #define HW_ICOLL_DBGREAD1_VALUE __BITS(31, 0) 301 302 /* 303 * Interrupt Collector Debug Flag Register. 304 */ 305 #define HW_ICOLL_DBGFLAG 0x1150 306 #define HW_ICOLL_DBGFLAG_SET 0x1154 307 #define HW_ICOLL_DBGFLAG_CLR 0x1158 308 #define HW_ICOLL_DBGFLAG_TOG 0x115C 309 310 #define HW_ICOLL_DBGFLAG_RSRVD1 __BITS(31, 16) 311 #define HW_ICOLL_DBGFLAG_FLAG __BITS(15, 0) 312 313 /* 314 * Interrupt Collector Debug Read Request Register 0. 315 */ 316 #define HW_ICOLL_DBGREQUEST0 0x1160 317 #define HW_ICOLL_DBGREQUEST0_SET 0x1164 318 #define HW_ICOLL_DBGREQUEST0_CLR 0x1168 319 #define HW_ICOLL_DBGREQUEST0_TOG 0x116C 320 321 #define HW_ICOLL_DBGREQUEST0_BITS __BITS(31, 0) 322 323 /* 324 * Interrupt Collector Debug Read Request Register 1. 325 */ 326 #define HW_ICOLL_DBGREQUEST1 0x1170 327 #define HW_ICOLL_DBGREQUEST1_SET 0x1174 328 #define HW_ICOLL_DBGREQUEST1_CLR 0x1178 329 #define HW_ICOLL_DBGREQUEST1_TOG 0x117C 330 331 #define HW_ICOLL_DBGREQUEST1_BITS __BITS(31, 0) 332 333 /* 334 * Interrupt Collector Debug Read Request Register 2. 335 */ 336 #define HW_ICOLL_DBGREQUEST2 0x1180 337 #define HW_ICOLL_DBGREQUEST2_SET 0x1184 338 #define HW_ICOLL_DBGREQUEST2_CLR 0x1188 339 #define HW_ICOLL_DBGREQUEST2_TOG 0x118C 340 341 #define HW_ICOLL_DBGREQUEST2_BITS __BITS(31, 0) 342 343 /* 344 * Interrupt Collector Debug Read Request Register 3. 345 */ 346 #define HW_ICOLL_DBGREQUEST3 0x1190 347 #define HW_ICOLL_DBGREQUEST3_SET 0x1194 348 #define HW_ICOLL_DBGREQUEST3_CLR 0x1198 349 #define HW_ICOLL_DBGREQUEST3_TOG 0x119C 350 351 #define HW_ICOLL_DBGREQUEST3_BITS __BITS(31, 0) 352 353 /* 354 * Interrupt Collector Version Register. 355 */ 356 #define HW_ICOLL_VERSION 0x11E0 357 358 #define HW_ICOLL_VERSION_MAJOR __BITS(31, 24) 359 #define HW_ICOLL_VERSION_MINOR __BITS(23, 16) 360 #define HW_ICOLL_VERSION_STEP __BITS(15, 0) 361 362 #endif /* !_ARM_IMX_IMX23_ICOLLREG_H_ */ 363
Indexes created Mon Sep 22 21:09:42 GMT 2025