| /src/external/apache2/llvm/dist/libcxx/include/__support/ibm/ |
| gettod_zos.h | 22 uint64_t Hi;
36 uint64_t us = (Value.Hi >> 4);
37 uint64_t ns = ((Value.Hi & 0x0F) << 8) + (Value.Lo >> 56);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 47 SDNode *Lo = nullptr, *Hi = nullptr;
59 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
61 return std::make_pair(Lo, Hi);
145 // lui $2, %hi($CPI1_0)
149 // lui $2, %hi($CPI1_0)
|
| MipsISelLowering.h | 74 // No relation with Mips Hi register
75 Hi,
408 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
414 SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
416 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
417 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
425 // (add %hi(sym), %lo(sym))
431 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
434 DAG.getNode(MipsISD::Hi, DL, Ty, Hi)
[all...] |
| MipsCallLowering.cpp | 147 auto Hi = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 1 : 0)));
148 MIRBuilder.buildMerge(ValVReg, {Lo, Hi});
|
| MipsInstructionSelector.cpp | 549 Register Hi = I.getOperand(1).getReg();
551 !(isRegInGprb(Lo, MRI) && isRegInGprb(Hi, MRI)))
565 .addDef(Hi)
|
| MipsSEFrameLowering.cpp | 202 // copy hi, $vr1
211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
811 // ISRs require HI/LO to be spilled into kernel registers to be then
|
| MipsSEISelDAGToDAG.cpp | 339 // lui $2, %hi($CPI1_0)
343 // lui $2, %hi($CPI1_0)
1138 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1142 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1144 if (Hi)
1149 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1151 assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!");
1161 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1165 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1167 if (Hi)
[all...] |
| MipsFastISel.cpp | 376 unsigned Hi = (Imm >> 16) & 0xFFFF;
378 // Both Lo and Hi have nonzero bits.
380 emitInst(Mips::LUi, TmpReg).addImm(Hi);
383 emitInst(Mips::LUi, ResultReg).addImm(Hi);
|
| MipsSEISelLowering.cpp | 731 // to retrieve the result from the HI/LO registers.
736 // HI/LO registers.
1191 SDValue Hi = DAG.getLoad(
1196 std::swap(Lo, Hi);
1198 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1199 SDValue Ops[2] = {BP, Hi.getValue(1)};
1215 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1219 std::swap(Lo, Hi);
1228 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1243 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32
[all...] |
| /src/sys/external/bsd/acpica/dist/utilities/ |
| utmath.c | 56 UINT32 Hi;
107 ACPI_MUL_64_BY_32 (0, MultiplicandOvl.Part.Hi, Multiplier,
108 Product.Part.Hi, Carry32);
113 Product.Part.Hi += Carry32;
154 OperandOvl.Part.Hi = OperandOvl.Part.Lo;
158 ACPI_SHIFT_LEFT_64_BY_32 (OperandOvl.Part.Hi,
199 OperandOvl.Part.Lo = OperandOvl.Part.Hi;
200 OperandOvl.Part.Hi = 0;
203 ACPI_SHIFT_RIGHT_64_BY_32 (OperandOvl.Part.Hi,
365 ACPI_DIV_64_BY_32 (0, DividendOvl.Part.Hi, Divisor
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| SwitchLoweringUtils.cpp | 75 const APInt &Hi = Clusters[i].High->getValue();
77 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
431 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
432 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
433 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
434 CB->Bits += Hi - Lo + 1;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/Disassembler/ |
| BPFDisassembler.cpp | 143 uint64_t Lo, Hi;
152 Hi = (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 0) | (Bytes[3] << 8);
155 Hi = (Bytes[0] << 24) | ((Bytes[1] & 0x0F) << 20) | ((Bytes[1] & 0xF0) << 12) |
159 Insn = Make_64(Hi, Lo);
169 uint64_t Insn, Hi;
198 Hi = (Bytes[12] << 0) | (Bytes[13] << 8) | (Bytes[14] << 16) | (Bytes[15] << 24);
200 Hi = (Bytes[12] << 24) | (Bytes[13] << 16) | (Bytes[14] << 8) | (Bytes[15] << 0);
202 Op.setImm(Make_64(Hi, Op.getImm()));
|
| /src/crypto/external/apache2/openssl/dist/crypto/modes/ |
| gcm128.c | 41 V.lo = (V.hi << 63) | (V.lo >> 1); \
42 V.hi = (V.hi >> 1) ^ T; \
45 V.lo = (V.hi << 63) | (V.lo >> 1); \
46 V.hi = (V.hi >> 1) ^ ((u64)T << 32); \
95 Htable[0].hi = 0;
97 V.hi = H[0];
107 u128 *Hi = Htable + i;
109 for (V = *Hi, j = 1; j < i; ++j)
[all...] |
| /src/crypto/external/bsd/openssl/dist/crypto/modes/ |
| gcm128.c | 34 V.lo = (V.hi<<63)|(V.lo>>1); \
35 V.hi = (V.hi>>1 )^T; \
39 V.lo = (V.hi<<63)|(V.lo>>1); \
40 V.hi = (V.hi>>1 )^((u64)T<<32); \
85 Htable[0].hi = 0;
87 V.hi = H[0];
96 u128 *Hi = Htable + i, H0 = *Hi;
[all...] |
| /src/crypto/external/bsd/openssl.old/dist/crypto/modes/ |
| gcm128.c | 32 V.lo = (V.hi<<63)|(V.lo>>1); \
33 V.hi = (V.hi>>1 )^T; \
37 V.lo = (V.hi<<63)|(V.lo>>1); \
38 V.hi = (V.hi>>1 )^((u64)T<<32); \
83 Htable[0].hi = 0;
85 V.hi = H[0];
94 u128 *Hi = Htable + i, H0 = *Hi;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 469 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
471 std::swap(Lo, Hi);
476 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
480 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
573 SDValue Lo, Hi;
585 Hi = DAG.getNode(
589 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
596 Hi = DAG.getNode
[all...] |
| LegalizeTypesGeneric.cpp | 13 // computation in two identical registers of a smaller type. The Lo/Hi part
31 // These routines assume that the Lo/Hi part is stored first in memory on
32 // little/big-endian machines, followed by the Hi/Lo part. This means that
35 SDValue &Lo, SDValue &Hi) {
37 GetExpandedOp(Op, Lo, Hi);
40 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
57 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi);
59 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
65 GetExpandedOp(InOp, Lo, Hi);
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/ProfileData/ |
| GCOV.h | 163 uint32_t Lo, Hi;
164 if (!readInt(Lo) || !readInt(Hi))
166 Val = ((uint64_t)Hi << 32) | Lo;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/ |
| M68kDisassembler.cpp | 172 uint64_t Hi = Bytes[Offset];
174 uint64_t Word = (Hi << 8) | Lo;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonSplitDouble.cpp | 339 unsigned Hi = D >> 32;
340 return profitImm(Lo) + profitImm(Hi);
818 // HiR = or (TmpR, asl(R.hi, #s))
820 // HiR = shr R.hi, #s
822 // LoR = insert TmpR, R.hi, #s, #32-s
848 // HiR = or (TmpR, asl(R.hi, #s))
854 // HiR = shr R.hi, #s
858 // LoR = insert TmpR, R.hi, #s, #32-s
934 // Tmp2 = or R1.hi, Tmp1
935 // HiR = or (Tmp2, asl(R2.hi, #s)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 1114 case LanaiISD::HI:
1115 return "LanaiISD::HI";
1147 SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
1151 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1153 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1182 SDValue Hi = DAG.getTargetGlobalAddress(
1186 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 2666 SDValue Lo, Hi;
2669 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2674 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2958 SDValue Lo, Hi;
2987 Hi = DAG.getBitcast(MVT::v32i1, ArgValueHi);
2990 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
5590 static bool isInRange(int Val, int Low, int Hi) {
5591 return (Val >= Low && Val < Hi);
5596 static bool isAnyInRange(ArrayRef<int> Mask, int Low, int Hi) {
5597 return llvm::any_of(Mask, [Low, Hi](int M) { return isInRange(M, Low, Hi); })
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| MCStreamer.cpp | 1012 MCSymbol *Hi = Context.createTempSymbol(Prefix + "_end");
1015 Hi, Lo, dwarf::getDwarfOffsetByteSize(Context.getDwarfFormat()));
1018 // Return the Hi symbol to the caller.
1019 return Hi;
1098 void MCStreamer::emitAbsoluteSymbolDiff(const MCSymbol *Hi, const MCSymbol *Lo,
1100 // Get the Hi-Lo expression.
1102 MCBinaryExpr::createSub(MCSymbolRefExpr::create(Hi, Context),
1117 void MCStreamer::emitAbsoluteSymbolDiffAsULEB128(const MCSymbol *Hi,
1119 // Get the Hi-Lo expression.
1121 MCBinaryExpr::createSub(MCSymbolRefExpr::create(Hi, Context)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUCodeGenPrepare.cpp | 824 Value *Hi = Builder.CreateLShr(MUL64, Builder.getInt64(32));
825 Hi = Builder.CreateTrunc(Hi, I32Ty);
826 return std::make_pair(Lo, Hi);
|
| R600ISelLowering.cpp | 770 SDValue Lo, Hi;
771 expandShiftParts(Op.getNode(), Lo, Hi, DAG);
772 return DAG.getMergeValues({Lo, Hi}, SDLoc(Op));
781 SDValue Hi = Op.getOperand(1);
783 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi);
788 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi);
|
