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  /src/external/gpl3/gdb/dist/sim/testsuite/bfin/
issue142.s 18 I1 = 0 (X);
a12.s 8 I1 = 0;
11080.s 9 I1 = R0;
21 DISALGNEXCPT || R2 = [I1++M0]; // i1 = 0xff9004aa (misaligned)
d0.s 6 I1 = 0x4 (X);
10 I1 -= M0;
11 R0 = I1;
14 I1 = 0xf0 (X);
18 I1 += M0;
19 R0 = I1;
c_ldstpmod_ld_dr_hi.s 19 I1 = P3; P3 = I0; I3 = SP; SP = I2;
22 loadsym i1, DATA_ADDR_4, 0x04;
27 P3 = I1; SP = I3;
c_ldstpmod_ld_dr_lo.s 18 I1 = P3; P3 = I0; I3 = SP; SP = I2;
21 loadsym i1, DATA_ADDR_4, 0x04;
26 P3 = I1; SP = I3;
c_ldstpmod_st_dr_hi.s 26 I1 = P3; P3 = I0; I3 = SP; SP = I2;
29 loadsym i1, DATA_ADDR_3, 0x04;
34 P3 = I1; SP = I3;
66 I1 = P3; P3 = I0; I3 = SP; SP = I2;
69 loadsym i1, DATA_ADDR_3, 0x08;
74 P3 = I1; SP = I3;
106 I1 = P3; P3 = I0; I3 = SP; SP = I2;
109 loadsym i1, DATA_ADDR_3, 0x00;
114 P3 = I1; SP = I3;
c_ldstpmod_st_dr_lo.s 26 I1 = P3; P3 = I0; I3 = SP; SP = I2;
29 loadsym i1, DATA_ADDR_3, 0x04;
34 P3 = I1; SP = I3;
67 I1 = P3; P3 = I0; I3 = SP; SP = I2;
70 loadsym i1, DATA_ADDR_3, 0x08;
75 P3 = I1; SP = I3;
107 I1 = P3; P3 = I0; I3 = SP; SP = I2;
110 loadsym i1, DATA_ADDR_3, 0x00;
115 P3 = I1; SP = I3;
pr.s 7 I1 = R3;
21 [i1] = r0;
31 MNOP || R2 = [ I0 ++ ] || R1 = [ I1 ++ ];
c_ldstidxl_ld_dr_h.s 19 I1 = P3; P3 = I0; I3 = SP; SP = I2;
22 loadsym i1, DATA_ADDR_1, 0x70;
27 P3 = I1; SP = I3;
c_ldstidxl_ld_dr_xb.s 18 I1 = P3; P3 = I0; I3 = SP; SP = I2;
21 loadsym i1, DATA_ADDR_1, 0x70;
26 P3 = I1; SP = I3;
c_ldstidxl_ld_dr_xh.s 19 I1 = P3; P3 = I0; I3 = SP; SP = I2;
22 loadsym i1, DATA_ADDR_1, 0x70;
27 P3 = I1; SP = I3;
c_ldstidxl_ld_preg.s 18 I1 = P3; P3 = I0; I3 = SP; SP = I2;
21 loadsym i1, DATA_ADDR_1, 0x70;
26 P3 = I1; SP = I3;
43 I1 = P3; P3 = I0; I3 = SP; SP = I2;
45 P3 = I1; SP = I3;
62 I1 = P3; P3 = I0; I3 = SP; SP = I2;
63 loadsym i1, DATA_ADDR_1, 0x70;
64 P3 = I1; SP = I3;
80 I1 = P3; P3 = I0; I3 = SP; SP = I2;
82 P3 = I1; SP = I3
    [all...]
c_ldstidxl_st_dreg.s 26 I1 = P3; P3 = I0; I3 = SP; SP = I2;
29 loadsym i1, DATA_ADDR_1, 0x10;
34 P3 = I1; SP = I3;
c_ldstiifp_ld_preg.s 18 I1 = P3; P3 = I0; I3 = SP; SP = I2;
20 P3 = I1; SP = I3;
22 P3 = I1; SP = I3;
38 I1 = P3; P3 = I0; I3 = SP; SP = I2;
40 P3 = I1; SP = I3;
57 I1 = P3; P3 = I0; I3 = SP; SP = I2;
59 P3 = I1; SP = I3;
76 I1 = P3; P3 = I0; I3 = SP; SP = I2;
78 P3 = I1; SP = I3;
95 I1 = P3; P3 = I0; I3 = SP; SP = I2
    [all...]
c_progctrl_nop.s 16 I1 = 0x3344 (Z);
18 R1 = I1;
  /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
issue142.s 18 I1 = 0 (X);
a12.s 8 I1 = 0;
11080.s 9 I1 = R0;
21 DISALGNEXCPT || R2 = [I1++M0]; // i1 = 0xff9004aa (misaligned)
d0.s 6 I1 = 0x4 (X);
10 I1 -= M0;
11 R0 = I1;
14 I1 = 0xf0 (X);
18 I1 += M0;
19 R0 = I1;
c_ldstpmod_ld_dr_hi.s 19 I1 = P3; P3 = I0; I3 = SP; SP = I2;
22 loadsym i1, DATA_ADDR_4, 0x04;
27 P3 = I1; SP = I3;
c_ldstpmod_ld_dr_lo.s 18 I1 = P3; P3 = I0; I3 = SP; SP = I2;
21 loadsym i1, DATA_ADDR_4, 0x04;
26 P3 = I1; SP = I3;
c_ldstpmod_st_dr_hi.s 26 I1 = P3; P3 = I0; I3 = SP; SP = I2;
29 loadsym i1, DATA_ADDR_3, 0x04;
34 P3 = I1; SP = I3;
66 I1 = P3; P3 = I0; I3 = SP; SP = I2;
69 loadsym i1, DATA_ADDR_3, 0x08;
74 P3 = I1; SP = I3;
106 I1 = P3; P3 = I0; I3 = SP; SP = I2;
109 loadsym i1, DATA_ADDR_3, 0x00;
114 P3 = I1; SP = I3;
c_ldstpmod_st_dr_lo.s 26 I1 = P3; P3 = I0; I3 = SP; SP = I2;
29 loadsym i1, DATA_ADDR_3, 0x04;
34 P3 = I1; SP = I3;
67 I1 = P3; P3 = I0; I3 = SP; SP = I2;
70 loadsym i1, DATA_ADDR_3, 0x08;
75 P3 = I1; SP = I3;
107 I1 = P3; P3 = I0; I3 = SP; SP = I2;
110 loadsym i1, DATA_ADDR_3, 0x00;
115 P3 = I1; SP = I3;
pr.s 7 I1 = R3;
21 [i1] = r0;
31 MNOP || R2 = [ I0 ++ ] || R1 = [ I1 ++ ];

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