1 /* $NetBSD: i82596reg.h,v 1.4 2008/04/05 08:42:35 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Jochen Kunz. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Jochen Kunz may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY JOCHEN KUNZ 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL JOCHEN KUNZ 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* All definitions are for a Intel 82596 DX/SX / CA in linear 32 bit mode. */ 33 34 #define IEE_SYSBUS_BE 0x80 /* == 1 32 bit pointers are big endian */ 35 #define IEE_SYSBUS_INT 0x20 /* == 1 interrupt pin is active low */ 36 #define IEE_SYSBUS_LOCK 0x10 /* == 1 lock function disabled */ 37 #define IEE_SYSBUS_TRG 0x08 /* == 1 external triggering of bus throttle */ 38 #define IEE_SYSBUS_M1 0x04 /* M1 == 0 && M0 == 0 82586 mode */ 39 #define IEE_SYSBUS_M0 0x02 /* M1 == 0 && M0 == 1 32 bit segmented mode */ 40 /* M1 == 1 && M0 == 0 linear mode */ 41 /* M1 == 1 && M0 == 1 reserved */ 42 #define IEE_SYSBUS_M 0x06 /* mode mask */ 43 #define IEE_SYSBUS_82586 0x00 /* 82586 mode */ 44 #define IEE_SYSBUS_32SEG 0x02 /* 32 bit segmented mode */ 45 #define IEE_SYSBUS_LIEAR 0x04 /* linear mode */ 46 #define IEE_SYSBUS_STD 0x40 /* must be 1 all times */ 47 48 #define IEE_PORT_RESET 0x0 /* PORT command reset */ 49 #define IEE_PORT_SEFTST 0x1 /* PORT command self test */ 50 #define IEE_PORT_SCP 0x2 /* PORT command set SCP */ 51 #define IEE_PORT_DUMP 0x3 /* PORT command dump aread pointer */ 52 53 /* System Control Block Command word.*/ 54 #define IEE_SCB_ACK_CX 0x8000 /* CU completed an Action */ 55 #define IEE_SCB_ACK_FR 0x4000 /* RU received a frame */ 56 #define IEE_SCB_ACK_CNA 0x2000 /* CU became not active */ 57 #define IEE_SCB_ACK_RNR 0x1000 /* RU became not active */ 58 #define IEE_SCB_ACK 0xf000 /* Acknowledge mask */ 59 60 #define IEE_SCB_CUC_NOP 0x0000 /* NOP, does not affect state of unit */ 61 #define IEE_SCB_CUC_EXE 0x0100 /* Start execution of CMD on CBL */ 62 #define IEE_SCB_CUC_RES 0x0200 /* Resume operat. of CU after suspend */ 63 #define IEE_SCB_CUC_SUS 0x0300 /* Suspend exec. of cmds on CBL */ 64 #define IEE_SCB_CUC_ABR 0x0400 /* Abort current command */ 65 #define IEE_SCB_CUC_BT 0x0500 /* Load Bus Throttle */ 66 #define IEE_SCB_CUC_BTI 0x0600 /* Load Bus Throttle immediately */ 67 #define IEE_SCB_CUC 0x0700 /* Command mask */ 68 69 #define IEE_SCB_RESET 0x0080 /* Reset the Chip */ 70 71 #define IEE_SCB_RUC_NOP 0x0000 /* NOP, does not affect state of unit */ 72 #define IEE_SCB_RUC_ST 0x0010 /* Start reception of frames */ 73 #define IEE_SCB_RUC_RES 0x0020 /* Resume operat. of RU after suspend */ 74 #define IEE_SCB_RUC_SUS 0x0030 /* Suspend frame reception */ 75 #define IEE_SCB_RUC_ABR 0x0040 /* Abort receiver operat. immediately */ 76 #define IEE_SCB_RUC 0x0070 /* Command mask */ 77 78 /* System Control Block Status word.*/ 79 #define IEE_SCB_STAT_CX 0x8000 /* CU finished cmd with int bit set */ 80 #define IEE_SCB_STAT_FR 0x4000 /* RU finished receiving a frame */ 81 #define IEE_SCB_STAT_CNA 0x2000 /* CU left active state */ 82 #define IEE_SCB_STAT_RNR 0x1000 /* RU left ready state */ 83 #define IEE_SCB_STAT 0xf000 /* Status mask */ 84 85 #define IEE_SCB_CUS_IDL 0x0000 /* Idle */ 86 #define IEE_SCB_CUS_SUS 0x0100 /* Suspend */ 87 #define IEE_SCB_CUS_ACT 0x0200 /* Active */ 88 #define IEE_SCB_CUS 0x0700 /* CU status bit mask */ 89 90 #define IEE_SCB_RUS_IDL 0x0000 /* Idle */ 91 #define IEE_SCB_RUS_SUS 0x0010 /* Suspend */ 92 #define IEE_SCB_RUS_NR1 0x0020 /* No Resources (RFDs and / or RBDs) */ 93 #define IEE_SCB_RUS_RDY 0x0040 /* Ready */ 94 #define IEE_SCB_RUS_NR2 0x00a0 /* No Resources (no RBDs) */ 95 #define IEE_SCB_RUS_NR3 0x00c0 /* No more RBDs */ 96 #define IEE_SCB_RUS 0x00f0 /* RU status bit mask */ 97 98 #define IEE_SCB_T 0x0008 /* Bus Throttle timers loaded */ 99 100 #define IEE_SCB_TON 0x0000ffff /* Bus Throttle TON mask */ 101 #define IEE_SCB_TOFF 0xffff0000 /* Bus Throttle TOFF mask */ 102 103 /* Bits in the Command Block Command word. */ 104 #define IEE_CB_EL 0x8000 /* End of List, cmd is last on CBL */ 105 #define IEE_CB_S 0x4000 /* Suspend after exec of this CB */ 106 #define IEE_CB_I 0x2000 /* generate Interrupt after exec */ 107 #define IEE_CB_NC 0x0010 /* No CRC insertion disable */ 108 #define IEE_CB_SF 0x0008 /* Flexible Mode, data in TCB and TBD */ 109 110 /* Bits in the Command Block Status word. */ 111 #define IEE_CB_C 0x8000 /* Command is executed */ 112 #define IEE_CB_B 0x4000 /* Command running or fetching CB */ 113 #define IEE_CB_OK 0x2000 /* Command finished without error */ 114 #define IEE_CB_A 0x1000 /* CU Abort control cmd was issued */ 115 #define IEE_CB_F 0x0800 /* self test failed */ 116 #define IEE_CB_EOF 0x8000 /* End Of Frame */ 117 #define IEE_CB_STAT 0xf800 /* Status bit mask */ 118 #define IEE_CB_COL 0x0020 /* TX stopped because of to much collisions */ 119 #define IEE_CB_MAXCOL 0x000f /* Number of Collisions mask */ 120 /* Commands */ 121 #define IEE_CB_CMD_NOP 0x0000 /* NOP */ 122 #define IEE_CB_CMD_IAS 0x0001 /* Individual Address Setup */ 123 #define IEE_CB_CMD_CONF 0x0002 /* Configure */ 124 #define IEE_CB_CMD_MCS 0x0003 /* Multicast Setup */ 125 #define IEE_CB_CMD_TR 0x0004 /* Transmit */ 126 #define IEE_CB_CMD_TDR 0x0005 /* Time Domain Reflectometry */ 127 #define IEE_CB_CMD_DUMP 0x0006 /* Dump */ 128 #define IEE_CB_CMD_DIAG 0x0007 /* Diagnose */ 129 #define IEE_CB_CMD 0x0007 /* CMD bit mask */ 130 131 /* Receive Frame Descriptor bits */ 132 #define IEE_RFD_EL 0x8000 /* End of List, RFD is last on list */ 133 #define IEE_RFD_S 0x4000 /* Suspend after this RFD is filled */ 134 #define IEE_RFD_SF 0x0008 /* Flexible Mode, data in RFD and RBD */ 135 #define IEE_RFD_C 0x8000 /* Frame reception has completed */ 136 #define IEE_RFD_B 0x4000 /* i82596 is busy on this RFD */ 137 #define IEE_RFD_OK 0x2000 /* Frame received without error */ 138 #define IEE_RFD_STAT 0x1fff /* Status bits */ 139 #define IEE_RFD_STAT_LEN 0x1000 /* Length error */ 140 #define IEE_RFD_STAT_CRC 0x0800 /* CRC error */ 141 #define IEE_RFD_STAT_ALIGN 0x0400 /* Alignment error */ 142 #define IEE_RFD_STAT_NORES 0x0200 /* Ran out of buffer space */ 143 #define IEE_RFD_STAT_DMA 0x0100 /* DMA Overrun */ 144 #define IEE_RFD_STAT_SHORT 0x0080 /* Frame to short */ 145 #define IEE_RFD_STAT_NOEOP 0x0040 /* No EOP Flag */ 146 #define IEE_RFD_STAT_TRUNC 0x0020 /* Frame was truncated */ 147 #define IEE_RFD_STAT_IA 0x0002 /* Frame doesn't match Individ. Addr. */ 148 #define IEE_RFD_STAT_COLL 0x0001 /* Receive Collision */ 149 #define IEE_RFD_EOF 0x8000 /* this is last buffer on list */ 150 #define IEE_RFD_F 0x4000 /* buffer has already been used */ 151 #define IEE_RFD_COUNT 0xc000 /* count mask */ 152 153 /* Receive Buffer Descriptor bits */ 154 #define IEE_RBD_EOF 0x8000 /* last buffer related to frame */ 155 #define IEE_RBD_F 0x4000 /* buffer has already been used */ 156 #define IEE_RBD_EL 0x8000 /* this is last buffer on list */ 157 #define IEE_RBD_P 0x4000 /* this buffer is already prefetched */ 158 #define IEE_RBD_COUNT 0x3fff /* count mask */ 159 160 /* Bits in Configure Bytes */ 161 #define IEE_CF_0_CNT(x) ((x) & 0x0f) /* Count of CF Bytes */ 162 #define IEE_CF_0_CNT_DEF 0x0e /* 14 Bytes is the default */ 163 #define IEE_CF_0_CNT_M 0x0f /* Mask */ 164 #define IEE_CF_0_PREF 0x80 /* Write Prefetched bit */ 165 #define IEE_CF_0_DEF 0x0e /* Configuration Byte 0 Default Value */ 166 167 #define IEE_CF_1_FIFO(x) ((x) & 0x0f) /* FIFO Limit */ 168 #define IEE_CF_1_FIFO_DEF 0x08 /* FIFO Default Value */ 169 #define IEE_CF_1_MON2 (((x) & 0x3) << 6) /* Monitor Bits */ 170 #define IEE_CF_1_MON_DEF 0xc0 /* Monitor Bits Default */ 171 #define IEE_CF_1_DEF 0xc8 /* Configuration Byte 1 Default Value */ 172 173 #define IEE_CF_2_SAVBF 0x02 /* Save Bad frames */ 174 #define IEE_CF_2_RESUM 0x80 /* Resume next CB */ 175 #define IEE_CF_2_DEF 0x40 /* Configuration Byte 2 Default Value */ 176 #define IEE_CF_2_STD 0x40 /* Configuration Byte 2 Standard Val. */ 177 178 #define IEE_CF_3_ADDRLEN(x) ((x) & 0x07) /* Address Length */ 179 #define IEE_CF_3_ADDRLEN_DEF 0x06 /* Address Length Default */ 180 #define IEE_CF_3_NSAI 0x08 /* No Source Address Insertion */ 181 #define IEE_CF_3_ALLOC 0x08 /* == AL_LOC */ 182 #define IEE_CF_3_PREAMLEN(x) (((x) & 0x3) << 4) /* Preamble Length */ 183 #define IEE_CF_3_PREAMLEN_DEF 0x20 /* */ 184 #define IEE_CF_3_LOOPBK(x) (((x) & 0x3) << 6) /* Loopback Mode */ 185 #define IEE_CF_3_LOOPBK_DEF 0x00 /* */ 186 #define IEE_CF_3_DEF 0x26 /* Configuration Byte 3 Default Value */ 187 188 #define IEE_CF_4_LINPRIO(x) ((x) & 0x07) /* Linear Priority */ 189 #define IEE_CF_4_LINPRIO_DEF 0x00 /* Linear Priority */ 190 #define IEE_CF_4_EXPPRIO(x) (((x) & 0x07) << 4) /* Exponential Prio. */ 191 #define IEE_CF_4_EXPPRIO_DEF 0x00 /* Exponential Prio. */ 192 #define IEE_CF_4_BOFMETD 0x80 /* Exponential Backoff Method */ 193 #define IEE_CF_4_DEF 0x00 /* Configuration Byte 4 Default Value */ 194 195 #define IEE_CF_5_IFSP(x) ((x) & 0xff) /* Inter Frame Spacing */ 196 #define IEE_CF_5_IFSP_DEF 0x60 /* */ 197 #define IEE_CF_5_DEF 0x60 /* Configuration Byte 5 Default Value */ 198 199 #define IEE_CF_6_SLOT_TL(x) ((x) & 0xff) /* Slot Time Low */ 200 #define IEE_CF_6_SLOT_TL_DEF 0x00 /* */ 201 #define IEE_CF_6_DEF 0x00 /* Configuration Byte 6 Default Value */ 202 203 #define IEE_CF_7_SLOT_TH(x) ((x) & 0x0f) /* Slot Time High */ 204 #define IEE_CF_7_SLOT_TH_DEF 0x02 /* */ 205 #define IEE_CF_7_RETR(x) (((x) & 0x0f) << 4) /* Num Retrans Retry */ 206 #define IEE_CF_7_RETR_DEF 0xf0 /* */ 207 #define IEE_CF_7_DEF 0xf2 /* Configuration Byte 7 Default Value */ 208 209 #define IEE_CF_8_PRM 0x01 /* Promiscuous Mode */ 210 #define IEE_CF_8_BCDIS 0x02 /* Bradcast Disable */ 211 #define IEE_CF_8_MANCH 0x04 /* Manchester encoding */ 212 #define IEE_CF_8_TONO 0x08 /* Transmit on no CRS */ 213 #define IEE_CF_8_NOCRCINS 0x10 /* No CRC Insertion */ 214 #define IEE_CF_8_CRC16 0x20 /* CRC16 */ 215 #define IEE_CF_8_BITSTF 0x40 /* Bit Stuffing */ 216 #define IEE_CF_8_PAD 0x80 /* Padding */ 217 #define IEE_CF_8_DEF 0x00 /* Configuration Byte 8 Default Value */ 218 219 #define IEE_CF_9_CRSF(x) ((x) & 0x07) /* Carrier Sense Filter Len */ 220 #define IEE_CF_9_CRSF_DEF 0x00 /* */ 221 #define IEE_CF_9_CRSSRC 0x08 /* Carrier Sense Source */ 222 #define IEE_CF_9_CDTF(x) (((x) & 0x07) << 4)/* Carrier Detect Filt Len */ 223 #define IEE_CF_9_CDTF_DEF 0x00 /* */ 224 #define IEE_CF_9_CDTSRC 0x80 /* Carrier Detect Source */ 225 #define IEE_CF_9_DEF 0x00 /* Configuration Byte 9 Default Value */ 226 227 #define IEE_CF_10_MINFRMLEN(x) ((x) & 0xff) /* Minimum Frame Length */ 228 #define IEE_CF_10_DEF 0x40 /* Configuration Byte 10 Default Val. */ 229 230 #define IEE_CF_11_PRECRS 0x01 /* Preamble until Carrier Sense */ 231 #define IEE_CF_11_LNGFLD 0x02 /* Length field. Enable padding */ 232 #define IEE_CF_11_CRCINM 0x04 /* Rx CRC appended to the frame in MEM*/ 233 #define IEE_CF_11_AUTOTX 0x08 /* Auto Retransmit when Coll in Preamb*/ 234 #define IEE_CF_11_CDBSAC 0x10 /* Coll Detect by source Addr Recogn */ 235 #define IEE_CF_11_MCALL 0x20 /* Enable to receive all MC Frames */ 236 #define IEE_CF_11_MON(x) (((x) & 0x03) << 6) /* Receive Monitor Bits */ 237 #define IEE_CF_11_MON_DEF 0xc0 /* */ 238 #define IEE_CF_11_DEF 0xff /* Configuration Byte 11 Default Val. */ 239 240 #define IEE_CF_12_FDX 0x40 /* Enable Full Duplex */ 241 #define IEE_CF_12_DEF 0x00 /* Configuration Byte 12 Default Val. */ 242 243 #define IEE_CF_13_MULTIA 0x40 /* Multiple Individual Address */ 244 #define IEE_CF_13_DISBOF 0x80 /* Disable the Backoff Algorithm */ 245 #define IEE_CF_13_DEF 0x3f /* Configuration Byte 13 Default Val. */ 246 247
Indexes created Tue Sep 23 14:10:03 GMT 2025