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      1 /*	$NetBSD: ifpgamem.h,v 1.2 2013/02/19 10:57:10 skrll Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2001 ARM Ltd
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. The name of the company may not be used to endorse or promote
     16  *    products derived from this software without specific prior written
     17  *    permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     20  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     21  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     22  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     23  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29  * SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Physical memory map provided by the integrator FPGA
     34  */
     35 
     36 #define	IFPGA_SDRAM_BASE		0x00000000
     37 #define IFPGA_SDRAM_SIZE		0x10000000	/* 256 MB */
     38 
     39 #define	IFPGA_SSRAM_BASE		0x00000000	/* Overlaps SDRAM */
     40 #define IFPGA_SSRAM_SIZE		0x00040000	/* 256 KB */
     41 
     42 #define IFPGA_IO_BASE			0x10000000
     43 #define IFPGA_IO_SIZE			0x10000000	/* 256 KB */
     44 
     45 #define IFPGA_IO_CM_BASE		0x00000000	/* Core module regs */
     46 #define IFPGA_IO_CM_SIZE		0x00000200
     47 
     48 #define IFPGA_IO_SC_BASE		0x01000000	/* System Ctrl regs */
     49 #define IFPGA_IO_SC_SIZE		0x00000028
     50 
     51 #define IFPGA_IO_TMR_BASE		0x03000000	/* Countr/timr regs */
     52 #define IFPGA_IO_TMR_SIZE		0x00000210
     53 
     54 #define IFPGA_IO_IRQ_BASE		0x04000000	/* IRQ controller */
     55 #define IFPGA_IO_IRQ_SIZE		0x00000100
     56 
     57 #define IFPGA_TIMER0_BASE		0x00000000
     58 #define IFPGA_TIMER1_BASE		0x00000100
     59 #define IFPGA_TIMER2_BASE		0x00000200
     60 
     61 #define IFPGA_TIMER0_IRQ		5
     62 #define IFPGA_TIMER1_IRQ		6
     63 #define IFPGA_TIMER2_IRQ		7
     64 
     65 #if defined(INTEGRATOR_CP)
     66 #define IFPGA_TIMER1_FREQ		1000000		/* 1 MHz */
     67 #define IFPGA_TIMER2_FREQ		1000000		/* 1 MHz */
     68 #else
     69 #define IFPGA_TIMER1_FREQ		24000000	/* 24 MHz */
     70 #define IFPGA_TIMER2_FREQ		24000000	/* 24 MHz */
     71 #endif
     72 
     73 #define IFPGA_EBI_ROM_BASE		0x20000000
     74 #define IFPGA_EBI_ROM_SIZE		0x04000000	/* 64MB */
     75 
     76 #define IFPGA_EBI_FLASH_BASE		0x24000000
     77 #define IFPGA_EBI_FLASH_SIZE		0x04000000	/* 64MB */
     78 
     79 #define IFPGA_EBI_SSRAM_BASE		0x28000000
     80 #define IFPGA_EBI_SSRAM_SIZE		0x04000000	/* 64MB */
     81 
     82 #define IFPGA_PCI_BASE			0x40000000	/* Base of entire PCI
     83 							   subsystem.  */
     84 
     85 #define IFPGA_PCI_APP0_BASE		0x40000000
     86 #define IFPGA_PCI_APP0_SIZE		0x10000000	/* 256MB */
     87 
     88 #define IFPGA_PCI_APP1_BASE		0x50000000
     89 #define IFPGA_PCI_APP1_SIZE		0x10000000	/* 256MB */
     90 
     91 #define IFPGA_PCI_IO_BASE		0x60000000	/* Absolute */
     92 #define IFPGA_PCI_IO_VBASE		0xfe000000
     93 #define IFPGA_PCI_IO_VSIZE		0x01000000	/* 16MB */
     94 
     95 #define IFPGA_PCI_CONF_BASE		0x61000000	/* Absolute */
     96 #define IFPGA_PCI_CONF_VBASE		0xff000000
     97 #define IFPGA_PCI_CONF_VSIZE		0x01000000      /* 16MB */
     98 
     99 #define IFPGA_V360_REG_BASE		0x62000000
    100 #define IFPGA_V360_REG_SIZE		0x00010000	/* 64K */
    101 
    102 /* Core module alias memory.  */
    103 #define IFPGA_CM_ALIAS_BASE		0x80000000
    104 
    105 /* Logic module memory.  */
    106 #define IFPGA_LM_BASE			0xc0000000
    107 
    108