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      1 /*	$NetBSD: ifpgareg.h,v 1.7 2015/01/27 16:34:34 jmcneill Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2001 ARM Ltd
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. The name of the company may not be used to endorse or promote
     16  *    products derived from this software without specific prior written
     17  *    permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     20  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     21  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     22  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     23  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29  * SUCH DAMAGE.
     30  */
     31 
     32 /* System clock defaults. */
     33 
     34 #define IFPGA_UART_CLK			14745600 /* Uart REFCLK freq */
     35 #define IFPGA_UART_SIZE			0x24
     36 
     37 #define IFPGA_MMC_CLK			14745600 /* MMC_5 freq */
     38 #define IFPGA_MMC_SIZE			0x1000
     39 
     40 /*
     41  * IFPGA registers
     42  */
     43 
     44 /* Core module */
     45 #define IFPGA_CM_ID			0x00000000	/* ID register */
     46 #define IFPGA_CM_PROC			0x00000004	/* Processor Reg */
     47 #define IFPGA_CM_OSC			0x00000008	/* Oscillator ctrl */
     48 #define IFPGA_CM_CTRL			0x0000000c	/* Control Reg */
     49 #define IFPGA_CM_STAT			0x00000010	/* Status Reg */
     50 #define IFPGA_CM_LOCK			0x00000014	/* Lock */
     51 #define IFPGA_CM_SDRAM			0x00000020	/* SDRAM stat/ctrl */
     52 #define IFPGA_CM_IRQ_STAT		0x00000040	/* IRQ Status */
     53 #define IFPGA_CM_IRQ_RSTAT		0x00000044	/* IRQ Raw status */
     54 #define IFPGA_CM_IRQ_ENSET		0x00000048	/* IRQ Enable set */
     55 #define IFPGA_CM_IRQ_ENCLR		0x0000004c	/* IRQ Enable clr */
     56 #define IFPGA_CM_SOFT_INTSET		0x00000050	/* S/W Int set */
     57 #define IFPGA_CM_SOFT_INTCLR		0x00000054	/* S/W Int clr */
     58 #define IFPGA_CM_FIQ_STAT		0x00000060	/* FIQ Status */
     59 #define IFPGA_CM_FIQ_RSTAT		0x00000064	/* FIQ Raw Status */
     60 #define IFPGA_CM_FIQ_ENSET		0x00000068	/* FIQ Enable set */
     61 #define IFPGA_CM_FIQ_ENCLR		0x0000006c	/* FIQ Enable clr */
     62 #define IFPGA_CM_SPD			0x00000100	/* SDRAM SPD memory */
     63 
     64 	/* CM-ARM10200 module only */
     65 #define IFPGA_CM_LMBUSCNT		0x00000018	/* LMBUS counter */
     66 #define IFPGA_CM_AUXOSC			0x0000001c	/* Aux Oscillator */
     67 #define IFPGA_CM_INIT			0x00000024	/* Initialization */
     68 #define IFPGA_CM_REFCNT			0x00000028	/* 24MHz counter */
     69 #define IFPGA_CM_FLAGS			0x00000030	/* Flags reg ? */
     70 #define IFPGA_CM_FLAGSS			0x00000030	/* Flags set */
     71 #define IFPGA_CM_FLAGSC			0x00000034	/* Flags clr */
     72 #define IFPGA_CM_NVFLAGS		0x00000038	/* NVFlags reg ? */
     73 #define IFPGA_CM_NVFLAGSS		0x00000038	/* NVFlags set */
     74 #define IFPGA_CM_NVFLAGSC		0x0000003c	/* NVFlags clr */
     75 
     76 /* CM_ID reg */
     77 #define IFPGA_CM_ID_MAN_MASK		0xff000000	/* Manufacturer ID */
     78 #define IFPGA_CM_ID_MAN_ARM		0x41000000	/* ARM Ltd */
     79 #define IFPGA_CM_ID_ARCH_MASK		0x00ff0000	/* Architecture */
     80 #define IFPGA_CM_ID_ARCH_ASBLE		0x00000000	/* ASB Little-endian */
     81 #define IFPGA_CM_ID_ARCH_AHBLE		0x00010000	/* AHB Little-endian */
     82 #define IFPGA_CM_ID_FPGA_MASK		0x0000f000	/* FPGA type */
     83 #define IFPGA_CM_ID_FPGA_XC4036		0x00000000	/* XC4036 */
     84 #define IFPGA_CM_ID_FPGA_XCV600		0x00003000	/* XCV600 */
     85 #define IFPGA_CM_ID_BUILD_MASK		0x00000ff0	/* Build number */
     86 #define IFPGA_CM_ID_BUILD_SHIFT		4
     87 #define IFPGA_CM_ID_REV_MASK		0x0000000f	/* Revision number */
     88 #define IFPGA_CM_ID_REV_A		0x00000000	/* Revision A */
     89 #define IFPGA_CM_ID_REV_B		0x00000001	/* Revision B */
     90 
     91 /* System controller */
     92 #define IFPGA_SC_ID			0x00000000	/* ID register */
     93 #define IFPGA_SC_OSC			0x00000004	/* Oscillator ctrl */
     94 #define IFPGA_SC_CTRLS			0x00000008	/* Ctrl Regs Set */
     95 #define IFPGA_SC_CTRLC			0x0000000c	/* Ctrl Regs Clr */
     96 #define IFPGA_SC_DEC			0x00000010	/* Decoder status */
     97 #define IFPGA_SC_ARB			0x00000014	/* Arbiter time-out */
     98 #define IFPGA_SC_PCI			0x00000018	/* PIC Ctrl */
     99 #define IFPGA_SC_LOCK			0x0000001c	/* Lock */
    100 #define IFPGA_SC_LBFADDR		0x00000020	/* PCI Lbus flt addr */
    101 #define IFPGA_SC_LBFCODE		0x00000024	/* PCI Lbus flt code */
    102 
    103 /* SC_ID reg */
    104 #define IFPGA_SC_ID_MAN_MASK		0xff000000	/* Manufacturer ID */
    105 #define IFPGA_SC_ID_MAN_ARM		0x41000000	/* ARM Ltd */
    106 #define IFPGA_SC_ID_ARCH_MASK		0x00ff0000	/* Architecture */
    107 #define IFPGA_SC_ID_ARCH_ASBLE		0x00000000	/* ASB Little-endian */
    108 #define IFPGA_SC_ID_ARCH_AHBLE		0x00010000	/* AHB Little-endian */
    109 #define IFPGA_SC_ID_FPGA_MASK		0x0000f000	/* FPGA type */
    110 #define IFPGA_SC_ID_FPGA_XC4062		0x00001000	/* XC4062 */
    111 #define IFPGA_SC_ID_FPGA_XC4085		0x00002000	/* XC4085 */
    112 #define IFPGA_SC_ID_BUILD_MASK		0x00000ff0	/* Build number */
    113 #define IFPGA_SC_ID_BUILD_SHIFT		4
    114 #define IFPGA_SC_ID_REV_MASK		0x0000000f	/* Revision number */
    115 #define IFPGA_SC_ID_REV_A		0x00000000	/* Revision A */
    116 #define IFPGA_SC_ID_REV_B		0x00000001	/* Revision B */
    117 
    118 /* SC_OSC reg */
    119 #define IFPGA_SC_OSC_DIV_X_Y		0x80
    120 #define IFPGA_SC_OSC_S_VDW		0x7f
    121 
    122 /* SC_CTRLS & SC_CTRLC regs */
    123 #define IFPGA_SC_CTRL_UART0RTS		0x80		/* Active low */
    124 #define IFPGA_SC_CTRL_UART0DTR		0x40		/* Active low */
    125 #define IFPGA_SC_CTRL_UART1RTS		0x20		/* Active low */
    126 #define IFPGA_SC_CTRL_UART1DTR		0x10		/* Active low */
    127 #define IFPGA_SC_CTRL_FLASHWP		0x04		/* W/P Flash */
    128 #define IFPGA_SC_CTRL_FLASHVPP		0x02		/* Flash VPP enable */
    129 #define IFPGA_SC_CTRL_SOFTRESET		0x01		/* Board reset */
    130 
    131 /* SC_DEC reg (read-only) */
    132 #define IFPGA_SC_DEC_EXP_MASK		0xf0		/* EXP connector */
    133 #define IFPGA_SC_DEC_EXP_SHIFT		4
    134 #define IFPGA_SC_DEC_HDR_MASK		0x0f		/* HDR connector */
    135 #define IFPGA_SC_DEC_HDR_SHIFT		0
    136 
    137 /* SC_ARB reg */
    138 #define IFPGA_SC_ARB_CCOUNT_MASK	0xffffff00	/* Cycle counter */
    139 #define IFPGA_SC_ARB_CCOUNT_SHIFT	8
    140 #define IFPGA_SC_ARB_TCOUNT_MASK	0xffffff00	/* Transaction cntr */
    141 #define IFPGA_SC_ARB_TCOUNT_SHIFT	0
    142 
    143 /* SC_PCI reg */
    144 #define IFPGA_SC_PCI_PCIEN		0x02		/* PCI Enable */
    145 #define IFPGA_SC_PCI_LBINT_CLR		0x01		/* LB interrupt clr */
    146 
    147 /* SC_LOCK reg */
    148 #define IFPGA_SC_LOCK_LCK		0x00010000	/* Is locked */
    149 #define IFPGA_SC_LOCK_MASK		0x0000ffff	/* Key */
    150 #define IFPGA_SC_LOCK_KEY		0x0000a05f	/* Key */
    151 
    152 /* SC_LBFADDR reg */
    153 
    154 /* SC_LBFCODE reg */
    155 #define IFPGA_SC_LBFCODE_BEN3		0x80		/* Byte enable 3 */
    156 #define IFPGA_SC_LBFCODE_BEN2		0x40		/* Byte enable 2 */
    157 #define IFPGA_SC_LBFCODE_BEN1		0x20		/* Byte enable 1 */
    158 #define IFPGA_SC_LBFCODE_BEN0		0x10		/* Byte enable 0 */
    159 #define IFPGA_SC_LBFCODE_LBURST		0x08		/* Burst */
    160 #define IFPGA_SC_LBFCODE_LREAD		0x04		/* Read */
    161 #define IFPGA_SC_LBFCODE_MASTER		0x02		/* Master */
    162 #define IFPGA_SC_LBFCODE_RLBFINT	0x01		/* Raw LBNT */
    163 
    164 /* Counter/Timer registers */
    165 
    166 #define TIMERx_LOAD			0x00	/* Load register */
    167 #define TIMERx_VALUE			0x04	/* Current value */
    168 #define TIMERx_CTRL			0x08	/* Control */
    169 #define TIMERx_CLR			0x0c	/* Clear */
    170 
    171 #define TIMERx_MAX			0xffff	/* Max count value */
    172 
    173 #define TIMERx_CTRL_ENABLE		0x80	/* Timer enable */
    174 #define TIMERx_CTRL_RAISE_IRQ		0x20	/* Raise IRQ on tick */
    175 #define TIMERx_CTRL_MODE_ONCE		0x00	/* Single shot */
    176 #define TIMERx_CTRL_MODE_PERIODIC	0x40	/* Single shot */
    177 #define TIMERx_CTRL_PRESCALE_DIV1	0x00	/* CLK / 1 */
    178 #define TIMERx_CTRL_PRESCALE_DIV16	0x04	/* CLK / 16 */
    179 #define TIMERx_CTRL_PRESCALE_DIV256	0x08	/* CLK / 256 */
    180 
    181 /* Interrupt registers */
    182 /* Bit positions...  */
    183 #define IFPGA_INTR_bit31		0x80000000
    184 #define IFPGA_INTR_bit30		0x40000000
    185 #define IFPGA_INTR_bit29		0x20000000
    186 #define IFPGA_INTR_bit28		0x10000000
    187 #define IFPGA_INTR_bit27		0x08000000
    188 #define IFPGA_INTR_bit26		0x04000000
    189 #define IFPGA_INTR_bit25		0x02000000
    190 #define IFPGA_INTR_bit24		0x01000000
    191 #define IFPGA_INTR_bit23		0x00800000
    192 #define IFPGA_INTR_bit22		0x00400000
    193 
    194 #define IFPGA_INTR_APCINT		0x00200000
    195 #define IFPGA_INTR_PCILBINT		0x00100000
    196 #define IFPGA_INTR_ENUMINT		0x00080000
    197 #define IFPGA_INTR_DEGINT		0x00040000
    198 #define IFPGA_INTR_LINT			0x00020000
    199 #define IFPGA_INTR_PCIINT3		0x00010000
    200 #define IFPGA_INTR_PCIINT2		0x00008000
    201 #define IFPGA_INTR_PCIINT1		0x00004000
    202 #define IFPGA_INTR_PCIINT0		0x00002000
    203 #define IFPGA_INTR_EXPINT3		0x00001000
    204 #define IFPGA_INTR_EXPINT2		0x00000800
    205 #define IFPGA_INTR_EXPINT1		0x00000400
    206 #define IFPGA_INTR_EXPINT0		0x00000200
    207 #define IFPGA_INTR_RTCINT		0x00000100
    208 #define IFPGA_INTR_TIMERINT2		0x00000080
    209 #define IFPGA_INTR_TIMERINT1		0x00000040
    210 #define IFPGA_INTR_TIMERINT0		0x00000020
    211 #define IFPGA_INTR_MOUSEINT		0x00000010
    212 #define IFPGA_INTR_KBDINT		0x00000008
    213 #define IFPGA_INTR_UARTINT1		0x00000004
    214 #define IFPGA_INTR_UARTINT0		0x00000002
    215 #define IFPGA_INTR_SOFTINT		0x00000001
    216 
    217 #if defined(INTEGRATOR_CP)
    218 #define IFPGA_INTR_HWMASK		0x08bfffff
    219 #else
    220 #define IFPGA_INTR_HWMASK		0x003fffff
    221 #endif
    222 
    223 /* ... and the corresponding numbers.  */
    224 #define IFPGA_INTRNUM_APCINT		21
    225 #define IFPGA_INTRNUM_PCILBINT		20
    226 #define IFPGA_INTRNUM_ENUMINT		19
    227 #define IFPGA_INTRNUM_DEGINT		18
    228 #define IFPGA_INTRNUM_LINT		17
    229 #define IFPGA_INTRNUM_PCIINT3		16
    230 #define IFPGA_INTRNUM_PCIINT2		15
    231 #define IFPGA_INTRNUM_PCIINT1		14
    232 #define IFPGA_INTRNUM_PCIINT0		13
    233 #define IFPGA_INTRNUM_EXPINT3		12
    234 #define IFPGA_INTRNUM_EXPINT2		11
    235 #define IFPGA_INTRNUM_EXPINT1		10
    236 #define IFPGA_INTRNUM_EXPINT0		9
    237 #define IFPGA_INTRNUM_RTCINT		8
    238 #define IFPGA_INTRNUM_TIMERINT2		7
    239 #define IFPGA_INTRNUM_TIMERINT1		6
    240 #define IFPGA_INTRNUM_TIMERINT0		5
    241 #define IFPGA_INTRNUM_MOUSEINT		4
    242 #define IFPGA_INTRNUM_KBDINT		3
    243 #define IFPGA_INTRNUM_UARTINT1		2
    244 #define IFPGA_INTRNUM_UARTINT0		1
    245 #define IFPGA_INTRNUM_SOFTINT		0
    246 
    247 #define IFPGA_INTR_STATUS		0x0	/* Offset to status reg */
    248 #define IFPGA_INTR_RAWSTAT		0x4	/* Offset to raw reg */
    249 #define IFPGA_INTR_ENABLESET		0x8	/* Offset to Enable-Set */
    250 #define IFPGA_INTR_ENABLECLR		0xc	/* Offset to Enable-Clear */
    251 
    252 #define IFPGA_IRQ0			0x00
    253 #define IFPGA_IRQ1			0x40
    254 #define IFPGA_IRQ2			0x80
    255 #define IFPGA_IRQ3			0xc0
    256 #define IFPGA_FIQ0			0x20
    257 #define IFPGA_FIQ1			0x60
    258 #define IFPGA_FIQ2			0xa0
    259 #define IFPGA_FIQ3			0xe0
    260 
    261 /* Peripheral registers */
    262 
    263 /* Real time clock */
    264 
    265 #define IFPGA_RTC_DR			0x00
    266 #define IFPGA_RTC_MR			0x04
    267 #define IFPGA_RTC_STAT			0x08
    268 #define IFPGA_RTC_EOI			0x08
    269 #define IFPGA_RTC_LR			0x0c
    270 #define IFPGA_RTC_CR			0x10
    271 
    272 #define IFPGA_RTC_STAT_INT		1
    273 
    274 #define IFPGA_RTC_CR_MIE		1	/* Match interrupt enable */
    275 
    276