1 /* $NetBSD: igpioreg.h,v 1.8 2023/01/07 11:15:00 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2021 Emmanuel Dreyfus 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _IGPIOREG_H 30 #define _IGPIOREG_H 31 32 #define IGPIO_REVID 0x0000 33 #define IGPIO_CAPLIST 0x0004 34 #define IGPIO_PADBAR 0x000c 35 36 #define IGPIO_PADCFG0 0x0000 37 38 #define IGPIO_PADCFG0_RXEVCFG_SHIFT 25 39 #define IGPIO_PADCFG0_RXEVCFG_MASK __BITS(26, 25) 40 #define IGPIO_PADCFG0_RXEVCFG_LEVEL 0 41 #define IGPIO_PADCFG0_RXEVCFG_EDGE 1 42 #define IGPIO_PADCFG0_RXEVCFG_DISABLED 2 43 #define IGPIO_PADCFG0_RXEVCFG_EDGE_BOTH 3 44 #define IGPIO_PADCFG0_PREGFRXSEL __BIT(24) 45 #define IGPIO_PADCFG0_RXINV __BIT(23) 46 #define IGPIO_PADCFG0_GPIROUTIOXAPIC __BIT(20) 47 #define IGPIO_PADCFG0_GPIROUTSCI __BIT(19) 48 #define IGPIO_PADCFG0_GPIROUTSMI __BIT(18) 49 #define IGPIO_PADCFG0_GPIROUTNMI __BIT(17) 50 #define IGPIO_PADCFG0_PMODE_SHIFT 10 51 #define IGPIO_PADCFG0_PMODE_MASK __BITS(13, 10) 52 #define IGPIO_PADCFG0_PMODE_GPIO 0 53 #define IGPIO_PADCFG0_GPIORXDIS __BIT(9) 54 #define IGPIO_PADCFG0_GPIOTXDIS __BIT(8) 55 #define IGPIO_PADCFG0_GPIORXSTATE __BIT(1) 56 #define IGPIO_PADCFG0_GPIOTXSTATE __BIT(0) 57 58 #define IGPIO_PADCFG1 0x0004 59 #define IGPIO_PADCFG1_TERM_UP __BIT(13) 60 #define IGPIO_PADCFG1_TERM_SHIFT 10 61 #define IGPIO_PADCFG1_TERM_MASK __BITS(12, 10) 62 #define IGPIO_PADCFG1_TERM_20K __BIT(2) 63 #define IGPIO_PADCFG1_TERM_5K __BIT(1) 64 #define IGPIO_PADCFG1_TERM_1K __BIT(0) 65 #define IGPIO_PADCFG1_TERM_833 (__BIT(1) | BIT(0)) 66 67 #define IGPIO_CAPLIST_ID_GPIO_HW_INFO 1 68 #define IGPIO_CAPLIST_ID_PWM 2 69 #define IGPIO_CAPLIST_ID_BLINK 3 70 #define IGPIO_CAPLIST_ID_EXP 4 71 72 73 #define IGPIO_PINCTRL_FEATURE_DEBOUNCE 0x001 74 #define IGPIO_PINCTRL_FEATURE_1K_PD 0x002 75 #define IGPIO_PINCTRL_FEATURE_GPIO_HW_INFO 0x004 76 #define IGPIO_PINCTRL_FEATURE_PWM 0x010 77 #define IGPIO_PINCTRL_FEATURE_BLINK 0x020 78 #define IGPIO_PINCTRL_FEATURE_EXP 0x040 79 80 struct igpio_bank_setup { 81 const char *ibs_acpi_hid; 82 int ibs_barno; 83 int ibs_first_pin; 84 int ibs_last_pin; 85 int ibs_gpi_is; /* Interrupt Status */ 86 int ibs_gpi_ie; /* Interrupt Enable */ 87 }; 88 89 struct igpio_pin_group { 90 const char *ipg_acpi_hid; 91 int ipg_groupno; 92 int ipg_first_pin; 93 const char *ipg_name; 94 }; 95 96 struct igpio_bank_setup igpio_bank_setup[] = { 97 /* Sunrisepoint-LP */ 98 { "INT344B", 0, 0, 47, 0x100, 0x120 }, 99 { "INT344B", 1, 48, 119, 0x100, 0x120 }, 100 { "INT344B", 2, 120, 151, 0x100, 0x120 }, 101 102 /* Coffee Lake-S (Same as Sunrisepoint-H(INT345D)) */ 103 { "INT3451", 0, 0, 47, 0x100, 0x120 }, 104 { "INT3451", 1, 48, 180, 0x100, 0x120 }, 105 { "INT3451", 2, 181, 191, 0x100, 0x120 }, 106 107 /* Sunrisepoint-H */ 108 { "INT345D", 0, 0, 47, 0x100, 0x120 }, 109 { "INT345D", 1, 48, 180, 0x100, 0x120 }, 110 { "INT345D", 2, 181, 191, 0x100, 0x120 }, 111 112 /* Baytrail XXX GPI_IS and GPI_IE */ 113 { "INT33B2", 0, 0, 101, 0x000, 0x000 }, 114 { "INT33FC", 0, 0, 101, 0x000, 0x000 }, 115 116 /* Lynxpoint XXX GPI_IS and GPI_IE */ 117 { "INT33C7", 0, 0, 94, 0x000, 0x000 }, 118 { "INT3437", 0, 0, 94, 0x000, 0x000 }, 119 120 /* Cannon Lake-H */ 121 { "INT3450", 0, 0, 50, 0x100, 0x120 }, 122 { "INT3450", 1, 51, 154, 0x100, 0x120 }, 123 { "INT3450", 2, 155, 248, 0x100, 0x120 }, 124 { "INT3450", 3, 249, 298, 0x100, 0x120 }, 125 126 /* Cannon Lake-LP */ 127 { "INT34BB", 0, 0, 67, 0x100, 0x120 }, 128 { "INT34BB", 1, 68, 180, 0x100, 0x120 }, 129 { "INT34BB", 2, 181, 243, 0x100, 0x120 }, 130 131 /* Ice Lake-LP */ 132 { "INT3455", 0, 0, 58, 0x100, 0x110 }, 133 { "INT3455", 1, 59, 152, 0x100, 0x110 }, 134 { "INT3455", 2, 153, 215, 0x100, 0x110 }, 135 { "INT3455", 3, 216, 240, 0x100, 0x110 }, 136 137 /* Ice Lake-N */ 138 { "INT34C3", 0, 0, 71, 0x100, 0x120 }, 139 { "INT34C3", 1, 72, 174, 0x100, 0x120 }, 140 { "INT34C3", 2, 175, 204, 0x100, 0x120 }, 141 { "INT34C3", 3, 205, 212, 0x100, 0x120 }, 142 143 /* Lakefield */ 144 { "INT34C4", 0, 0, 59, 0x100, 0x110 }, 145 { "INT34C4", 1, 60, 148, 0x100, 0x110 }, 146 { "INT34C4", 2, 149, 237, 0x100, 0x110 }, 147 { "INT34C4", 3, 238, 266, 0x100, 0x110 }, 148 149 /* Tiger Lake-LP */ 150 { "INT34C5", 0, 0, 66, 0x100, 0x120 }, 151 { "INT34C5", 1, 67, 170, 0x100, 0x120 }, 152 { "INT34C5", 2, 171, 259, 0x100, 0x120 }, 153 { "INT34C5", 3, 260, 276, 0x100, 0x120 }, 154 155 /* Alder Lake-P (Same as Tiger Lake-LP(INT34C5)) */ 156 { "INTC1055", 0, 0, 66, 0x100, 0x120 }, 157 { "INTC1055", 1, 67, 170, 0x100, 0x120 }, 158 { "INTC1055", 2, 171, 259, 0x100, 0x120 }, 159 { "INTC1055", 3, 260, 276, 0x100, 0x120 }, 160 161 /* Tiger Lake-H */ 162 { "INT34C6", 0, 0, 78, 0x100, 0x120 }, 163 { "INT34C6", 1, 79, 180, 0x100, 0x120 }, 164 { "INT34C6", 2, 181, 217, 0x100, 0x120 }, 165 { "INT34C6", 3, 218, 266, 0x100, 0x120 }, 166 { "INT34C6", 4, 267, 290, 0x100, 0x120 }, 167 168 /* Jasper Lake */ 169 { "INT34C8", 0, 0, 91, 0x100, 0x120 }, 170 { "INT34C8", 1, 92, 194, 0x100, 0x120 }, 171 { "INT34C8", 2, 195, 224, 0x100, 0x120 }, 172 { "INT34C8", 3, 225, 232, 0x100, 0x120 }, 173 174 /* Alder Lake-S */ 175 { "INTC1056", 0, 0, 94, 0x200, 0x220 }, 176 { "INTC1056", 1, 95, 150, 0x200, 0x220 }, 177 { "INTC1056", 2, 151, 199, 0x200, 0x220 }, 178 { "INTC1056", 3, 200, 269, 0x200, 0x220 }, 179 { "INTC1056", 4, 270, 303, 0x200, 0x220 }, 180 181 /* Alder Lake-N */ 182 { "INTC1057", 0, 0, 66, 0x100, 0x120 }, 183 { "INTC1057", 1, 67, 168, 0x100, 0x120 }, 184 { "INTC1057", 2, 169, 248, 0x100, 0x120 }, 185 { "INTC1057", 3, 249, 256, 0x100, 0x120 }, 186 187 /* Raptor Lake-S (Same as Alder Lake-S(INTC1056)) */ 188 { "INTC1085", 0, 0, 94, 0x200, 0x220 }, 189 { "INTC1085", 1, 95, 150, 0x200, 0x220 }, 190 { "INTC1085", 2, 151, 199, 0x200, 0x220 }, 191 { "INTC1085", 3, 200, 269, 0x200, 0x220 }, 192 { "INTC1085", 4, 270, 303, 0x200, 0x220 }, 193 194 /* Lewisburg */ 195 { "INT3536", 0, 0, 71, 0x100, 0x110 }, 196 { "INT3536", 1, 72, 132, 0x100, 0x110 }, 197 { "INT3536", 3, 133, 143, 0x100, 0x110 }, 198 { "INT3536", 4, 144, 178, 0x100, 0x110 }, 199 { "INT3536", 5, 179, 246, 0x100, 0x110 }, 200 201 /* Emmitsburg */ 202 { "INTC1071", 0, 0, 65, 0x200, 0x210 }, 203 { "INTC1071", 1, 66, 111, 0x200, 0x210 }, 204 { "INTC1071", 2, 112, 145, 0x200, 0x210 }, 205 { "INTC1071", 3, 146, 183, 0x200, 0x210 }, 206 { "INTC1071", 4, 184, 261, 0x200, 0x210 }, 207 208 /* Denverton */ 209 { "INTC3000", 0, 0, 40, 0x100, 0x120 }, 210 { "INTC3000", 1, 41, 153, 0x100, 0x120 }, 211 212 /* Cedarfork */ 213 { "INTC3001", 0, 0, 167, 0x200, 0x230 }, 214 { "INTC3001", 1, 168, 236, 0x200, 0x230 }, 215 216 /* Gemini Lake */ 217 { "INT3453", 0, 0, 34, 0x100, 0x110 }, 218 219 #ifdef notyet 220 /* 221 * BAR mappings not obvious, further studying required 222 */ 223 /* Broxton */ 224 { "apollolake-pinctrl", 0, 0, 0, 0x100, 0x110 }, 225 { "broxton-pinctrl", 0, 0, 0, 0x100, 0x110 }, 226 { "INT34D1", 0, 0, 0, 0x100, 0x110 }, 227 { "INT3452", 0, 0, 0, 0x100, 0x110 }, 228 229 /* Cherryview */ 230 { "INT33FF", 0, 0, 0, 0x000, 0x000 }, 231 #endif 232 233 { NULL, 0, 0, 0, 0x000, 0x000 }, 234 }; 235 236 struct igpio_pin_group igpio_pin_group[] = { 237 /* Sunrisepoint-LP */ 238 { "INT344B", 0, 0, "GPP_A" }, 239 { "INT344B", 1, 24, "GPP_B" }, 240 { "INT344B", 0, 48, "GPP_C" }, 241 { "INT344B", 1, 72, "GPP_D" }, 242 { "INT344B", 2, 96, "GPP_E" }, 243 { "INT344B", 0, 120, "GPP_F" }, 244 245 /* Coffee Lake-S (Same as Sunrisepoint-H(INT345D)) */ 246 { "INT3451", 0, 0, "GPP_A" }, 247 { "INT3451", 1, 24, "GPP_B" }, 248 { "INT3451", 0, 48, "GPP_C" }, 249 { "INT3451", 1, 72, "GPP_D" }, 250 { "INT3451", 2, 96, "GPP_E" }, 251 { "INT3451", 3, 109, "GPP_F" }, 252 { "INT3451", 4, 133, "GPP_G" }, 253 { "INT3451", 5, 157, "GPP_H" }, 254 { "INT3451", 0, 181, "GPP_I" }, 255 256 /* Sunrisepoint-H */ 257 { "INT345D", 0, 0, "GPP_A" }, 258 { "INT345D", 1, 24, "GPP_B" }, 259 { "INT345D", 0, 48, "GPP_C" }, 260 { "INT345D", 1, 72, "GPP_D" }, 261 { "INT345D", 2, 96, "GPP_E" }, 262 { "INT345D", 3, 109, "GPP_F" }, 263 { "INT345D", 4, 133, "GPP_G" }, 264 { "INT345D", 5, 157, "GPP_H" }, 265 { "INT345D", 0, 181, "GPP_I" }, 266 267 268 /* Baytrail */ 269 { "INT33B2", 0, 101, "A" }, 270 { "INT33FC", 0, 101, "A" }, 271 272 /* Lynxpoint */ 273 { "INT33C7", 0, 94, "A" }, 274 { "INT3437", 0, 94, "A" }, 275 276 /* Cannon Lake-H */ 277 { "INT3450", 0, 0, "GPP_A" }, 278 { "INT3450", 1, 25, "GPP_B" }, 279 { "INT3450", 0, 51, "GPP_C" }, 280 { "INT3450", 1, 75, "GPP_D" }, 281 { "INT3450", 2, 99, "GPP_G" }, 282 { "INT3450", 3, 107, "AZA" }, 283 { "INT3450", 4, 115, "vGPIO_0" }, 284 { "INT3450", 5, 147, "vGPIO_1" }, 285 { "INT3450", 0, 155, "GPP_K" }, 286 { "INT3450", 1, 179, "GPP_H" }, 287 { "INT3450", 2, 203, "GPP_E" }, 288 { "INT3450", 3, 216, "GPP_F" }, 289 { "INT3450", 4, 240, "SPI" }, 290 { "INT3450", 0, 249, "CPU" }, 291 { "INT3450", 1, 260, "JTAG" }, 292 { "INT3450", 2, 269, "GPP_I" }, 293 { "INT3450", 3, 287, "GPP_J" }, 294 295 /* Cannon Lake-LP */ 296 { "INT34BB", 0, 0, "GPP_A" }, 297 { "INT34BB", 1, 25, "GPP_B" }, 298 { "INT34BB", 2, 51, "GPP_G" }, 299 { "INT34BB", 3, 59, "SPI" }, 300 { "INT34BB", 0, 68, "GPP_D" }, 301 { "INT34BB", 1, 93, "GPP_F" }, 302 { "INT34BB", 2, 117, "GPP_H" }, 303 { "INT34BB", 3, 141, "vGPIO_0" }, 304 { "INT34BB", 4, 173, "vGPIO_1" }, 305 { "INT34BB", 0, 181, "GPP_C" }, 306 { "INT34BB", 1, 205, "GPP_E" }, 307 { "INT34BB", 2, 229, "JTAG" }, 308 { "INT34BB", 3, 238, "HVCMOS" }, 309 310 /* Ice Lake-LP */ 311 { "INT3455", 0, 0, "GPP_G" }, 312 { "INT3455", 1, 8, "GPP_B" }, 313 { "INT3455", 2, 34, "GPP_A" }, 314 { "INT3455", 0, 59, "GPP_H" }, 315 { "INT3455", 1, 83, "GPP_D" }, 316 { "INT3455", 2, 104, "GPP_F" }, 317 { "INT3455", 3, 124, "vGPIO" }, 318 { "INT3455", 0, 153, "GPP_C" }, 319 { "INT3455", 1, 177, "HVCMOS" }, 320 { "INT3455", 2, 183, "GPP_E" }, 321 { "INT3455", 3, 207, "JTAG" }, 322 { "INT3455", 0, 216, "GPP_R" }, 323 { "INT3455", 1, 224, "GPP_S" }, 324 { "INT3455", 2, 232, "SPI" }, 325 326 /* Ice Lake-N */ 327 { "INT34C3", 0, 0, "SPI" }, 328 { "INT34C3", 1, 9, "GPP_B" }, 329 { "INT34C3", 2, 35, "GPP_A" }, 330 { "INT34C3", 3, 56, "GPP_S" }, 331 { "INT34C3", 4, 64, "GPP_R" }, 332 { "INT34C3", 0, 72, "GPP_H" }, 333 { "INT34C3", 1, 96, "GPP_D" }, 334 { "INT34C3", 2, 122, "vGPIO" }, 335 { "INT34C3", 3, 151, "GPP_C" }, 336 { "INT34C3", 0, 175, "HVCMOS" }, 337 { "INT34C3", 1, 181, "GPP_E" }, 338 { "INT34C3", 0, 205, "GPP_G" }, 339 340 /* Lakefield */ 341 { "INT34C4", 0, 0, "EAST_0" }, 342 { "INT34C4", 1, 32, "EAST_1" }, 343 { "INT34C4", 0, 60, "NORTHWEST_0" }, 344 { "INT34C4", 1, 92, "NORTHWEST_1" }, 345 { "INT34C4", 2, 124, "NORTHWEST_2" }, 346 { "INT34C4", 0, 149, "WEST_0" }, 347 { "INT34C4", 1, 181, "WEST_1" }, 348 { "INT34C4", 2, 213, "WEST_2" }, 349 { "INT34C4", 0, 238, "SOUTHEAST" }, 350 351 /* Tiger Lake-LP */ 352 { "INT34C5", 0, 0, "GPP_B" }, 353 { "INT34C5", 1, 26, "GPP_T" }, 354 { "INT34C5", 2, 42, "GPP_A" }, 355 { "INT34C5", 0, 67, "GPP_S" }, 356 { "INT34C5", 1, 75, "GPP_H" }, 357 { "INT34C5", 2, 99, "GPP_D" }, 358 { "INT34C5", 3, 120, "GPP_U" }, 359 { "INT34C5", 4, 144, "vGPIO" }, 360 { "INT34C5", 0, 171, "GPP_C" }, 361 { "INT34C5", 1, 195, "GPP_F" }, 362 { "INT34C5", 2, 220, "HVCMOS" }, 363 { "INT34C5", 3, 226, "GPP_E" }, 364 { "INT34C5", 4, 251, "JTAG" }, 365 { "INT34C5", 0, 260, "GPP_R" }, 366 { "INT34C5", 1, 268, "SPI" }, 367 368 /* Alder Lake-P (Same as Tiger Lake-LP(INT34C5)) */ 369 { "INTC1055", 0, 0, "GPP_B" }, 370 { "INTC1055", 1, 26, "GPP_T" }, 371 { "INTC1055", 2, 42, "GPP_A" }, 372 { "INTC1055", 0, 67, "GPP_S" }, 373 { "INTC1055", 1, 75, "GPP_H" }, 374 { "INTC1055", 2, 99, "GPP_D" }, 375 { "INTC1055", 3, 120, "GPP_U" }, 376 { "INTC1055", 4, 144, "vGPIO" }, 377 { "INTC1055", 0, 171, "GPP_C" }, 378 { "INTC1055", 1, 195, "GPP_F" }, 379 { "INTC1055", 2, 220, "HVCMOS" }, 380 { "INTC1055", 3, 226, "GPP_E" }, 381 { "INTC1055", 4, 251, "JTAG" }, 382 { "INTC1055", 0, 260, "GPP_R" }, 383 { "INTC1055", 1, 268, "SPI" }, 384 385 /* Tiger Lake-H */ 386 { "INT34C6", 0, 0, "GPP_A" }, 387 { "INT34C6", 1, 25, "GPP_R" }, 388 { "INT34C6", 2, 45, "GPP_B" }, 389 { "INT34C6", 3, 71, "vGPIO_0" }, 390 { "INT34C6", 0, 79, "GPP_D" }, 391 { "INT34C6", 1, 105, "GPP_C" }, 392 { "INT34C6", 2, 129, "GPP_S" }, 393 { "INT34C6", 3, 137, "GPP_G" }, 394 { "INT34C6", 4, 154, "vGPIO" }, 395 { "INT34C6", 0, 181, "GPP_E" }, 396 { "INT34C6", 1, 194, "GPP_F" }, 397 { "INT34C6", 0, 218, "GPP_H" }, 398 { "INT34C6", 1, 242, "GPP_J" }, 399 { "INT34C6", 2, 252, "GPP_K" }, 400 { "INT34C6", 0, 267, "GPP_I" }, 401 { "INT34C6", 1, 282, "JTAG" }, 402 403 /* Jasper Lake */ 404 { "INT34C8", 0, 0, "GPP_F" }, 405 { "INT34C8", 1, 20, "SPI" }, 406 { "INT34C8", 2, 29, "GPP_B" }, 407 { "INT34C8", 3, 55, "GPP_A" }, 408 { "INT34C8", 4, 76, "GPP_S" }, 409 { "INT34C8", 5, 84, "GPP_R" }, 410 { "INT34C8", 0, 92, "GPP_H" }, 411 { "INT34C8", 1, 116, "GPP_D" }, 412 { "INT34C8", 2, 142, "vGPIO" }, 413 { "INT34C8", 3, 171, "GPP_C" }, 414 { "INT34C8", 0, 195, "HVCMOS" }, 415 { "INT34C8", 1, 201, "GPP_E" }, 416 { "INT34C8", 0, 225, "GPP_G" }, 417 418 /* Alder Lake-S */ 419 { "INTC1056", 0, 0, "GPP_I" }, 420 { "INTC1056", 1, 25, "GPP_R" }, 421 { "INTC1056", 2, 48, "GPP_J" }, 422 { "INTC1056", 3, 60, "vGPIO" }, 423 { "INTC1056", 4, 87, "vGPIO_0" }, 424 { "INTC1056", 0, 95, "GPP_B" }, 425 { "INTC1056", 1, 119, "GPP_G" }, 426 { "INTC1056", 2, 127, "GPP_H" }, 427 { "INTC1056", 0, 151, "SPI0" }, 428 { "INTC1056", 1, 160, "GPP_A" }, 429 { "INTC1056", 2, 176, "GPP_C" }, 430 { "INTC1056", 0, 200, "GPP_S" }, 431 { "INTC1056", 1, 208, "GPP_E" }, 432 { "INTC1056", 2, 231, "GPP_K" }, 433 { "INTC1056", 3, 246, "GPP_F" }, 434 { "INTC1056", 0, 270, "GPP_D" }, 435 { "INTC1056", 1, 295, "JTAG" }, 436 437 /* Alder Lake-N */ 438 { "INTC1057", 0, 0, "GPP_B" }, 439 { "INTC1057", 1, 26, "GPP_T" }, 440 { "INTC1057", 2, 42, "GPP_A" }, 441 { "INTC1057", 0, 67, "GPP_S" }, 442 { "INTC1057", 1, 75, "GPP_I" }, 443 { "INTC1057", 2, 95, "GPP_H" }, 444 { "INTC1057", 3, 119, "GPP_D" }, 445 { "INTC1057", 4, 140, "vGPIO" }, 446 { "INTC1057", 0, 169, "GPP_C" }, 447 { "INTC1057", 1, 193, "GPP_F" }, 448 { "INTC1057", 2, 218, "HVCMOS" }, 449 { "INTC1057", 3, 224, "GPP_E" }, 450 { "INTC1057", 0, 249, "GPP_R" }, 451 452 /* Raptor Lake-S (Same as Alder Lake-S(INTC1056)) */ 453 { "INTC1085", 0, 0, "GPP_I" }, 454 { "INTC1085", 1, 25, "GPP_R" }, 455 { "INTC1085", 2, 48, "GPP_J" }, 456 { "INTC1085", 3, 60, "vGPIO" }, 457 { "INTC1085", 4, 87, "vGPIO_0" }, 458 { "INTC1085", 0, 95, "GPP_B" }, 459 { "INTC1085", 1, 119, "GPP_G" }, 460 { "INTC1085", 2, 127, "GPP_H" }, 461 { "INTC1085", 0, 151, "SPI0" }, 462 { "INTC1085", 1, 160, "GPP_A" }, 463 { "INTC1085", 2, 176, "GPP_C" }, 464 { "INTC1085", 0, 200, "GPP_S" }, 465 { "INTC1085", 1, 208, "GPP_E" }, 466 { "INTC1085", 2, 231, "GPP_K" }, 467 { "INTC1085", 3, 246, "GPP_F" }, 468 { "INTC1085", 0, 270, "GPP_D" }, 469 { "INTC1085", 1, 295, "JTAG" }, 470 471 /* Lewisburg */ 472 { "INT3536", 0, 0, "" }, 473 474 /* Emmitsburg */ 475 { "INTC1071", 0, 0, "GPP_A" }, 476 { "INTC1071", 1, 21, "GPP_B" }, 477 { "INTC1071", 2, 45, "SPI" }, 478 { "INTC1071", 0, 66, "GPP_C" }, 479 { "INTC1071", 1, 88, "GPP_D" }, 480 { "INTC1071", 0, 112, "GPP_E" }, 481 { "INTC1071", 1, 136, "JTAG" }, 482 { "INTC1071", 0, 146, "GPP_H" }, 483 { "INTC1071", 1, 166, "GPP_J" }, 484 { "INTC1071", 0, 184, "GPP_I" }, 485 { "INTC1071", 1, 208, "GPP_L" }, 486 { "INTC1071", 2, 226, "GPP_M" }, 487 { "INTC1071", 3, 244, "GPP_N" }, 488 489 /* Denverton */ 490 { "INTC3000", 0, 0, "North_ALL_0" }, 491 { "INTC3000", 1, 32, "North_ALL_1" }, 492 { "INTC3000", 0, 41, "South_DFX" }, 493 { "INTC3000", 1, 59, "South_GPP0_0" }, 494 { "INTC3000", 2, 91, "South_GPP0_1" }, 495 { "INTC3000", 3, 112, "South_GPP1_0" }, 496 { "INTC3000", 4, 144, "South_GPP1_1" }, 497 498 /* Cedarfork */ 499 { "INTC3001", 0, 0, "WEST2" }, 500 { "INTC3001", 1, 24, "WEST3" }, 501 { "INTC3001", 2, 48, "WEST01" }, 502 { "INTC3001", 3, 71, "WEST5" }, 503 { "INTC3001", 4, 91, "WESTC" }, 504 { "INTC3001", 5, 97, "WESTC_DFX" }, 505 { "INTC3001", 6, 102, "WESTA" }, 506 { "INTC3001", 7, 112, "WESTB" }, 507 { "INTC3001", 8, 124, "WESTD" }, 508 { "INTC3001", 9, 144, "WESTD_PECI" }, 509 { "INTC3001", 10, 145, "WESTF" }, 510 { "INTC3001", 0, 168, "EAST2" }, 511 { "INTC3001", 1, 192, "EAST3" }, 512 { "INTC3001", 2, 203, "EAST0" }, 513 { "INTC3001", 3, 226, "EMMC" }, 514 515 /* Gemini Lake */ 516 { "INT3453", 0, 34, "" }, 517 518 #ifdef notyet 519 /* 520 * BAR mappings not obvious, further studying required 521 */ 522 /* Broxton */ 523 { "apollolake-pinctrl", 0, 0, "" }, 524 { "broxton-pinctrl", 0, 0, "" }, 525 { "INT34D1", 0, 0, "" }, 526 { "INT3452", 0, 0, "" }, 527 528 /* Cherryview */ 529 { "INT33FF", 0, 0, "" }, 530 #endif 531 532 { NULL, 0, 0, 0 }, 533 }; 534 535 #endif /* _IGPIOREG_H */ 536
Indexes created Sat Sep 20 22:09:52 GMT 2025